From: Baolu Lu <baolu.lu@linux.intel.com> To: "Tian, Kevin" <kevin.tian@intel.com>, Joerg Roedel <joro@8bytes.org>, Jason Gunthorpe <jgg@nvidia.com>, Christoph Hellwig <hch@infradead.org>, "Raj, Ashok" <ashok.raj@intel.com>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Jean-Philippe Brucker <jean-philippe@linaro.com>, "Jiang, Dave" <dave.jiang@intel.com>, Vinod Koul <vkoul@kernel.org> Cc: baolu.lu@linux.intel.com, Eric Auger <eric.auger@redhat.com>, "Liu, Yi L" <yi.l.liu@intel.com>, "Pan, Jacob jun" <jacob.jun.pan@intel.com>, "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Jean-Philippe Brucker <jean-philippe@linaro.org> Subject: Re: [PATCH v7 01/10] iommu: Add pasids field in struct iommu_device Date: Wed, 25 May 2022 10:03:26 +0800 [thread overview] Message-ID: <3c112762-f6e6-0b41-b38f-3bb2995d97cf@linux.intel.com> (raw) In-Reply-To: <BN9PR11MB52766D61BBE784A70B4BF06F8CD79@BN9PR11MB5276.namprd11.prod.outlook.com> Hi Kevin, Thank you for reviewing my patches. On 2022/5/24 17:24, Tian, Kevin wrote: >> From: Lu Baolu <baolu.lu@linux.intel.com> >> Sent: Thursday, May 19, 2022 3:21 PM >> >> Use this field to keep the number of supported PASIDs that an IOMMU >> hardware is able to support. This is a generic attribute of an IOMMU >> and lifting it into the per-IOMMU device structure makes it possible >> to allocate a PASID for device without calls into the IOMMU drivers. >> Any iommu driver which suports PASID related features should set this >> field before enabling them on the devices. >> >> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> >> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> >> --- >> include/linux/iommu.h | 2 ++ >> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + >> drivers/iommu/intel/dmar.c | 4 ++++ >> 3 files changed, 7 insertions(+) >> >> diff --git a/include/linux/iommu.h b/include/linux/iommu.h >> index 5e1afe169549..da423e87f248 100644 >> --- a/include/linux/iommu.h >> +++ b/include/linux/iommu.h >> @@ -318,12 +318,14 @@ struct iommu_domain_ops { >> * @list: Used by the iommu-core to keep a list of registered iommus >> * @ops: iommu-ops for talking to this iommu >> * @dev: struct device for sysfs handling >> + * @pasids: number of supported PASIDs >> */ >> struct iommu_device { >> struct list_head list; >> const struct iommu_ops *ops; >> struct fwnode_handle *fwnode; >> struct device *dev; >> + u32 pasids; > > max_pasid or nr_pasids? max_pasid looks better. > >> }; >> >> /** >> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> index 88817a3376ef..6e2cd082c670 100644 >> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> @@ -3546,6 +3546,7 @@ static int arm_smmu_device_hw_probe(struct >> arm_smmu_device *smmu) >> /* SID/SSID sizes */ >> smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); >> smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); >> + smmu->iommu.pasids = smmu->ssid_bits; >> >> /* >> * If the SMMU supports fewer bits than would fill a single L2 stream >> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c >> index 4de960834a1b..1c3cf267934d 100644 >> --- a/drivers/iommu/intel/dmar.c >> +++ b/drivers/iommu/intel/dmar.c >> @@ -1126,6 +1126,10 @@ static int alloc_iommu(struct dmar_drhd_unit >> *drhd) >> >> raw_spin_lock_init(&iommu->register_lock); >> >> + /* Supports full 20-bit PASID in scalable mode. */ >> + if (ecap_pasid(iommu->ecap)) >> + iommu->iommu.pasids = 1UL << 20; >> + > > supported pasid bits is reported by ecap_pss(). I don't think we should > assume 20bits here. Yes. I overlooked this. Thanks for reminding. Another thing I need to improve is that scalable mode could be disabled. This field should be 0 in that case. > >> /* >> * This is only for hotplug; at boot time intel_iommu_enabled won't >> * be set yet. When intel_iommu_init() runs, it registers the units >> -- >> 2.25.1 > Best regards, baolu
WARNING: multiple messages have this Message-ID (diff)
From: Baolu Lu <baolu.lu@linux.intel.com> To: "Tian, Kevin" <kevin.tian@intel.com>, Joerg Roedel <joro@8bytes.org>, Jason Gunthorpe <jgg@nvidia.com>, Christoph Hellwig <hch@infradead.org>, "Raj, Ashok" <ashok.raj@intel.com>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Jean-Philippe Brucker <jean-philippe@linaro.com>, "Jiang, Dave" <dave.jiang@intel.com>, Vinod Koul <vkoul@kernel.org> Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>, "Pan, Jacob jun" <jacob.jun.pan@intel.com> Subject: Re: [PATCH v7 01/10] iommu: Add pasids field in struct iommu_device Date: Wed, 25 May 2022 10:03:26 +0800 [thread overview] Message-ID: <3c112762-f6e6-0b41-b38f-3bb2995d97cf@linux.intel.com> (raw) In-Reply-To: <BN9PR11MB52766D61BBE784A70B4BF06F8CD79@BN9PR11MB5276.namprd11.prod.outlook.com> Hi Kevin, Thank you for reviewing my patches. On 2022/5/24 17:24, Tian, Kevin wrote: >> From: Lu Baolu <baolu.lu@linux.intel.com> >> Sent: Thursday, May 19, 2022 3:21 PM >> >> Use this field to keep the number of supported PASIDs that an IOMMU >> hardware is able to support. This is a generic attribute of an IOMMU >> and lifting it into the per-IOMMU device structure makes it possible >> to allocate a PASID for device without calls into the IOMMU drivers. >> Any iommu driver which suports PASID related features should set this >> field before enabling them on the devices. >> >> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> >> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> >> --- >> include/linux/iommu.h | 2 ++ >> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + >> drivers/iommu/intel/dmar.c | 4 ++++ >> 3 files changed, 7 insertions(+) >> >> diff --git a/include/linux/iommu.h b/include/linux/iommu.h >> index 5e1afe169549..da423e87f248 100644 >> --- a/include/linux/iommu.h >> +++ b/include/linux/iommu.h >> @@ -318,12 +318,14 @@ struct iommu_domain_ops { >> * @list: Used by the iommu-core to keep a list of registered iommus >> * @ops: iommu-ops for talking to this iommu >> * @dev: struct device for sysfs handling >> + * @pasids: number of supported PASIDs >> */ >> struct iommu_device { >> struct list_head list; >> const struct iommu_ops *ops; >> struct fwnode_handle *fwnode; >> struct device *dev; >> + u32 pasids; > > max_pasid or nr_pasids? max_pasid looks better. > >> }; >> >> /** >> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> index 88817a3376ef..6e2cd082c670 100644 >> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> @@ -3546,6 +3546,7 @@ static int arm_smmu_device_hw_probe(struct >> arm_smmu_device *smmu) >> /* SID/SSID sizes */ >> smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); >> smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); >> + smmu->iommu.pasids = smmu->ssid_bits; >> >> /* >> * If the SMMU supports fewer bits than would fill a single L2 stream >> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c >> index 4de960834a1b..1c3cf267934d 100644 >> --- a/drivers/iommu/intel/dmar.c >> +++ b/drivers/iommu/intel/dmar.c >> @@ -1126,6 +1126,10 @@ static int alloc_iommu(struct dmar_drhd_unit >> *drhd) >> >> raw_spin_lock_init(&iommu->register_lock); >> >> + /* Supports full 20-bit PASID in scalable mode. */ >> + if (ecap_pasid(iommu->ecap)) >> + iommu->iommu.pasids = 1UL << 20; >> + > > supported pasid bits is reported by ecap_pss(). I don't think we should > assume 20bits here. Yes. I overlooked this. Thanks for reminding. Another thing I need to improve is that scalable mode could be disabled. This field should be 0 in that case. > >> /* >> * This is only for hotplug; at boot time intel_iommu_enabled won't >> * be set yet. When intel_iommu_init() runs, it registers the units >> -- >> 2.25.1 > Best regards, baolu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2022-05-25 2:03 UTC|newest] Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-19 7:20 [PATCH v7 00/10] iommu: SVA and IOPF refactoring Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 7:20 ` [PATCH v7 01/10] iommu: Add pasids field in struct iommu_device Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 10:37 ` Jean-Philippe Brucker 2022-05-19 10:37 ` Jean-Philippe Brucker 2022-05-19 11:55 ` Baolu Lu 2022-05-19 11:55 ` Baolu Lu 2022-05-24 9:24 ` Tian, Kevin 2022-05-24 9:24 ` Tian, Kevin 2022-05-25 2:03 ` Baolu Lu [this message] 2022-05-25 2:03 ` Baolu Lu 2022-05-25 2:13 ` Baolu Lu 2022-05-25 2:13 ` Baolu Lu 2022-05-19 7:20 ` [PATCH v7 02/10] iommu: Remove SVM_FLAG_SUPERVISOR_MODE support Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 16:22 ` Jean-Philippe Brucker 2022-05-19 16:22 ` Jean-Philippe Brucker 2022-05-24 9:27 ` Tian, Kevin 2022-05-24 9:27 ` Tian, Kevin 2022-05-19 7:20 ` [PATCH v7 03/10] iommu/sva: Add iommu_sva_domain support Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 16:33 ` Jean-Philippe Brucker 2022-05-19 16:33 ` Jean-Philippe Brucker 2022-05-20 4:55 ` Baolu Lu 2022-05-20 4:55 ` Baolu Lu 2022-05-23 7:12 ` Baolu Lu 2022-05-23 7:12 ` Baolu Lu 2022-05-24 9:44 ` Tian, Kevin 2022-05-24 9:44 ` Tian, Kevin 2022-05-25 2:18 ` Baolu Lu 2022-05-25 2:18 ` Baolu Lu 2022-05-24 9:39 ` Tian, Kevin 2022-05-24 9:39 ` Tian, Kevin 2022-05-24 13:38 ` Jason Gunthorpe 2022-05-24 13:38 ` Jason Gunthorpe via iommu 2022-05-25 0:44 ` Tian, Kevin 2022-05-25 0:44 ` Tian, Kevin 2022-05-25 2:38 ` Baolu Lu 2022-05-25 2:38 ` Baolu Lu 2022-05-25 4:50 ` Baolu Lu 2022-05-25 4:50 ` Baolu Lu 2022-05-24 13:44 ` Jason Gunthorpe 2022-05-24 13:44 ` Jason Gunthorpe via iommu 2022-05-25 5:19 ` Baolu Lu 2022-05-25 5:19 ` Baolu Lu 2022-05-25 15:25 ` Jason Gunthorpe 2022-05-25 15:25 ` Jason Gunthorpe via iommu 2022-05-26 1:03 ` Baolu Lu 2022-05-26 1:03 ` Baolu Lu 2022-05-25 5:33 ` Baolu Lu 2022-05-25 5:33 ` Baolu Lu 2022-05-24 14:36 ` Robin Murphy 2022-05-24 14:36 ` Robin Murphy 2022-05-25 6:20 ` Baolu Lu 2022-05-25 6:20 ` Baolu Lu 2022-05-25 10:07 ` Robin Murphy 2022-05-25 10:07 ` Robin Murphy 2022-05-25 11:06 ` Jean-Philippe Brucker 2022-05-25 11:06 ` Jean-Philippe Brucker 2022-05-25 13:11 ` Baolu Lu 2022-05-25 13:11 ` Baolu Lu 2022-05-19 7:20 ` [PATCH v7 04/10] iommu/vt-d: Add SVA domain support Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 7:20 ` [PATCH v7 05/10] arm-smmu-v3/sva: " Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 16:37 ` Jean-Philippe Brucker 2022-05-19 16:37 ` Jean-Philippe Brucker 2022-05-19 7:20 ` [PATCH v7 06/10] iommu/sva: Refactoring iommu_sva_bind/unbind_device() Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 16:39 ` Jean-Philippe Brucker 2022-05-19 16:39 ` Jean-Philippe Brucker 2022-05-20 6:38 ` Baolu Lu 2022-05-20 6:38 ` Baolu Lu 2022-05-20 11:28 ` Jean-Philippe Brucker 2022-05-20 11:28 ` Jean-Philippe Brucker 2022-05-23 3:07 ` Baolu Lu 2022-05-23 3:07 ` Baolu Lu 2022-05-24 10:22 ` Tian, Kevin 2022-05-24 10:22 ` Tian, Kevin 2022-05-24 10:57 ` Jean-Philippe Brucker 2022-05-24 10:57 ` Jean-Philippe Brucker 2022-05-25 2:04 ` Tian, Kevin 2022-05-25 2:04 ` Tian, Kevin 2022-05-25 7:29 ` Jean-Philippe Brucker 2022-05-25 7:29 ` Jean-Philippe Brucker 2022-06-02 6:46 ` Tian, Kevin 2022-06-02 6:46 ` Tian, Kevin 2022-05-19 7:20 ` [PATCH v7 07/10] iommu: Remove SVA related callbacks from iommu ops Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-24 10:23 ` Tian, Kevin 2022-05-24 10:23 ` Tian, Kevin 2022-05-19 7:20 ` [PATCH v7 08/10] iommu: Prepare IOMMU domain for IOPF Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 16:40 ` Jean-Philippe Brucker 2022-05-19 16:40 ` Jean-Philippe Brucker 2022-05-19 7:20 ` [PATCH v7 09/10] iommu: Per-domain I/O page fault handling Lu Baolu 2022-05-19 7:20 ` Lu Baolu 2022-05-19 7:20 ` [PATCH v7 10/10] iommu: Rename iommu-sva-lib.{c,h} Lu Baolu 2022-05-19 7:20 ` Lu Baolu
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