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From: "H. Peter Anvin" <h.peter.anvin@intel.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
	"H. Peter Anvin" <hpa@linux.intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	"Bae, Chang Seok" <chang.seok.bae@intel.com>,
	"Metzger, Markus T" <markus.t.metzger@intel.com>
Subject: Re: [PATCH v3 1/7] x86/ldt: refresh %fs and %gs in refresh_ldt_segments()
Date: Fri, 22 Jun 2018 11:29:45 -0700	[thread overview]
Message-ID: <408ed97a-c64d-c523-c403-4e066d1f34c3@intel.com> (raw)
In-Reply-To: <CALCETrWerhEUMw+JS4p5MVEopiMnUjbUtX58Ci7UYfYT=Y5Cvw@mail.gmail.com>

On 06/22/18 07:24, Andy Lutomirski wrote:
> 
> That RPL3 part is false.  The following program does:
> 
> #include <stdio.h>
> 
> int main()
> {
>     unsigned short sel;
>     asm volatile ("mov %%ss, %0" : "=rm" (sel));
>     sel &= ~3;
>     printf("Will write 0x%hx to GS\n", sel);
>     asm volatile ("mov %0, %%gs" :: "rm" (sel & ~3));
>     asm volatile ("mov %%gs, %0" : "=rm" (sel));
>     printf("GS = 0x%hx\n", sel);
>     return 0;
> }
> 
> prints:
> 
> Will write 0x28 to GS
> GS = 0x28
> 
> The x86 architecture is *insane*.
> 
> Other than that, this patch seems generally sensible.  But my
> objection that it's incorrect with FSGSBASE enabled for %fs and %gs
> still applies.
> 

Ugh, you're right... I misremembered.  The CPL simply overrides the RPL
rather than trapping.

We still need to give legacy applications which have zero idea about the
separate bases that apply only to 64-bit mode a way to DTRT.  Requiring
these old crufty applications to do something new is not an option.

As ugly as it is, I'm thinking the Right Thing is to simply make it a
part of the Linux ABI that if the FS or GS selector registers point into
the LDT then we will requalify them; if a 64-bit app does that then they
get that behavior.  This isn't something that will happen
asynchronously, and if a 64-bit process loads an LDT value into FS or
GS, they are considered to have opted in to that behavior.

The only other sensible option is to conditionalize this on the affected
process being in !64-bit mode.  I don't like that myself.

	-hpa

  reply	other threads:[~2018-06-22 18:29 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-21 21:17 [PATCH v3 0/7] x86/ptrace: regset access to the GDT and LDT H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 1/7] x86/ldt: refresh %fs and %gs in refresh_ldt_segments() H. Peter Anvin, Intel
2018-06-22 14:24   ` Andy Lutomirski
2018-06-22 18:29     ` H. Peter Anvin [this message]
2018-06-22 18:47       ` Andy Lutomirski
2018-06-27 18:19         ` Andy Lutomirski
2018-06-27 18:22           ` hpa
2018-06-27 18:33             ` hpa
2018-06-28 20:33             ` Andy Lutomirski
2018-06-28 20:39               ` hpa
2018-06-21 21:17 ` [PATCH v3 2/7] x86/ldt: use a common value for read_default_ldt() H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 3/7] x86: move fill_user_desc() from tls.c to desc.h and add validity check H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 4/7] x86/tls: create an explicit config symbol for the TLS area in the GDT H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 5/7] x86/segment: add #define for the last user-visible GDT slot H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 6/7] x86/tls,ptrace: provide regset access to the GDT H. Peter Anvin, Intel
2018-06-22 14:43   ` Andy Lutomirski
2018-06-21 21:17 ` [PATCH v3 7/7] x86/ldt,ptrace: provide regset access to the LDT H. Peter Anvin, Intel
2018-06-22 14:49   ` Andy Lutomirski
2018-06-22 15:05     ` hpa
2018-06-22 15:30       ` Andy Lutomirski
2018-06-22  1:58 ` [PATCH v3 0/7] x86/ptrace: regset access to the GDT and LDT Ingo Molnar
2018-06-22  2:25   ` hpa

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