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From: Andy Lutomirski <luto@kernel.org>
To: "H. Peter Anvin" <h.peter.anvin@intel.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
	"H. Peter Anvin" <hpa@linux.intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Andrew Lutomirski <luto@kernel.org>,
	"Bae, Chang Seok" <chang.seok.bae@intel.com>,
	"Metzger, Markus T" <markus.t.metzger@intel.com>
Subject: Re: [PATCH v3 1/7] x86/ldt: refresh %fs and %gs in refresh_ldt_segments()
Date: Fri, 22 Jun 2018 07:24:56 -0700	[thread overview]
Message-ID: <CALCETrWerhEUMw+JS4p5MVEopiMnUjbUtX58Ci7UYfYT=Y5Cvw@mail.gmail.com> (raw)
In-Reply-To: <20180621211754.12757-2-h.peter.anvin@intel.com>

On Thu, Jun 21, 2018 at 2:18 PM H. Peter Anvin, Intel
<h.peter.anvin@intel.com> wrote:
>
> From: "H. Peter Anvin" <hpa@linux.intel.com>
>
> It is not only %ds and %es which contain cached user descriptor
> information, %fs and %gs do as well.
>
> To make sure we don't do something stupid that will affect processes
> which wouldn't want this requalification, be more restrictive about
> which selector numbers will be requalified: they need to be LDT
> selectors (which by definition are never null), have an RPL of 3
> (always the case in user space unless null), and match the updated
> descriptor.

That RPL3 part is false.  The following program does:

#include <stdio.h>

int main()
{
    unsigned short sel;
    asm volatile ("mov %%ss, %0" : "=rm" (sel));
    sel &= ~3;
    printf("Will write 0x%hx to GS\n", sel);
    asm volatile ("mov %0, %%gs" :: "rm" (sel & ~3));
    asm volatile ("mov %%gs, %0" : "=rm" (sel));
    printf("GS = 0x%hx\n", sel);
    return 0;
}

prints:

Will write 0x28 to GS
GS = 0x28

The x86 architecture is *insane*.

Other than that, this patch seems generally sensible.  But my
objection that it's incorrect with FSGSBASE enabled for %fs and %gs
still applies.

  reply	other threads:[~2018-06-22 14:25 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-21 21:17 [PATCH v3 0/7] x86/ptrace: regset access to the GDT and LDT H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 1/7] x86/ldt: refresh %fs and %gs in refresh_ldt_segments() H. Peter Anvin, Intel
2018-06-22 14:24   ` Andy Lutomirski [this message]
2018-06-22 18:29     ` H. Peter Anvin
2018-06-22 18:47       ` Andy Lutomirski
2018-06-27 18:19         ` Andy Lutomirski
2018-06-27 18:22           ` hpa
2018-06-27 18:33             ` hpa
2018-06-28 20:33             ` Andy Lutomirski
2018-06-28 20:39               ` hpa
2018-06-21 21:17 ` [PATCH v3 2/7] x86/ldt: use a common value for read_default_ldt() H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 3/7] x86: move fill_user_desc() from tls.c to desc.h and add validity check H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 4/7] x86/tls: create an explicit config symbol for the TLS area in the GDT H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 5/7] x86/segment: add #define for the last user-visible GDT slot H. Peter Anvin, Intel
2018-06-21 21:17 ` [PATCH v3 6/7] x86/tls,ptrace: provide regset access to the GDT H. Peter Anvin, Intel
2018-06-22 14:43   ` Andy Lutomirski
2018-06-21 21:17 ` [PATCH v3 7/7] x86/ldt,ptrace: provide regset access to the LDT H. Peter Anvin, Intel
2018-06-22 14:49   ` Andy Lutomirski
2018-06-22 15:05     ` hpa
2018-06-22 15:30       ` Andy Lutomirski
2018-06-22  1:58 ` [PATCH v3 0/7] x86/ptrace: regset access to the GDT and LDT Ingo Molnar
2018-06-22  2:25   ` hpa

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