* [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups
@ 2019-04-09 19:02 Simon Goldschmidt
2019-04-09 19:02 ` [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout Simon Goldschmidt
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Simon Goldschmidt @ 2019-04-09 19:02 UTC (permalink / raw)
To: u-boot
This series cleans up stack definitions in socfpga_common.h as well as
cleans up defconfig files by implying/defaulting common things in Kconfig
files.
Finally, it reduces the malloc pool size used in first stage of gen5 SPL
(without ddr available) in order to have more space available for code.
As this series does not contain direct bugfixes, it targets the
socfpga-next branch.
Note that this series is meant for socfpga-next but depends on the generic
series "spl: full-featured heap cleanups" from:
https://patchwork.ozlabs.org/project/uboot/list/?series=99561
Changes in v4:
- make this patch 2/4 work without changing a10 heap allocation strategy
(as the series doing that has been rejected)
- adapt to socfpga-next
Changes in v3:
- removed patch 2/5 from v2 (moved to patchwork #1067366, series #99561)
- adapt to socfpge-next: imply USE_TINY_PRINTF only for gen5 & a10,
not s10
- adapt to socfpga-next
Changes in v2:
- fix commit message: "SPL post-reloc", not "SPL pre-reloc"
- added patch to imply/default common config options
- added patch to reduce gen5 SPL initial malloc pool to 2 KiB
Simon Goldschmidt (4):
arm: socfpga: fix comment about SPL memory layout
arm: socfpga: put initial U-Boot stack into DDR
arm: socfpga: imply/default common config options
arm: socfpga: gen5: reduce SPL pre-reloc malloc
arch/arm/Kconfig | 2 ++
arch/arm/mach-socfpga/Kconfig | 23 ++++++++++++
configs/socfpga_arria10_defconfig | 6 ----
configs/socfpga_arria5_defconfig | 10 ------
configs/socfpga_cyclone5_defconfig | 10 ------
configs/socfpga_dbm_soc1_defconfig | 10 ------
configs/socfpga_de0_nano_soc_defconfig | 10 ------
configs/socfpga_de10_nano_defconfig | 10 ------
configs/socfpga_de1_soc_defconfig | 10 ------
configs/socfpga_is1_defconfig | 8 -----
configs/socfpga_sockit_defconfig | 10 ------
configs/socfpga_socrates_defconfig | 10 ------
configs/socfpga_sr1500_defconfig | 10 ------
configs/socfpga_stratix10_defconfig | 2 --
configs/socfpga_vining_fpga_defconfig | 10 ------
include/configs/socfpga_common.h | 48 ++++++++++++--------------
16 files changed, 48 insertions(+), 141 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout
2019-04-09 19:02 [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Simon Goldschmidt
@ 2019-04-09 19:02 ` Simon Goldschmidt
2019-04-09 19:33 ` Marek Vasut
2019-04-09 19:02 ` [U-Boot] [PATCH v4 2/4] arm: socfpga: put initial U-Boot stack into DDR Simon Goldschmidt
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Simon Goldschmidt @ 2019-04-09 19:02 UTC (permalink / raw)
To: u-boot
The comment about SPL memory layout for socfpga gen5 is outdated: the
initial malloc memory is now at the end of the SRAM, gd is below it
(see board_init_f_alloc_reserve).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/socfpga_common.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f9e2cdc1b3..32ee7426b6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -236,9 +236,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
- * 0xFFFF_yyyy ...... Malloc area
- * 0xFFFF_zzzz ...... Global Data
- * 0xFFFF_FF00 ...... End of SRAM
+ * 0xFFFF_yyyy ...... Global Data
+ * 0xFFFF_zzzz ...... Malloc area
+ * 0xFFFF_FFFF ...... End of SRAM
*
* SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom)
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 2/4] arm: socfpga: put initial U-Boot stack into DDR
2019-04-09 19:02 [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Simon Goldschmidt
2019-04-09 19:02 ` [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout Simon Goldschmidt
@ 2019-04-09 19:02 ` Simon Goldschmidt
2019-04-09 19:34 ` Marek Vasut
2019-04-09 19:02 ` [U-Boot] [PATCH v4 3/4] arm: socfpga: imply/default common config options Simon Goldschmidt
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Simon Goldschmidt @ 2019-04-09 19:02 UTC (permalink / raw)
To: u-boot
If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to
do that, too.
The reason to do so is that this way, U-Boot initial stack can be larger
than SPL initial stack. In situations where we want to save the SPL
in SRAM for next boot without reloading, this prevents overwriting the
SPL DTB in SRAM if U-Boot stack usage gets too high.
To achieve this, the malloc definition for a10 is moved up and sligthly
changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v4:
- make this patch 2/4 work without changing a10 heap allocation strategy
(as the series doing that has been rejected)
Changes in v3:
- removed patch 2/5 from v2 (moved to patchwork #1067366, series #99561)
Changes in v2:
- fix commit message: "SPL post-reloc", not "SPL pre-reloc"
include/configs/socfpga_common.h | 42 +++++++++++++++-----------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 32ee7426b6..a501b5209f 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -26,7 +26,13 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
@@ -38,12 +44,23 @@
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)))
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
+#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
#else
-#define CONFIG_SYS_INIT_SP_ADDR \
+#define CONFIG_SPL_STACK \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#endif
+/*
+ * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
+ * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
+ * in U-Boot pre-reloc is higher than in SPL.
+ */
+#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
+#else
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
+#endif
+
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
@@ -252,16 +269,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#endif
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-/* SPL memory allocation configuration, this is for FAT implementation */
-#ifndef CONFIG_SYS_SPL_MALLOC_START
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
- CONFIG_SYS_SPL_MALLOC_SIZE + \
- CONFIG_SYS_INIT_RAM_ADDR)
-#endif
-#endif
-
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
@@ -292,15 +299,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#endif
-/*
- * Stack setup
- */
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
-#endif
-
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 3/4] arm: socfpga: imply/default common config options
2019-04-09 19:02 [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Simon Goldschmidt
2019-04-09 19:02 ` [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout Simon Goldschmidt
2019-04-09 19:02 ` [U-Boot] [PATCH v4 2/4] arm: socfpga: put initial U-Boot stack into DDR Simon Goldschmidt
@ 2019-04-09 19:02 ` Simon Goldschmidt
2019-04-09 19:34 ` Marek Vasut
2019-04-09 19:02 ` [U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc Simon Goldschmidt
2019-04-09 19:33 ` [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Marek Vasut
4 siblings, 1 reply; 10+ messages in thread
From: Simon Goldschmidt @ 2019-04-09 19:02 UTC (permalink / raw)
To: u-boot
This commit moves common config options used in all socfpga boards
to select/imply in Kconfig. This both cleans up the defconfig files
as well as makes future changes easier.
Options implied/defaulted for all sub-arches:
- SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS
Options implied/defaulted for implied for A10 & gen5:
- FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE
Options implied/defaulted for gen5:
- SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v4:
- adapt to socfpga-next
Changes in v3:
- adapt to socfpge-next: imply USE_TINY_PRINTF only for gen5 & a10,
not s10
Changes in v2:
- added patch to imply/default common config options
arch/arm/Kconfig | 2 ++
arch/arm/mach-socfpga/Kconfig | 20 ++++++++++++++++++++
configs/socfpga_arria10_defconfig | 6 ------
configs/socfpga_arria5_defconfig | 10 ----------
configs/socfpga_cyclone5_defconfig | 10 ----------
configs/socfpga_dbm_soc1_defconfig | 10 ----------
configs/socfpga_de0_nano_soc_defconfig | 10 ----------
configs/socfpga_de10_nano_defconfig | 10 ----------
configs/socfpga_de1_soc_defconfig | 10 ----------
configs/socfpga_is1_defconfig | 8 --------
configs/socfpga_sockit_defconfig | 10 ----------
configs/socfpga_socrates_defconfig | 10 ----------
configs/socfpga_sr1500_defconfig | 10 ----------
configs/socfpga_stratix10_defconfig | 2 --
configs/socfpga_vining_fpga_defconfig | 10 ----------
15 files changed, 22 insertions(+), 116 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 77a534f81f..6554ad94f8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -841,6 +841,8 @@ config ARCH_SOCFPGA
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
+ imply SPL
+ imply SPL_DM
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC_SUPPORT
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5e87371f8c..3c6c63067d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,8 +1,22 @@
if ARCH_SOCFPGA
+config NR_DRAM_BANKS
+ default 1
+
+config SPL_STACK_R_ADDR
+ default 0x00800000 if TARGET_SOCFPGA_GEN5
+
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
+config SYS_MALLOC_F_LEN
+ default 0x2000 if TARGET_SOCFPGA_ARRIA10
+ default 0x2000 if TARGET_SOCFPGA_GEN5
+
+config SYS_TEXT_BASE
+ default 0x01000040 if TARGET_SOCFPGA_ARRIA10
+ default 0x01000040 if TARGET_SOCFPGA_GEN5
+
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
@@ -21,6 +35,8 @@ config TARGET_SOCFPGA_ARRIA10
select SYSCON
select SPL_SYSCON if SPL
select ETH_DESIGNWARE_SOCFPGA
+ imply FPGA_SOCFPGA
+ imply USE_TINY_PRINTF
config TARGET_SOCFPGA_CYCLONE5
bool
@@ -29,6 +45,10 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
+ imply FPGA_SOCFPGA
+ imply SPL_STACK_R
+ imply SPL_SYS_MALLOC_SIMPLE
+ imply USE_TINY_PRINTF
config TARGET_SOCFPGA_STRATIX10
bool
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index f321a0ac3b..b3540cfe42 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -1,12 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
@@ -28,9 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
@@ -42,4 +37,3 @@ CONFIG_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 2f04092649..d514b14364 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -72,4 +63,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 2625aadf40..2d1a20154a 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index b6f4f8a3dd..233d1334b3 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -1,11 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@@ -15,8 +10,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -41,9 +34,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -67,4 +58,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 9a89bb5d68..dfd2d0f504 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -40,9 +33,7 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -68,4 +59,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index db516891ba..d02a8d7d87 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -36,9 +29,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -64,4 +55,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 5bed755723..c860bb45ad 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -36,8 +29,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -55,5 +46,4 @@ CONFIG_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
-CONFIG_USE_TINY_PRINTF=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index cd7211d202..7c81a83fc6 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_IS1=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@@ -17,7 +12,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -36,11 +30,9 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 4c17d1a9e4..805bbe1a1a 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 45fd78a15c..0ded246e78 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -40,10 +33,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index b8de47a4b1..6542045ca2 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SR1500=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -18,8 +13,6 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -40,11 +33,9 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
@@ -64,4 +55,3 @@ CONFIG_MII=y
CONFIG_DM_RESET=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 4848013b21..a6a28893ca 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x1000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
-CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
CONFIG_NR_DRAM_BANKS=2
@@ -30,7 +29,6 @@ CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 3eba09dcb1..7b47b111b7 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,12 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
@@ -19,8 +14,6 @@ CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -45,12 +38,10 @@ CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_LED_STATUS=y
@@ -90,4 +81,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc
2019-04-09 19:02 [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Simon Goldschmidt
` (2 preceding siblings ...)
2019-04-09 19:02 ` [U-Boot] [PATCH v4 3/4] arm: socfpga: imply/default common config options Simon Goldschmidt
@ 2019-04-09 19:02 ` Simon Goldschmidt
2019-04-09 19:34 ` Marek Vasut
2019-04-09 19:33 ` [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Marek Vasut
4 siblings, 1 reply; 10+ messages in thread
From: Simon Goldschmidt @ 2019-04-09 19:02 UTC (permalink / raw)
To: u-boot
By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.
On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).
To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v4: None
Changes in v3:
- adapt to socfpga-next
Changes in v2:
- added patch to reduce gen5 SPL initial malloc pool to 2 KiB
arch/arm/mach-socfpga/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 3c6c63067d..8f7b79f586 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -6,6 +6,9 @@ config NR_DRAM_BANKS
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
+config SPL_SYS_MALLOC_F_LEN
+ default 0x800 if TARGET_SOCFPGA_GEN5
+
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups
2019-04-09 19:02 [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Simon Goldschmidt
` (3 preceding siblings ...)
2019-04-09 19:02 ` [U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc Simon Goldschmidt
@ 2019-04-09 19:33 ` Marek Vasut
4 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2019-04-09 19:33 UTC (permalink / raw)
To: u-boot
On 4/9/19 9:02 PM, Simon Goldschmidt wrote:
> This series cleans up stack definitions in socfpga_common.h as well as
> cleans up defconfig files by implying/defaulting common things in Kconfig
> files.
>
> Finally, it reduces the malloc pool size used in first stage of gen5 SPL
> (without ddr available) in order to have more space available for code.
>
> As this series does not contain direct bugfixes, it targets the
> socfpga-next branch.
>
> Note that this series is meant for socfpga-next but depends on the generic
> series "spl: full-featured heap cleanups" from:
> https://patchwork.ozlabs.org/project/uboot/list/?series=99561
>
> Changes in v4:
> - make this patch 2/4 work without changing a10 heap allocation strategy
> (as the series doing that has been rejected)
> - adapt to socfpga-next
>
> Changes in v3:
> - removed patch 2/5 from v2 (moved to patchwork #1067366, series #99561)
> - adapt to socfpge-next: imply USE_TINY_PRINTF only for gen5 & a10,
> not s10
> - adapt to socfpga-next
>
> Changes in v2:
> - fix commit message: "SPL post-reloc", not "SPL pre-reloc"
> - added patch to imply/default common config options
> - added patch to reduce gen5 SPL initial malloc pool to 2 KiB
>
> Simon Goldschmidt (4):
> arm: socfpga: fix comment about SPL memory layout
> arm: socfpga: put initial U-Boot stack into DDR
> arm: socfpga: imply/default common config options
> arm: socfpga: gen5: reduce SPL pre-reloc malloc
>
> arch/arm/Kconfig | 2 ++
> arch/arm/mach-socfpga/Kconfig | 23 ++++++++++++
> configs/socfpga_arria10_defconfig | 6 ----
> configs/socfpga_arria5_defconfig | 10 ------
> configs/socfpga_cyclone5_defconfig | 10 ------
> configs/socfpga_dbm_soc1_defconfig | 10 ------
> configs/socfpga_de0_nano_soc_defconfig | 10 ------
> configs/socfpga_de10_nano_defconfig | 10 ------
> configs/socfpga_de1_soc_defconfig | 10 ------
> configs/socfpga_is1_defconfig | 8 -----
> configs/socfpga_sockit_defconfig | 10 ------
> configs/socfpga_socrates_defconfig | 10 ------
> configs/socfpga_sr1500_defconfig | 10 ------
> configs/socfpga_stratix10_defconfig | 2 --
> configs/socfpga_vining_fpga_defconfig | 10 ------
> include/configs/socfpga_common.h | 48 ++++++++++++--------------
> 16 files changed, 48 insertions(+), 141 deletions(-)
>
Acked-by: Marek Vasut <marex@denx.de>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout
2019-04-09 19:02 ` [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout Simon Goldschmidt
@ 2019-04-09 19:33 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2019-04-09 19:33 UTC (permalink / raw)
To: u-boot
On 4/9/19 9:02 PM, Simon Goldschmidt wrote:
> The comment about SPL memory layout for socfpga gen5 is outdated: the
> initial malloc memory is now at the end of the SRAM, gd is below it
> (see board_init_f_alloc_reserve).
>
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> include/configs/socfpga_common.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index f9e2cdc1b3..32ee7426b6 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -236,9 +236,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> *
> * 0xFFFF_0000 ...... Start of SRAM
> * 0xFFFF_xxxx ...... Top of stack (grows down)
> - * 0xFFFF_yyyy ...... Malloc area
> - * 0xFFFF_zzzz ...... Global Data
> - * 0xFFFF_FF00 ...... End of SRAM
> + * 0xFFFF_yyyy ...... Global Data
> + * 0xFFFF_zzzz ...... Malloc area
> + * 0xFFFF_FFFF ...... End of SRAM
> *
> * SRAM Memory layout for Arria 10:
> * 0xFFE0_0000 ...... Start of SRAM (bottom)
>
Acked-by: Marek Vasut <marex@denx.de>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 2/4] arm: socfpga: put initial U-Boot stack into DDR
2019-04-09 19:02 ` [U-Boot] [PATCH v4 2/4] arm: socfpga: put initial U-Boot stack into DDR Simon Goldschmidt
@ 2019-04-09 19:34 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2019-04-09 19:34 UTC (permalink / raw)
To: u-boot
On 4/9/19 9:02 PM, Simon Goldschmidt wrote:
> If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to
> do that, too.
>
> The reason to do so is that this way, U-Boot initial stack can be larger
> than SPL initial stack. In situations where we want to save the SPL
> in SRAM for next boot without reloading, this prevents overwriting the
> SPL DTB in SRAM if U-Boot stack usage gets too high.
>
> To achieve this, the malloc definition for a10 is moved up and sligthly
> changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size.
>
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
>
> Changes in v4:
> - make this patch 2/4 work without changing a10 heap allocation strategy
> (as the series doing that has been rejected)
>
> Changes in v3:
> - removed patch 2/5 from v2 (moved to patchwork #1067366, series #99561)
>
> Changes in v2:
> - fix commit message: "SPL post-reloc", not "SPL pre-reloc"
>
> include/configs/socfpga_common.h | 42 +++++++++++++++-----------------
> 1 file changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 32ee7426b6..a501b5209f 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -26,7 +26,13 @@
> #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
> +/* SPL memory allocation configuration, this is for FAT implementation */
> +#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
> +#endif
> +#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
> + CONFIG_SYS_INIT_RAM_SIZE)
> #endif
>
> /*
> @@ -38,12 +44,23 @@
> #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
> (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
> CONFIG_SYS_INIT_RAM_SIZE)))
> -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
> +#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
> #else
> -#define CONFIG_SYS_INIT_SP_ADDR \
> +#define CONFIG_SPL_STACK \
> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
> #endif
>
> +/*
> + * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
> + * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
> + * in U-Boot pre-reloc is higher than in SPL.
> + */
> +#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
> +#else
> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
> +#endif
> +
> #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
>
> /*
> @@ -252,16 +269,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
> #endif
>
> -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> -/* SPL memory allocation configuration, this is for FAT implementation */
> -#ifndef CONFIG_SYS_SPL_MALLOC_START
> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
> - CONFIG_SYS_SPL_MALLOC_SIZE + \
> - CONFIG_SYS_INIT_RAM_ADDR)
> -#endif
> -#endif
> -
> /* SPL SDMMC boot support */
> #ifdef CONFIG_SPL_MMC_SUPPORT
> #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
> @@ -292,15 +299,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> #endif
> #endif
>
> -/*
> - * Stack setup
> - */
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> -#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
> -#endif
> -
> /* Extra Environment */
> #ifndef CONFIG_SPL_BUILD
>
>
Acked-by: Marek Vasut <marex@denx.de>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 3/4] arm: socfpga: imply/default common config options
2019-04-09 19:02 ` [U-Boot] [PATCH v4 3/4] arm: socfpga: imply/default common config options Simon Goldschmidt
@ 2019-04-09 19:34 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2019-04-09 19:34 UTC (permalink / raw)
To: u-boot
On 4/9/19 9:02 PM, Simon Goldschmidt wrote:
> This commit moves common config options used in all socfpga boards
> to select/imply in Kconfig. This both cleans up the defconfig files
> as well as makes future changes easier.
>
> Options implied/defaulted for all sub-arches:
> - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS
>
> Options implied/defaulted for implied for A10 & gen5:
> - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE
>
> Options implied/defaulted for gen5:
> - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR
>
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
>
> Changes in v4:
> - adapt to socfpga-next
>
> Changes in v3:
> - adapt to socfpge-next: imply USE_TINY_PRINTF only for gen5 & a10,
> not s10
>
> Changes in v2:
> - added patch to imply/default common config options
>
> arch/arm/Kconfig | 2 ++
> arch/arm/mach-socfpga/Kconfig | 20 ++++++++++++++++++++
> configs/socfpga_arria10_defconfig | 6 ------
> configs/socfpga_arria5_defconfig | 10 ----------
> configs/socfpga_cyclone5_defconfig | 10 ----------
> configs/socfpga_dbm_soc1_defconfig | 10 ----------
> configs/socfpga_de0_nano_soc_defconfig | 10 ----------
> configs/socfpga_de10_nano_defconfig | 10 ----------
> configs/socfpga_de1_soc_defconfig | 10 ----------
> configs/socfpga_is1_defconfig | 8 --------
> configs/socfpga_sockit_defconfig | 10 ----------
> configs/socfpga_socrates_defconfig | 10 ----------
> configs/socfpga_sr1500_defconfig | 10 ----------
> configs/socfpga_stratix10_defconfig | 2 --
> configs/socfpga_vining_fpga_defconfig | 10 ----------
> 15 files changed, 22 insertions(+), 116 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 77a534f81f..6554ad94f8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -841,6 +841,8 @@ config ARCH_SOCFPGA
> imply DM_SPI
> imply DM_SPI_FLASH
> imply FAT_WRITE
> + imply SPL
> + imply SPL_DM
> imply SPL_LIBDISK_SUPPORT
> imply SPL_MMC_SUPPORT
> imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 5e87371f8c..3c6c63067d 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -1,8 +1,22 @@
> if ARCH_SOCFPGA
>
> +config NR_DRAM_BANKS
> + default 1
> +
> +config SPL_STACK_R_ADDR
> + default 0x00800000 if TARGET_SOCFPGA_GEN5
> +
> config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
> default 0xa2
>
> +config SYS_MALLOC_F_LEN
> + default 0x2000 if TARGET_SOCFPGA_ARRIA10
> + default 0x2000 if TARGET_SOCFPGA_GEN5
> +
> +config SYS_TEXT_BASE
> + default 0x01000040 if TARGET_SOCFPGA_ARRIA10
> + default 0x01000040 if TARGET_SOCFPGA_GEN5
> +
> config TARGET_SOCFPGA_ARRIA5
> bool
> select TARGET_SOCFPGA_GEN5
> @@ -21,6 +35,8 @@ config TARGET_SOCFPGA_ARRIA10
> select SYSCON
> select SPL_SYSCON if SPL
> select ETH_DESIGNWARE_SOCFPGA
> + imply FPGA_SOCFPGA
> + imply USE_TINY_PRINTF
>
> config TARGET_SOCFPGA_CYCLONE5
> bool
> @@ -29,6 +45,10 @@ config TARGET_SOCFPGA_CYCLONE5
> config TARGET_SOCFPGA_GEN5
> bool
> select ALTERA_SDRAM
> + imply FPGA_SOCFPGA
> + imply SPL_STACK_R
> + imply SPL_SYS_MALLOC_SIMPLE
> + imply USE_TINY_PRINTF
>
> config TARGET_SOCFPGA_STRATIX10
> bool
> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
> index f321a0ac3b..b3540cfe42 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -1,12 +1,9 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> -CONFIG_SPL=y
> CONFIG_IDENT_STRING="socfpga_arria10"
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_USE_BOOTARGS=y
> CONFIG_BOOTARGS="console=ttyS0,115200"
> # CONFIG_USE_BOOTCOMMAND is not set
> @@ -28,9 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_MMC=y
> @@ -42,4 +37,3 @@ CONFIG_SPI=y
> CONFIG_TIMER=y
> CONFIG_SPL_TIMER=y
> CONFIG_DESIGNWARE_APB_TIMER=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
> index 2f04092649..d514b14364 100644
> --- a/configs/socfpga_arria5_defconfig
> +++ b/configs/socfpga_arria5_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -72,4 +63,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
> index 2625aadf40..2d1a20154a 100644
> --- a/configs/socfpga_cyclone5_defconfig
> +++ b/configs/socfpga_cyclone5_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
> index b6f4f8a3dd..233d1334b3 100644
> --- a/configs/socfpga_dbm_soc1_defconfig
> +++ b/configs/socfpga_dbm_soc1_defconfig
> @@ -1,11 +1,6 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> CONFIG_USE_BOOTARGS=y
> CONFIG_BOOTARGS="console=ttyS0,115200"
> @@ -15,8 +10,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_HUSH_PARSER=y
> CONFIG_CMD_BOOTZ=y
> @@ -41,9 +34,7 @@ CONFIG_CMD_FAT=y
> CONFIG_CMD_FS_GENERIC=y
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -67,4 +58,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
> index 9a89bb5d68..dfd2d0f504 100644
> --- a/configs/socfpga_de0_nano_soc_defconfig
> +++ b/configs/socfpga_de0_nano_soc_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -40,9 +33,7 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -68,4 +59,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
> index db516891ba..d02a8d7d87 100644
> --- a/configs/socfpga_de10_nano_defconfig
> +++ b/configs/socfpga_de10_nano_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb"
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -36,9 +29,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -64,4 +55,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
> index 5bed755723..c860bb45ad 100644
> --- a/configs/socfpga_de1_soc_defconfig
> +++ b/configs/socfpga_de1_soc_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_YMODEM_SUPPORT=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -36,8 +29,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -55,5 +46,4 @@ CONFIG_SPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
> CONFIG_USB_DWC2=y
> -CONFIG_USE_TINY_PRINTF=y
> # CONFIG_EFI_LOADER is not set
> diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
> index cd7211d202..7c81a83fc6 100644
> --- a/configs/socfpga_is1_defconfig
> +++ b/configs/socfpga_is1_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_IS1=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> CONFIG_USE_BOOTARGS=y
> CONFIG_BOOTARGS="console=ttyS0,115200"
> @@ -17,7 +12,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -36,11 +30,9 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
> CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_BOOTCOUNT_LIMIT=y
> CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
> index 4c17d1a9e4..805bbe1a1a 100644
> --- a/configs/socfpga_sockit_defconfig
> +++ b/configs/socfpga_sockit_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
> index 45fd78a15c..0ded246e78 100644
> --- a/configs/socfpga_socrates_defconfig
> +++ b/configs/socfpga_socrates_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -40,10 +33,8 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
> CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
> index b8de47a4b1..6542045ca2 100644
> --- a/configs/socfpga_sr1500_defconfig
> +++ b/configs/socfpga_sr1500_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_SR1500=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> # CONFIG_USE_BOOTCOMMAND is not set
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -18,8 +13,6 @@ CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -40,11 +33,9 @@ CONFIG_CMD_UBI=y
> # CONFIG_EFI_PARTITION is not set
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
> CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_BOOTCOUNT_LIMIT=y
> CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> @@ -64,4 +55,3 @@ CONFIG_MII=y
> CONFIG_DM_RESET=y
> CONFIG_SPI=y
> CONFIG_CADENCE_QSPI=y
> -CONFIG_USE_TINY_PRINTF=y
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index 4848013b21..a6a28893ca 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -3,7 +3,6 @@ CONFIG_ARCH_SOCFPGA=y
> CONFIG_SYS_TEXT_BASE=0x1000
> CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
> -CONFIG_SPL=y
> CONFIG_IDENT_STRING="socfpga_stratix10"
> CONFIG_SPL_FS_FAT=y
> CONFIG_NR_DRAM_BANKS=2
> @@ -30,7 +29,6 @@ CONFIG_OF_EMBED=y
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
> CONFIG_ENV_IS_IN_MMC=y
> CONFIG_NET_RANDOM_ETHADDR=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
> index 3eba09dcb1..7b47b111b7 100644
> --- a/configs/socfpga_vining_fpga_defconfig
> +++ b/configs/socfpga_vining_fpga_defconfig
> @@ -1,12 +1,7 @@
> CONFIG_ARM=y
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_SYS_TEXT_BASE=0x01000040
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
> -CONFIG_SPL=y
> -CONFIG_SPL_STACK_R_ADDR=0x00800000
> CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> CONFIG_BOOTDELAY=5
> CONFIG_USE_BOOTARGS=y
> @@ -19,8 +14,6 @@ CONFIG_MISC_INIT_R=y
> CONFIG_VERSION_VARIABLE=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> CONFIG_SPL_SPI_LOAD=y
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> @@ -45,12 +38,10 @@ CONFIG_CMD_UBI=y
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
> CONFIG_ENV_IS_IN_SPI_FLASH=y
> CONFIG_NET_RANDOM_ETHADDR=y
> -CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> CONFIG_DFU_RAM=y
> CONFIG_DFU_SF=y
> -CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_LED_STATUS=y
> @@ -90,4 +81,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_USB_GADGET_DWC2_OTG=y
> CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USE_TINY_PRINTF=y
>
Acked-by: Marek Vasut <marex@denx.de>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc
2019-04-09 19:02 ` [U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc Simon Goldschmidt
@ 2019-04-09 19:34 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2019-04-09 19:34 UTC (permalink / raw)
To: u-boot
On 4/9/19 9:02 PM, Simon Goldschmidt wrote:
> By enabling debug prints in malloc_simple, we can see that SPL for socfpga
> gen5 does by far not need the 8 KiB malloc pool currently allocated for
> SPL in pre-reloc phase.
>
> On socfpga_socrates, 1304 bytes are currently used (and this increases by
> ~200 bytes only for the sdram/reset fixes in socfpga-next).
>
> To prevent wasting precious SRAM space, let's reduce the initial heap used
> for SPL to 2 KiB. This is still some hundred bytes more than currently
> used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
> early. Only the initial uclass/dm parsing, serial console and DDR
> initialization is done in the initial heap, so these 2 KiB should be
> enough for all boards.
>
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
>
> Changes in v4: None
> Changes in v3:
> - adapt to socfpga-next
>
> Changes in v2:
> - added patch to reduce gen5 SPL initial malloc pool to 2 KiB
>
> arch/arm/mach-socfpga/Kconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 3c6c63067d..8f7b79f586 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -6,6 +6,9 @@ config NR_DRAM_BANKS
> config SPL_STACK_R_ADDR
> default 0x00800000 if TARGET_SOCFPGA_GEN5
>
> +config SPL_SYS_MALLOC_F_LEN
> + default 0x800 if TARGET_SOCFPGA_GEN5
> +
> config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
> default 0xa2
>
>
Acked-by: Marek Vasut <marex@denx.de>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-04-09 19:34 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-09 19:02 [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Simon Goldschmidt
2019-04-09 19:02 ` [U-Boot] [PATCH v4 1/4] arm: socfpga: fix comment about SPL memory layout Simon Goldschmidt
2019-04-09 19:33 ` Marek Vasut
2019-04-09 19:02 ` [U-Boot] [PATCH v4 2/4] arm: socfpga: put initial U-Boot stack into DDR Simon Goldschmidt
2019-04-09 19:34 ` Marek Vasut
2019-04-09 19:02 ` [U-Boot] [PATCH v4 3/4] arm: socfpga: imply/default common config options Simon Goldschmidt
2019-04-09 19:34 ` Marek Vasut
2019-04-09 19:02 ` [U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc Simon Goldschmidt
2019-04-09 19:34 ` Marek Vasut
2019-04-09 19:33 ` [U-Boot] [PATCH v4 0/4] arm: socfpga: stack and Kconfig cleanups Marek Vasut
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