* [PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V
@ 2021-07-05 6:43 Kito Cheng
2021-07-06 3:28 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Kito Cheng @ 2021-07-05 6:43 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, qemu-devel, qemu-riscv,
richard.henderson
Cc: Kito Cheng
Set I, M, A, F, D and C bit for hwcap if misa is set.
V2 Changes:
- Only set imafdc bits, sync with upstream linux kernel.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
linux-user/elfload.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 598ab8aa13..3cdc7d06e1 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1426,7 +1426,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
#ifdef TARGET_RISCV
#define ELF_START_MMAP 0x80000000
-#define ELF_ARCH EM_RISCV
+#define ELF_ARCH EM_RISCV
#ifdef TARGET_RISCV32
#define ELF_CLASS ELFCLASS32
@@ -1434,6 +1434,34 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
#define ELF_CLASS ELFCLASS64
#endif
+#define ELF_HWCAP get_elf_hwcap()
+
+static uint32_t get_elf_hwcap(void)
+{
+ RISCVCPU *cpu = RISCV_CPU(thread_cpu);
+ uint32_t hwcap = 0;
+
+#define MISA_BIT(EXT) (1 << (EXT - 'A'))
+#define GET_EXT(EXT) \
+ do { \
+ if (cpu->env.misa & MISA_BIT(EXT)) { \
+ hwcap |= MISA_BIT(EXT); \
+ } \
+ } while (0)
+
+ GET_EXT('I');
+ GET_EXT('M');
+ GET_EXT('A');
+ GET_EXT('F');
+ GET_EXT('D');
+ GET_EXT('C');
+
+#undef MISA_BIT
+#undef GET_EXT
+
+ return hwcap;
+}
+
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V
2021-07-05 6:43 [PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng
@ 2021-07-06 3:28 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2021-07-06 3:28 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv
On 7/4/21 11:43 PM, Kito Cheng wrote:
> +static uint32_t get_elf_hwcap(void)
> +{
> + RISCVCPU *cpu = RISCV_CPU(thread_cpu);
> + uint32_t hwcap = 0;
> +
> +#define MISA_BIT(EXT) (1 << (EXT - 'A'))
> +#define GET_EXT(EXT) \
> + do { \
> + if (cpu->env.misa & MISA_BIT(EXT)) { \
> + hwcap |= MISA_BIT(EXT); \
> + } \
> + } while (0)
> +
> + GET_EXT('I');
> + GET_EXT('M');
> + GET_EXT('A');
> + GET_EXT('F');
> + GET_EXT('D');
> + GET_EXT('C');
You're not transforming the bits; there's no reason to be so around-the-bush about this.
Just use
uint32_t mask = MISA_BIT('I') | ...
return cpu->env.misa & mask;
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-07-06 3:29 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-05 6:43 [PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng
2021-07-06 3:28 ` Richard Henderson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.