From: crj <algea.cao@rock-chips.com> To: "Vicente Bergas" <vicencb@gmail.com>, "Doug Anderson" <dianders@chromium.org>, "Andy Yan" <andy.yan@rock-chips.com>, "Sandy Huang" <hjc@rock-chips.com>, "Heiko Stübner" <heiko@sntech.de>, "David Airlie" <airlied@linux.ie>, "Daniel Vetter" <daniel@ffwll.ch>, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v2 1/3] drm: rockchip: hdmi: fix clock rounding code Date: Wed, 23 Sep 2020 09:37:41 +0800 [thread overview] Message-ID: <50002e7b-d1f2-8209-fe65-7f60f036f7d3@rock-chips.com> (raw) In-Reply-To: <20200922203107.2932-2-vicencb@gmail.com> 在 2020/9/23 4:31, Vicente Bergas 写道: > Under certain conditions vop_crtc_mode_fixup rounds the clock > 148500000 to 148501000 which leads to the following error: > dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 148501000) > > The issue was found on RK3399 booting with u-boot. U-boot configures the > display at 2560x1440 and then linux comes up with a black screen. > A workaround was to un-plug and re-plug the HDMI display. > > Signed-off-by: Vicente Bergas <vicencb@gmail.com> > Tested-by: Vicente Bergas <vicencb@gmail.com> > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index c80f7d9fd13f..92efbd899dee 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -1176,12 +1176,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, > * > * 2. Get the clock framework to round the rate for us to tell us > * what it will actually make. > - * > - * 3. Store the rounded up rate so that we don't need to worry about > - * this in the actual clk_set_rate(). > */ > rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); > - adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); > + adjusted_mode->clock = rate / 1000; > > return true; > } > @@ -1380,7 +1377,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, > > VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); > > - clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); > + clk_set_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); In some RK platform, such as RK3328, dclk is generated by the INNO HDMI PHY PLL, which support frac divider can support any dclk frequency. And The PLL must use the exact clock to determine the PLL configuration. So adjusted_mode->clock * 1000 + 999 may cause INNO HDMI PHY PLL couldn't find the right configuration. INNO HDMI PHY's driver path is: drivers/phy/rockchip/phy-rockchip-inno-hdmi.c > > VOP_REG_SET(vop, common, standby, 0); > mutex_unlock(&vop->vop_lock); _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: crj <algea.cao@rock-chips.com> To: "Vicente Bergas" <vicencb@gmail.com>, "Doug Anderson" <dianders@chromium.org>, "Andy Yan" <andy.yan@rock-chips.com>, "Sandy Huang" <hjc@rock-chips.com>, "Heiko Stübner" <heiko@sntech.de>, "David Airlie" <airlied@linux.ie>, "Daniel Vetter" <daniel@ffwll.ch>, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v2 1/3] drm: rockchip: hdmi: fix clock rounding code Date: Wed, 23 Sep 2020 09:37:41 +0800 [thread overview] Message-ID: <50002e7b-d1f2-8209-fe65-7f60f036f7d3@rock-chips.com> (raw) In-Reply-To: <20200922203107.2932-2-vicencb@gmail.com> 在 2020/9/23 4:31, Vicente Bergas 写道: > Under certain conditions vop_crtc_mode_fixup rounds the clock > 148500000 to 148501000 which leads to the following error: > dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 148501000) > > The issue was found on RK3399 booting with u-boot. U-boot configures the > display at 2560x1440 and then linux comes up with a black screen. > A workaround was to un-plug and re-plug the HDMI display. > > Signed-off-by: Vicente Bergas <vicencb@gmail.com> > Tested-by: Vicente Bergas <vicencb@gmail.com> > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index c80f7d9fd13f..92efbd899dee 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -1176,12 +1176,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, > * > * 2. Get the clock framework to round the rate for us to tell us > * what it will actually make. > - * > - * 3. Store the rounded up rate so that we don't need to worry about > - * this in the actual clk_set_rate(). > */ > rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); > - adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); > + adjusted_mode->clock = rate / 1000; > > return true; > } > @@ -1380,7 +1377,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, > > VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); > > - clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); > + clk_set_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); In some RK platform, such as RK3328, dclk is generated by the INNO HDMI PHY PLL, which support frac divider can support any dclk frequency. And The PLL must use the exact clock to determine the PLL configuration. So adjusted_mode->clock * 1000 + 999 may cause INNO HDMI PHY PLL couldn't find the right configuration. INNO HDMI PHY's driver path is: drivers/phy/rockchip/phy-rockchip-inno-hdmi.c > > VOP_REG_SET(vop, common, standby, 0); > mutex_unlock(&vop->vop_lock); _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-09-23 1:38 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-22 20:31 [PATCH v2 0/3] drm: rockchip: hdmi: enable higher resolutions than FHD Vicente Bergas 2020-09-22 20:31 ` Vicente Bergas 2020-09-22 20:31 ` [PATCH v2 1/3] drm: rockchip: hdmi: fix clock rounding code Vicente Bergas 2020-09-22 20:31 ` Vicente Bergas 2020-09-23 1:37 ` crj [this message] 2020-09-23 1:37 ` crj 2020-09-23 22:58 ` Doug Anderson 2020-09-23 22:58 ` Doug Anderson 2020-09-23 22:55 ` Doug Anderson 2020-09-23 22:55 ` Doug Anderson 2020-09-22 20:31 ` [PATCH v2 2/3] drm: rockchip: hdmi: allow any clock that is within the range Vicente Bergas 2020-09-22 20:31 ` Vicente Bergas 2020-09-22 20:31 ` [PATCH v2 3/3] drm: rockchip: hdmi: add higher pixel clock frequencies Vicente Bergas 2020-09-22 20:31 ` Vicente Bergas 2020-09-23 22:18 ` [PATCH v2 0/3] drm: rockchip: hdmi: enable higher resolutions than FHD Robin Murphy 2020-09-23 22:18 ` Robin Murphy 2020-09-23 23:25 ` Doug Anderson 2020-09-23 23:25 ` Doug Anderson
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