From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-riscv] [PATCH for 4.1 v1 5/6] target/riscv: Remove the generic no MMU CPUs
Date: Tue, 19 Mar 2019 18:21:32 +0000 [thread overview]
Message-ID: <5192dd7d90cab0837ec848635b57128988b6b1bd.1553019560.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1553019560.git.alistair.francis@wdc.com>
These can now be specified via the command line so we no longer need
these.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 --
target/riscv/cpu.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 298413f6f6..1d507c5216 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -570,13 +570,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d7caa294e..2b26f77a5a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -50,10 +50,8 @@
#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
--
2.21.0
next prev parent reply other threads:[~2019-03-19 18:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 18:20 [Qemu-riscv] [PATCH for 4.1 v1 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
2019-03-19 18:20 ` [Qemu-riscv] [PATCH for 4.1 v1 1/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 2/6] target/riscv: Create settable CPU properties Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 3/6] riscv: virt: Allow specifying a CPU via commandline Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU Alistair Francis
2019-03-19 19:10 ` [Qemu-riscv] [Qemu-devel] " Peter Maydell
2019-03-20 21:35 ` Alistair Francis
2019-03-19 18:21 ` Alistair Francis [this message]
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 6/6] riscv: Add a generic spike machine Alistair Francis
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