From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-riscv] [PATCH for 4.1 v1 3/6] riscv: virt: Allow specifying a CPU via commandline
Date: Tue, 19 Mar 2019 18:21:14 +0000 [thread overview]
Message-ID: <ab6961a0893e75fb331d0346b3d70e8f26fcd800.1553019560.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1553019560.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index fc4c6b306e..5b25f028ad 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -400,7 +400,7 @@ static void riscv_virt_board_init(MachineState *machine)
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
@@ -526,6 +526,7 @@ static void riscv_virt_board_machine_init(MachineClass *mc)
mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
mc->init = riscv_virt_board_init;
mc->max_cpus = 8; /* hardcoded limit in BBL */
+ mc->default_cpu_type = VIRT_CPU;
}
DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
--
2.21.0
next prev parent reply other threads:[~2019-03-19 18:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 18:20 [Qemu-riscv] [PATCH for 4.1 v1 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
2019-03-19 18:20 ` [Qemu-riscv] [PATCH for 4.1 v1 1/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 2/6] target/riscv: Create settable CPU properties Alistair Francis
2019-03-19 18:21 ` Alistair Francis [this message]
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU Alistair Francis
2019-03-19 19:10 ` [Qemu-riscv] [Qemu-devel] " Peter Maydell
2019-03-20 21:35 ` Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 5/6] target/riscv: Remove the generic no MMU CPUs Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 6/6] riscv: Add a generic spike machine Alistair Francis
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