* [Qemu-devel] [PATCH v12 0/4] EEH Support for VFIO Devices
@ 2014-07-16 0:20 Gavin Shan
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public Gavin Shan
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 0:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: agraf, aik, qemu-devel, Gavin Shan, alex.williamson
The series of patches adds support EEH for VFIO PCI devices on sPAPR platform.
It requires corresponding host kernel support. It has been rebased to Alex Graf's
QEMU repository:
QEMU: git://github.com/agraf/qemu.git (branch: ppc-next)
Kernel: http://patchwork.ozlabs.org/patch/357665/
http://patchwork.ozlabs.org/patch/357667/
http://patchwork.ozlabs.org/patch/357666/
The implementations notes are below. Please comment.
* RTAS calls are received in spapr_pci.c, sanity check is done there. RTAS
handlers handle what they can. If there is something it cannot handle and
sPAPRPHBClass::eeh_handler callback is defined, it is called.
* sPAPRPHBClass::eeh_handler is only implemented for VFIO now. It does ioctl()
to the IOMMU container fd to complete the call. Error codes from that ioctl()
are transferred back to the guest.
Changelog
=========
v8 -> v9:
* Update kernel header (vfio.h) according to changes applied to kerenl.
* Rename rtas_finish_eeh_request() to rtas_handle_eeh_request().
* vfio_pci_container_ioctl() moved to Alexey's VFIO patchset.
v9 -> v10:
* Make sure we have zero struct vfio_eeh_pe_op::flags
v10 -> v11:
* Don't explicitly set struct vfio_eeh_pe_op::flags to 0.
* rtas_handle_eeh_request() checks the validity of sPAPRPHBState and
sPAPRPHBClass::eeh_handler.
* The first level functions set the RTAS call return value.
* Replace "if (...)" with "switch (...)".
v11 -> v12:
* RTAS call returns RTAS_OUT_NO_ERRORS_FOUND on success because we
don't support it yet.
* Add one more patch from Alexey to make find_phb() and find_dev()
phblic.
* Rebase to Alex Graf's QEMU repository.
Alexey Kardashevskiy (1):
spapr_pci: Make find_phb()/find_dev() public
Gavin Shan (3):
sPAPR: Implement EEH RTAS calls
headers: Update kernel header
sPAPR: Implement sPAPRPHBClass::eeh_handler
hw/misc/vfio.c | 1 +
hw/ppc/spapr_pci.c | 268 ++++++++++++++++++++++++++++++++++++++++++--
hw/ppc/spapr_pci_vfio.c | 56 +++++++++
include/hw/pci-host/spapr.h | 11 ++
include/hw/ppc/spapr.h | 43 ++++++-
linux-headers/linux/vfio.h | 34 ++++++
6 files changed, 400 insertions(+), 13 deletions(-)
--
1.8.3.2
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public
2014-07-16 0:20 [Qemu-devel] [PATCH v12 0/4] EEH Support for VFIO Devices Gavin Shan
@ 2014-07-16 0:20 ` Gavin Shan
2014-07-28 12:49 ` Alexander Graf
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls Gavin Shan
` (2 subsequent siblings)
3 siblings, 1 reply; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 0:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: aik, alex.williamson, qemu-devel, agraf
From: Alexey Kardashevskiy <aik@ozlabs.ru>
This makes find_phb()/find_dev() public and changed its names
to spapr_pci_find_phb()/spapr_pci_find_dev() as they are going to
be used from other parts of QEMU such as VFIO DDW (dynamic DMA window)
or VFIO PCI error injection or VFIO EEH handling - in all these
cases there are RTAS calls which are addressed to BUID+config_addr
in IEEE1275 format.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_pci.c | 22 +++++++++++-----------
include/hw/pci-host/spapr.h | 4 ++++
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 9ed39a9..230b59c 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -47,7 +47,7 @@
#define RTAS_TYPE_MSI 1
#define RTAS_TYPE_MSIX 2
-static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
+sPAPRPHBState *spapr_pci_find_phb(sPAPREnvironment *spapr, uint64_t buid)
{
sPAPRPHBState *sphb;
@@ -61,10 +61,10 @@ static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
return NULL;
}
-static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
- uint32_t config_addr)
+PCIDevice *spapr_pci_find_dev(sPAPREnvironment *spapr, uint64_t buid,
+ uint32_t config_addr)
{
- sPAPRPHBState *sphb = find_phb(spapr, buid);
+ sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
int bus_num = (config_addr >> 16) & 0xFF;
int devfn = (config_addr >> 8) & 0xFF;
@@ -95,7 +95,7 @@ static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
return;
}
- pci_dev = find_dev(spapr, buid, addr);
+ pci_dev = spapr_pci_find_dev(spapr, buid, addr);
addr = rtas_pci_cfgaddr(addr);
if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
@@ -162,7 +162,7 @@ static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
return;
}
- pci_dev = find_dev(spapr, buid, addr);
+ pci_dev = spapr_pci_find_dev(spapr, buid, addr);
addr = rtas_pci_cfgaddr(addr);
if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
@@ -281,9 +281,9 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
}
/* Fins sPAPRPHBState */
- phb = find_phb(spapr, buid);
+ phb = spapr_pci_find_phb(spapr, buid);
if (phb) {
- pdev = find_dev(spapr, buid, config_addr);
+ pdev = spapr_pci_find_dev(spapr, buid, config_addr);
}
if (!phb || !pdev) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@@ -377,9 +377,9 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
spapr_pci_msi *msi;
/* Find sPAPRPHBState */
- phb = find_phb(spapr, buid);
+ phb = spapr_pci_find_phb(spapr, buid);
if (phb) {
- pdev = find_dev(spapr, buid, config_addr);
+ pdev = spapr_pci_find_dev(spapr, buid, config_addr);
}
if (!phb || !pdev) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@@ -553,7 +553,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
return;
}
- if (find_phb(spapr, sphb->buid)) {
+ if (spapr_pci_find_phb(spapr, sphb->buid)) {
error_setg(errp, "PCI host bridges must have unique BUIDs");
return;
}
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 32f0aa7..14c2ab0 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -122,4 +122,8 @@ void spapr_pci_msi_init(sPAPREnvironment *spapr, hwaddr addr);
void spapr_pci_rtas_init(void);
+sPAPRPHBState *spapr_pci_find_phb(sPAPREnvironment *spapr, uint64_t buid);
+PCIDevice *spapr_pci_find_dev(sPAPREnvironment *spapr, uint64_t buid,
+ uint32_t config_addr);
+
#endif /* __HW_SPAPR_PCI_H__ */
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls
2014-07-16 0:20 [Qemu-devel] [PATCH v12 0/4] EEH Support for VFIO Devices Gavin Shan
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public Gavin Shan
@ 2014-07-16 0:20 ` Gavin Shan
2014-07-16 1:06 ` Alexey Kardashevskiy
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header Gavin Shan
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 4/4] sPAPR: Implement sPAPRPHBClass::eeh_handler Gavin Shan
3 siblings, 1 reply; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 0:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: agraf, aik, qemu-devel, Gavin Shan, alex.williamson
The emulation for EEH RTAS requests from guest isn't covered
by QEMU yet and the patch implements them.
The patch defines constants used by EEH RTAS calls and adds
callback sPAPRPHBClass::eeh_handler, which is going to be used
this way:
* RTAS calls are received in spapr_pci.c, sanity check is done
there.
* RTAS handlers handle what they can. If there is something it
cannot handle and sPAPRPHBClass::eeh_handler callback is defined,
it is called.
* sPAPRPHBClass::eeh_handler is only implemented for VFIO now. It
does ioctl() to the IOMMU container fd to complete the call. Error
codes from that ioctl() are transferred back to the guest.
[aik: defined RTAS tokens for EEH RTAS calls]
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
hw/ppc/spapr_pci.c | 246 ++++++++++++++++++++++++++++++++++++++++++++
include/hw/pci-host/spapr.h | 7 ++
include/hw/ppc/spapr.h | 43 +++++++-
3 files changed, 294 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 230b59c..63394f5 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -402,6 +402,233 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
}
+static int rtas_handle_eeh_request(sPAPREnvironment *spapr,
+ uint64_t buid, uint32_t req, uint32_t opt)
+{
+ sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
+ sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
+
+ if (!sphb || !info->eeh_handler) {
+ return -ENOENT;
+ }
+
+ return info->eeh_handler(sphb, req, opt);
+}
+
+static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
+ sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ uint32_t addr, option;
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ int ret;
+
+ if ((nargs != 4) || (nret != 1)) {
+ goto param_error_exit;
+ }
+
+ addr = rtas_ld(args, 0);
+ option = rtas_ld(args, 3);
+ switch (option) {
+ case RTAS_EEH_ENABLE:
+ if (!spapr_pci_find_dev(spapr, buid, addr)) {
+ goto param_error_exit;
+ }
+ break;
+ case RTAS_EEH_DISABLE:
+ case RTAS_EEH_THAW_IO:
+ case RTAS_EEH_THAW_DMA:
+ break;
+ default:
+ goto param_error_exit;
+ }
+
+ ret = rtas_handle_eeh_request(spapr, buid,
+ RTAS_EEH_REQ_SET_OPTION, option);
+ if (ret >= 0) {
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ return;
+ }
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
+static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
+ sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ uint32_t addr, option;
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
+ sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
+ PCIDevice *pdev;
+
+ if (!sphb || !info->eeh_handler) {
+ goto param_error_exit;
+ }
+
+ if ((nargs != 4) || (nret != 2)) {
+ goto param_error_exit;
+ }
+
+ addr = rtas_ld(args, 0);
+ option = rtas_ld(args, 3);
+ if (option != RTAS_GET_PE_ADDR && option != RTAS_GET_PE_MODE) {
+ goto param_error_exit;
+ }
+
+ pdev = spapr_pci_find_dev(spapr, buid, addr);
+ if (!pdev) {
+ goto param_error_exit;
+ }
+
+ /*
+ * For now, we always have bus level PE whose address
+ * has format "00BBSS00". The guest OS might regard
+ * PE address 0 as invalid. We avoid that simply by
+ * extending it with one.
+ */
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ if (option == RTAS_GET_PE_ADDR) {
+ rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
+ } else {
+ rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
+ }
+
+ return;
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
+static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
+ sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ int ret;
+
+ if ((nargs != 3) || (nret != 4 && nret != 5)) {
+ goto param_error_exit;
+ }
+
+ ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_GET_STATE, 0);
+ if (ret >= 0) {
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ rtas_st(rets, 1, ret);
+ rtas_st(rets, 2, RTAS_EEH_SUPPORT);
+ rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
+ if (nret >= 5) {
+ rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
+ }
+
+ return;
+ }
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
+static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
+ sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ uint32_t option;
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ int ret;
+
+ if ((nargs != 4) || (nret != 1)) {
+ goto param_error_exit;
+ }
+
+ option = rtas_ld(args, 3);
+ switch (option) {
+ case RTAS_SLOT_RESET_DEACTIVATE:
+ case RTAS_SLOT_RESET_HOT:
+ case RTAS_SLOT_RESET_FUNDAMENTAL:
+ break;
+ default:
+ goto param_error_exit;
+ }
+
+ ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_RESET, option);
+ if (ret >= 0) {
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ return;
+ }
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
+static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
+ sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ int ret;
+
+ if ((nargs != 3) || (nret != 1)) {
+ goto param_error_exit;
+ }
+
+ ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_CONFIGURE, 0);
+ if (ret >= 0) {
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ return;
+ }
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
+/* To support it later */
+static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
+ sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ int option;
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
+ sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
+
+ if (!sphb || !info->eeh_handler) {
+ goto param_error_exit;
+ }
+
+ if ((nargs != 8) || (nret != 1)) {
+ goto param_error_exit;
+ }
+
+ option = rtas_ld(args, 7);
+ switch (option) {
+ case RTAS_SLOT_TEMP_ERR_LOG:
+ case RTAS_SLOT_PERM_ERR_LOG:
+ break;
+ default:
+ goto param_error_exit;
+ }
+
+ rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
+ return;
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
static int pci_spapr_swizzle(int slot, int pin)
{
return (slot + pin) % PCI_NUM_PINS;
@@ -953,6 +1180,25 @@ void spapr_pci_rtas_init(void)
spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
rtas_ibm_change_msi);
}
+
+ spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
+ "ibm,set-eeh-option",
+ rtas_ibm_set_eeh_option);
+ spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
+ "ibm,get-config-addr-info2",
+ rtas_ibm_get_config_addr_info2);
+ spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
+ "ibm,read-slot-reset-state2",
+ rtas_ibm_read_slot_reset_state2);
+ spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
+ "ibm,set-slot-reset",
+ rtas_ibm_set_slot_reset);
+ spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
+ "ibm,configure-pe",
+ rtas_ibm_configure_pe);
+ spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
+ "ibm,slot-error-detail",
+ rtas_ibm_slot_error_detail);
}
static void spapr_pci_register_types(void)
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 14c2ab0..ea39aa6 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -49,6 +49,7 @@ struct sPAPRPHBClass {
PCIHostBridgeClass parent_class;
void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
+ int (*eeh_handler)(sPAPRPHBState *sphb, int req, int opt);
};
typedef struct spapr_pci_msi {
@@ -107,6 +108,12 @@ struct sPAPRPHBVFIOState {
#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
+/* EEH related requests */
+#define RTAS_EEH_REQ_SET_OPTION 0
+#define RTAS_EEH_REQ_GET_STATE 1
+#define RTAS_EEH_REQ_RESET 2
+#define RTAS_EEH_REQ_CONFIGURE 3
+
static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
{
return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index bbba51a..f74c7f2 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -338,6 +338,39 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
int spapr_allocate_irq(int hint, bool lsi);
int spapr_allocate_irq_block(int num, bool lsi, bool msi);
+/* ibm,set-eeh-option */
+#define RTAS_EEH_DISABLE 0
+#define RTAS_EEH_ENABLE 1
+#define RTAS_EEH_THAW_IO 2
+#define RTAS_EEH_THAW_DMA 3
+
+/* ibm,get-config-addr-info2 */
+#define RTAS_GET_PE_ADDR 0
+#define RTAS_GET_PE_MODE 1
+#define RTAS_PE_MODE_NONE 0
+#define RTAS_PE_MODE_NOT_SHARED 1
+#define RTAS_PE_MODE_SHARED 2
+
+/* ibm,read-slot-reset-state2 */
+#define RTAS_EEH_PE_STATE_NORMAL 0
+#define RTAS_EEH_PE_STATE_RESET 1
+#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
+#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
+#define RTAS_EEH_PE_STATE_UNAVAIL 5
+#define RTAS_EEH_NOT_SUPPORT 0
+#define RTAS_EEH_SUPPORT 1
+#define RTAS_EEH_PE_UNAVAIL_INFO 1000
+#define RTAS_EEH_PE_RECOVER_INFO 0
+
+/* ibm,set-slot-reset */
+#define RTAS_SLOT_RESET_DEACTIVATE 0
+#define RTAS_SLOT_RESET_HOT 1
+#define RTAS_SLOT_RESET_FUNDAMENTAL 3
+
+/* ibm,slot-error-detail */
+#define RTAS_SLOT_TEMP_ERR_LOG 1
+#define RTAS_SLOT_PERM_ERR_LOG 2
+
/* RTAS return codes */
#define RTAS_OUT_SUCCESS 0
#define RTAS_OUT_NO_ERRORS_FOUND 1
@@ -383,8 +416,14 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
#define RTAS_IBM_EXTENDED_OS_TERM (RTAS_TOKEN_BASE + 0x20)
-
-#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x21)
+#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x21)
+#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x22)
+#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x23)
+#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x24)
+#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x25)
+#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x26)
+
+#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x27)
/* RTAS ibm,get-system-parameter token values */
#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header
2014-07-16 0:20 [Qemu-devel] [PATCH v12 0/4] EEH Support for VFIO Devices Gavin Shan
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public Gavin Shan
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls Gavin Shan
@ 2014-07-16 0:20 ` Gavin Shan
2014-07-16 1:09 ` Alexey Kardashevskiy
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 4/4] sPAPR: Implement sPAPRPHBClass::eeh_handler Gavin Shan
3 siblings, 1 reply; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 0:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: agraf, aik, qemu-devel, Gavin Shan, alex.williamson
This updates kernel header (vfio.h) for EEH support on VFIO PCI
devices.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
| 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
--git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
index 26c218e..95b591b 100644
--- a/linux-headers/linux/vfio.h
+++ b/linux-headers/linux/vfio.h
@@ -30,6 +30,9 @@
*/
#define VFIO_DMA_CC_IOMMU 4
+/* Check if EEH is supported */
+#define VFIO_EEH 5
+
/*
* The IOCTL interface is designed for extensibility by embedding the
* structure length (argsz) and flags into structures passed between
@@ -455,6 +458,37 @@ struct vfio_iommu_spapr_tce_info {
#define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
+/*
+ * EEH PE operation struct provides ways to:
+ * - enable/disable EEH functionality;
+ * - unfreeze IO/DMA for frozen PE;
+ * - read PE state;
+ * - reset PE;
+ * - configure PE.
+ */
+struct vfio_eeh_pe_op {
+ __u32 argsz;
+ __u32 flags;
+ __u32 op;
+};
+
+#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
+#define VFIO_EEH_PE_ENABLE 1 /* Enable EEH functionality */
+#define VFIO_EEH_PE_UNFREEZE_IO 2 /* Enable IO for frozen PE */
+#define VFIO_EEH_PE_UNFREEZE_DMA 3 /* Enable DMA for frozen PE */
+#define VFIO_EEH_PE_GET_STATE 4 /* PE state retrieval */
+#define VFIO_EEH_PE_STATE_NORMAL 0 /* PE in functional state */
+#define VFIO_EEH_PE_STATE_RESET 1 /* PE reset in progress */
+#define VFIO_EEH_PE_STATE_STOPPED 2 /* Stopped DMA and IO */
+#define VFIO_EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
+#define VFIO_EEH_PE_STATE_UNAVAIL 5 /* State unavailable */
+#define VFIO_EEH_PE_RESET_DEACTIVATE 5 /* Deassert PE reset */
+#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
+#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
+#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
+
+#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
+
/* ***************************************************************** */
#endif /* VFIO_H */
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v12 4/4] sPAPR: Implement sPAPRPHBClass::eeh_handler
2014-07-16 0:20 [Qemu-devel] [PATCH v12 0/4] EEH Support for VFIO Devices Gavin Shan
` (2 preceding siblings ...)
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header Gavin Shan
@ 2014-07-16 0:20 ` Gavin Shan
3 siblings, 0 replies; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 0:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: agraf, aik, qemu-devel, Gavin Shan, alex.williamson
The patch implements sPAPRPHBClass::eeh_handler so that the
EEH RTAS requests can be routed to VFIO for further handling.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
hw/misc/vfio.c | 1 +
hw/ppc/spapr_pci_vfio.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c
index 0b9eba0..03f2839 100644
--- a/hw/misc/vfio.c
+++ b/hw/misc/vfio.c
@@ -4437,6 +4437,7 @@ int vfio_container_ioctl(AddressSpace *as, int32_t groupid,
switch (req) {
case VFIO_CHECK_EXTENSION:
case VFIO_IOMMU_SPAPR_TCE_GET_INFO:
+ case VFIO_EEH_PE_OP:
break;
default:
/* Return an error on unknown requests */
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index d3bddf2..032431f 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -71,6 +71,61 @@ static void spapr_phb_vfio_finish_realize(sPAPRPHBState *sphb, Error **errp)
spapr_tce_get_iommu(tcet));
}
+static int spapr_phb_vfio_eeh_handler(sPAPRPHBState *sphb, int req, int opt)
+{
+ sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
+ struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
+ int cmd;
+
+ switch (req) {
+ case RTAS_EEH_REQ_SET_OPTION:
+ switch (opt) {
+ case RTAS_EEH_DISABLE:
+ cmd = VFIO_EEH_PE_DISABLE;
+ break;
+ case RTAS_EEH_ENABLE:
+ cmd = VFIO_EEH_PE_ENABLE;
+ break;
+ case RTAS_EEH_THAW_IO:
+ cmd = VFIO_EEH_PE_UNFREEZE_IO;
+ break;
+ case RTAS_EEH_THAW_DMA:
+ cmd = VFIO_EEH_PE_UNFREEZE_DMA;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case RTAS_EEH_REQ_GET_STATE:
+ cmd = VFIO_EEH_PE_GET_STATE;
+ break;
+ case RTAS_EEH_REQ_RESET:
+ switch (opt) {
+ case RTAS_SLOT_RESET_DEACTIVATE:
+ cmd = VFIO_EEH_PE_RESET_DEACTIVATE;
+ break;
+ case RTAS_SLOT_RESET_HOT:
+ cmd = VFIO_EEH_PE_RESET_HOT;
+ break;
+ case RTAS_SLOT_RESET_FUNDAMENTAL:
+ cmd = VFIO_EEH_PE_RESET_FUNDAMENTAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case RTAS_EEH_REQ_CONFIGURE:
+ cmd = VFIO_EEH_PE_CONFIGURE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ op.op = cmd;
+ return vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
+ VFIO_EEH_PE_OP, &op);
+}
+
static void spapr_phb_vfio_reset(DeviceState *qdev)
{
/* Do nothing */
@@ -84,6 +139,7 @@ static void spapr_phb_vfio_class_init(ObjectClass *klass, void *data)
dc->props = spapr_phb_vfio_properties;
dc->reset = spapr_phb_vfio_reset;
spc->finish_realize = spapr_phb_vfio_finish_realize;
+ spc->eeh_handler = spapr_phb_vfio_eeh_handler;
}
static const TypeInfo spapr_phb_vfio_info = {
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls Gavin Shan
@ 2014-07-16 1:06 ` Alexey Kardashevskiy
2014-07-16 1:12 ` Gavin Shan
0 siblings, 1 reply; 15+ messages in thread
From: Alexey Kardashevskiy @ 2014-07-16 1:06 UTC (permalink / raw)
To: Gavin Shan, qemu-ppc; +Cc: alex.williamson, qemu-devel, agraf
On 07/16/2014 10:20 AM, Gavin Shan wrote:
> The emulation for EEH RTAS requests from guest isn't covered
> by QEMU yet and the patch implements them.
>
> The patch defines constants used by EEH RTAS calls and adds
> callback sPAPRPHBClass::eeh_handler, which is going to be used
> this way:
>
> * RTAS calls are received in spapr_pci.c, sanity check is done
> there.
> * RTAS handlers handle what they can. If there is something it
> cannot handle and sPAPRPHBClass::eeh_handler callback is defined,
> it is called.
> * sPAPRPHBClass::eeh_handler is only implemented for VFIO now. It
> does ioctl() to the IOMMU container fd to complete the call. Error
> codes from that ioctl() are transferred back to the guest.
>
> [aik: defined RTAS tokens for EEH RTAS calls]
> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
> ---
> hw/ppc/spapr_pci.c | 246 ++++++++++++++++++++++++++++++++++++++++++++
> include/hw/pci-host/spapr.h | 7 ++
> include/hw/ppc/spapr.h | 43 +++++++-
> 3 files changed, 294 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index 230b59c..63394f5 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -402,6 +402,233 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
> rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
> }
>
> +static int rtas_handle_eeh_request(sPAPREnvironment *spapr,
> + uint64_t buid, uint32_t req, uint32_t opt)
> +{
> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> +
> + if (!sphb || !info->eeh_handler) {
> + return -ENOENT;
> + }
> +
> + return info->eeh_handler(sphb, req, opt);
> +}
> +
> +static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
> + sPAPREnvironment *spapr,
> + uint32_t token, uint32_t nargs,
> + target_ulong args, uint32_t nret,
> + target_ulong rets)
> +{
> + uint32_t addr, option;
> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
> + int ret;
> +
> + if ((nargs != 4) || (nret != 1)) {
> + goto param_error_exit;
> + }
> +
> + addr = rtas_ld(args, 0);
> + option = rtas_ld(args, 3);
> + switch (option) {
> + case RTAS_EEH_ENABLE:
> + if (!spapr_pci_find_dev(spapr, buid, addr)) {
> + goto param_error_exit;
> + }
> + break;
> + case RTAS_EEH_DISABLE:
> + case RTAS_EEH_THAW_IO:
> + case RTAS_EEH_THAW_DMA:
> + break;
> + default:
> + goto param_error_exit;
> + }
> +
> + ret = rtas_handle_eeh_request(spapr, buid,
> + RTAS_EEH_REQ_SET_OPTION, option);
> + if (ret >= 0) {
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> + return;
> + }
> +
> +param_error_exit:
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> +}
> +
> +static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
> + sPAPREnvironment *spapr,
> + uint32_t token, uint32_t nargs,
> + target_ulong args, uint32_t nret,
> + target_ulong rets)
> +{
> + uint32_t addr, option;
> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> + PCIDevice *pdev;
> +
> + if (!sphb || !info->eeh_handler) {
> + goto param_error_exit;
> + }
> +
> + if ((nargs != 4) || (nret != 2)) {
> + goto param_error_exit;
> + }
> +
> + addr = rtas_ld(args, 0);
> + option = rtas_ld(args, 3);
> + if (option != RTAS_GET_PE_ADDR && option != RTAS_GET_PE_MODE) {
> + goto param_error_exit;
> + }
> +
> + pdev = spapr_pci_find_dev(spapr, buid, addr);
> + if (!pdev) {
> + goto param_error_exit;
> + }
> +
> + /*
> + * For now, we always have bus level PE whose address
> + * has format "00BBSS00". The guest OS might regard
> + * PE address 0 as invalid. We avoid that simply by
> + * extending it with one.
> + */
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> + if (option == RTAS_GET_PE_ADDR) {
> + rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
> + } else {
> + rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
> + }
> +
> + return;
> +
> +param_error_exit:
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> +}
> +
> +static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
> + sPAPREnvironment *spapr,
> + uint32_t token, uint32_t nargs,
> + target_ulong args, uint32_t nret,
> + target_ulong rets)
> +{
> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
> + int ret;
> +
> + if ((nargs != 3) || (nret != 4 && nret != 5)) {
> + goto param_error_exit;
> + }
> +
> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_GET_STATE, 0);
> + if (ret >= 0) {
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> + rtas_st(rets, 1, ret);
> + rtas_st(rets, 2, RTAS_EEH_SUPPORT);
> + rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
> + if (nret >= 5) {
> + rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
> + }
> +
> + return;
> + }
> +
> +param_error_exit:
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> +}
> +
> +static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
> + sPAPREnvironment *spapr,
> + uint32_t token, uint32_t nargs,
> + target_ulong args, uint32_t nret,
> + target_ulong rets)
> +{
> + uint32_t option;
> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
> + int ret;
> +
> + if ((nargs != 4) || (nret != 1)) {
> + goto param_error_exit;
> + }
> +
> + option = rtas_ld(args, 3);
> + switch (option) {
> + case RTAS_SLOT_RESET_DEACTIVATE:
> + case RTAS_SLOT_RESET_HOT:
> + case RTAS_SLOT_RESET_FUNDAMENTAL:
> + break;
> + default:
> + goto param_error_exit;
> + }
> +
> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_RESET, option);
> + if (ret >= 0) {
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> + return;
> + }
> +
> +param_error_exit:
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> +}
> +
> +static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
> + sPAPREnvironment *spapr,
> + uint32_t token, uint32_t nargs,
> + target_ulong args, uint32_t nret,
> + target_ulong rets)
> +{
> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
> + int ret;
> +
> + if ((nargs != 3) || (nret != 1)) {
> + goto param_error_exit;
> + }
> +
> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_CONFIGURE, 0);
> + if (ret >= 0) {
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> + return;
> + }
> +
> +param_error_exit:
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> +}
> +
> +/* To support it later */
> +static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
> + sPAPREnvironment *spapr,
> + uint32_t token, uint32_t nargs,
> + target_ulong args, uint32_t nret,
> + target_ulong rets)
> +{
> + int option;
> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> +
> + if (!sphb || !info->eeh_handler) {
> + goto param_error_exit;
> + }
> +
> + if ((nargs != 8) || (nret != 1)) {
> + goto param_error_exit;
> + }
> +
> + option = rtas_ld(args, 7);
> + switch (option) {
> + case RTAS_SLOT_TEMP_ERR_LOG:
> + case RTAS_SLOT_PERM_ERR_LOG:
> + break;
> + default:
> + goto param_error_exit;
> + }
> +
> + rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
> + return;
> +
> +param_error_exit:
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> +}
> +
> static int pci_spapr_swizzle(int slot, int pin)
> {
> return (slot + pin) % PCI_NUM_PINS;
> @@ -953,6 +1180,25 @@ void spapr_pci_rtas_init(void)
> spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
> rtas_ibm_change_msi);
> }
> +
> + spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
> + "ibm,set-eeh-option",
> + rtas_ibm_set_eeh_option);
> + spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
> + "ibm,get-config-addr-info2",
> + rtas_ibm_get_config_addr_info2);
> + spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
> + "ibm,read-slot-reset-state2",
> + rtas_ibm_read_slot_reset_state2);
> + spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
> + "ibm,set-slot-reset",
> + rtas_ibm_set_slot_reset);
> + spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
> + "ibm,configure-pe",
> + rtas_ibm_configure_pe);
> + spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
> + "ibm,slot-error-detail",
> + rtas_ibm_slot_error_detail);
> }
>
> static void spapr_pci_register_types(void)
> diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
> index 14c2ab0..ea39aa6 100644
> --- a/include/hw/pci-host/spapr.h
> +++ b/include/hw/pci-host/spapr.h
> @@ -49,6 +49,7 @@ struct sPAPRPHBClass {
> PCIHostBridgeClass parent_class;
>
> void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
> + int (*eeh_handler)(sPAPRPHBState *sphb, int req, int opt);
> };
>
> typedef struct spapr_pci_msi {
> @@ -107,6 +108,12 @@ struct sPAPRPHBVFIOState {
>
> #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
>
> +/* EEH related requests */
> +#define RTAS_EEH_REQ_SET_OPTION 0
> +#define RTAS_EEH_REQ_GET_STATE 1
> +#define RTAS_EEH_REQ_RESET 2
> +#define RTAS_EEH_REQ_CONFIGURE 3
> +
> static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
> {
> return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index bbba51a..f74c7f2 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -338,6 +338,39 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
> int spapr_allocate_irq(int hint, bool lsi);
> int spapr_allocate_irq_block(int num, bool lsi, bool msi);
>
> +/* ibm,set-eeh-option */
> +#define RTAS_EEH_DISABLE 0
> +#define RTAS_EEH_ENABLE 1
> +#define RTAS_EEH_THAW_IO 2
> +#define RTAS_EEH_THAW_DMA 3
> +
> +/* ibm,get-config-addr-info2 */
> +#define RTAS_GET_PE_ADDR 0
> +#define RTAS_GET_PE_MODE 1
> +#define RTAS_PE_MODE_NONE 0
> +#define RTAS_PE_MODE_NOT_SHARED 1
> +#define RTAS_PE_MODE_SHARED 2
> +
> +/* ibm,read-slot-reset-state2 */
> +#define RTAS_EEH_PE_STATE_NORMAL 0
> +#define RTAS_EEH_PE_STATE_RESET 1
> +#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
> +#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
> +#define RTAS_EEH_PE_STATE_UNAVAIL 5
> +#define RTAS_EEH_NOT_SUPPORT 0
> +#define RTAS_EEH_SUPPORT 1
> +#define RTAS_EEH_PE_UNAVAIL_INFO 1000
> +#define RTAS_EEH_PE_RECOVER_INFO 0
> +
> +/* ibm,set-slot-reset */
> +#define RTAS_SLOT_RESET_DEACTIVATE 0
> +#define RTAS_SLOT_RESET_HOT 1
> +#define RTAS_SLOT_RESET_FUNDAMENTAL 3
> +
> +/* ibm,slot-error-detail */
> +#define RTAS_SLOT_TEMP_ERR_LOG 1
> +#define RTAS_SLOT_PERM_ERR_LOG 2
> +
> /* RTAS return codes */
> #define RTAS_OUT_SUCCESS 0
> #define RTAS_OUT_NO_ERRORS_FOUND 1
> @@ -383,8 +416,14 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
> #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
> #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
> #define RTAS_IBM_EXTENDED_OS_TERM (RTAS_TOKEN_BASE + 0x20)
Rebase your set on top ppc-next-2.2 from git://github.com/agraf/qemu.git
RTAS_IBM_EXTENDED_OS_TERM is not there.
> -
> -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x21)
> +#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x21)
> +#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x22)
> +#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x23)
> +#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x24)
> +#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x25)
> +#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x26)
> +
> +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x27)
>
> /* RTAS ibm,get-system-parameter token values */
> #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
>
--
Alexey
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header Gavin Shan
@ 2014-07-16 1:09 ` Alexey Kardashevskiy
2014-07-16 1:16 ` Gavin Shan
0 siblings, 1 reply; 15+ messages in thread
From: Alexey Kardashevskiy @ 2014-07-16 1:09 UTC (permalink / raw)
To: Gavin Shan, qemu-ppc; +Cc: alex.williamson, qemu-devel, agraf
On 07/16/2014 10:20 AM, Gavin Shan wrote:
> This updates kernel header (vfio.h) for EEH support on VFIO PCI
> devices.
Has this reached kernel upstream? The way linux headers update normally
happens is you have to run scripts/update-linux-headers.sh against some
linux kernel tag which you know that it won't change (like v3.16-rc5) and
post all the changes as a single patch. It is never a header update for a
specific feature, it is just an update.
>
> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
> ---
> linux-headers/linux/vfio.h | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
> index 26c218e..95b591b 100644
> --- a/linux-headers/linux/vfio.h
> +++ b/linux-headers/linux/vfio.h
> @@ -30,6 +30,9 @@
> */
> #define VFIO_DMA_CC_IOMMU 4
>
> +/* Check if EEH is supported */
> +#define VFIO_EEH 5
> +
> /*
> * The IOCTL interface is designed for extensibility by embedding the
> * structure length (argsz) and flags into structures passed between
> @@ -455,6 +458,37 @@ struct vfio_iommu_spapr_tce_info {
>
> #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
>
> +/*
> + * EEH PE operation struct provides ways to:
> + * - enable/disable EEH functionality;
> + * - unfreeze IO/DMA for frozen PE;
> + * - read PE state;
> + * - reset PE;
> + * - configure PE.
> + */
> +struct vfio_eeh_pe_op {
> + __u32 argsz;
> + __u32 flags;
> + __u32 op;
> +};
> +
> +#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
> +#define VFIO_EEH_PE_ENABLE 1 /* Enable EEH functionality */
> +#define VFIO_EEH_PE_UNFREEZE_IO 2 /* Enable IO for frozen PE */
> +#define VFIO_EEH_PE_UNFREEZE_DMA 3 /* Enable DMA for frozen PE */
> +#define VFIO_EEH_PE_GET_STATE 4 /* PE state retrieval */
> +#define VFIO_EEH_PE_STATE_NORMAL 0 /* PE in functional state */
> +#define VFIO_EEH_PE_STATE_RESET 1 /* PE reset in progress */
> +#define VFIO_EEH_PE_STATE_STOPPED 2 /* Stopped DMA and IO */
> +#define VFIO_EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
> +#define VFIO_EEH_PE_STATE_UNAVAIL 5 /* State unavailable */
> +#define VFIO_EEH_PE_RESET_DEACTIVATE 5 /* Deassert PE reset */
> +#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
> +#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
> +#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
> +
> +#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
> +
> /* ***************************************************************** */
>
> #endif /* VFIO_H */
>
--
Alexey
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls
2014-07-16 1:06 ` Alexey Kardashevskiy
@ 2014-07-16 1:12 ` Gavin Shan
2014-07-16 1:28 ` Alexey Kardashevskiy
0 siblings, 1 reply; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 1:12 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: qemu-devel, agraf, Gavin Shan, alex.williamson, qemu-ppc
On Wed, Jul 16, 2014 at 11:06:21AM +1000, Alexey Kardashevskiy wrote:
>On 07/16/2014 10:20 AM, Gavin Shan wrote:
>> The emulation for EEH RTAS requests from guest isn't covered
>> by QEMU yet and the patch implements them.
>>
>> The patch defines constants used by EEH RTAS calls and adds
>> callback sPAPRPHBClass::eeh_handler, which is going to be used
>> this way:
>>
>> * RTAS calls are received in spapr_pci.c, sanity check is done
>> there.
>> * RTAS handlers handle what they can. If there is something it
>> cannot handle and sPAPRPHBClass::eeh_handler callback is defined,
>> it is called.
>> * sPAPRPHBClass::eeh_handler is only implemented for VFIO now. It
>> does ioctl() to the IOMMU container fd to complete the call. Error
>> codes from that ioctl() are transferred back to the guest.
>>
>> [aik: defined RTAS tokens for EEH RTAS calls]
>> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
>> ---
>> hw/ppc/spapr_pci.c | 246 ++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/pci-host/spapr.h | 7 ++
>> include/hw/ppc/spapr.h | 43 +++++++-
>> 3 files changed, 294 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
>> index 230b59c..63394f5 100644
>> --- a/hw/ppc/spapr_pci.c
>> +++ b/hw/ppc/spapr_pci.c
>> @@ -402,6 +402,233 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
>> rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
>> }
>>
>> +static int rtas_handle_eeh_request(sPAPREnvironment *spapr,
>> + uint64_t buid, uint32_t req, uint32_t opt)
>> +{
>> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
>> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
>> +
>> + if (!sphb || !info->eeh_handler) {
>> + return -ENOENT;
>> + }
>> +
>> + return info->eeh_handler(sphb, req, opt);
>> +}
>> +
>> +static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
>> + sPAPREnvironment *spapr,
>> + uint32_t token, uint32_t nargs,
>> + target_ulong args, uint32_t nret,
>> + target_ulong rets)
>> +{
>> + uint32_t addr, option;
>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>> + int ret;
>> +
>> + if ((nargs != 4) || (nret != 1)) {
>> + goto param_error_exit;
>> + }
>> +
>> + addr = rtas_ld(args, 0);
>> + option = rtas_ld(args, 3);
>> + switch (option) {
>> + case RTAS_EEH_ENABLE:
>> + if (!spapr_pci_find_dev(spapr, buid, addr)) {
>> + goto param_error_exit;
>> + }
>> + break;
>> + case RTAS_EEH_DISABLE:
>> + case RTAS_EEH_THAW_IO:
>> + case RTAS_EEH_THAW_DMA:
>> + break;
>> + default:
>> + goto param_error_exit;
>> + }
>> +
>> + ret = rtas_handle_eeh_request(spapr, buid,
>> + RTAS_EEH_REQ_SET_OPTION, option);
>> + if (ret >= 0) {
>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>> + return;
>> + }
>> +
>> +param_error_exit:
>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> +}
>> +
>> +static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
>> + sPAPREnvironment *spapr,
>> + uint32_t token, uint32_t nargs,
>> + target_ulong args, uint32_t nret,
>> + target_ulong rets)
>> +{
>> + uint32_t addr, option;
>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
>> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
>> + PCIDevice *pdev;
>> +
>> + if (!sphb || !info->eeh_handler) {
>> + goto param_error_exit;
>> + }
>> +
>> + if ((nargs != 4) || (nret != 2)) {
>> + goto param_error_exit;
>> + }
>> +
>> + addr = rtas_ld(args, 0);
>> + option = rtas_ld(args, 3);
>> + if (option != RTAS_GET_PE_ADDR && option != RTAS_GET_PE_MODE) {
>> + goto param_error_exit;
>> + }
>> +
>> + pdev = spapr_pci_find_dev(spapr, buid, addr);
>> + if (!pdev) {
>> + goto param_error_exit;
>> + }
>> +
>> + /*
>> + * For now, we always have bus level PE whose address
>> + * has format "00BBSS00". The guest OS might regard
>> + * PE address 0 as invalid. We avoid that simply by
>> + * extending it with one.
>> + */
>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>> + if (option == RTAS_GET_PE_ADDR) {
>> + rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
>> + } else {
>> + rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
>> + }
>> +
>> + return;
>> +
>> +param_error_exit:
>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> +}
>> +
>> +static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
>> + sPAPREnvironment *spapr,
>> + uint32_t token, uint32_t nargs,
>> + target_ulong args, uint32_t nret,
>> + target_ulong rets)
>> +{
>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>> + int ret;
>> +
>> + if ((nargs != 3) || (nret != 4 && nret != 5)) {
>> + goto param_error_exit;
>> + }
>> +
>> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_GET_STATE, 0);
>> + if (ret >= 0) {
>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>> + rtas_st(rets, 1, ret);
>> + rtas_st(rets, 2, RTAS_EEH_SUPPORT);
>> + rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
>> + if (nret >= 5) {
>> + rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
>> + }
>> +
>> + return;
>> + }
>> +
>> +param_error_exit:
>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> +}
>> +
>> +static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
>> + sPAPREnvironment *spapr,
>> + uint32_t token, uint32_t nargs,
>> + target_ulong args, uint32_t nret,
>> + target_ulong rets)
>> +{
>> + uint32_t option;
>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>> + int ret;
>> +
>> + if ((nargs != 4) || (nret != 1)) {
>> + goto param_error_exit;
>> + }
>> +
>> + option = rtas_ld(args, 3);
>> + switch (option) {
>> + case RTAS_SLOT_RESET_DEACTIVATE:
>> + case RTAS_SLOT_RESET_HOT:
>> + case RTAS_SLOT_RESET_FUNDAMENTAL:
>> + break;
>> + default:
>> + goto param_error_exit;
>> + }
>> +
>> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_RESET, option);
>> + if (ret >= 0) {
>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>> + return;
>> + }
>> +
>> +param_error_exit:
>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> +}
>> +
>> +static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
>> + sPAPREnvironment *spapr,
>> + uint32_t token, uint32_t nargs,
>> + target_ulong args, uint32_t nret,
>> + target_ulong rets)
>> +{
>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>> + int ret;
>> +
>> + if ((nargs != 3) || (nret != 1)) {
>> + goto param_error_exit;
>> + }
>> +
>> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_CONFIGURE, 0);
>> + if (ret >= 0) {
>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>> + return;
>> + }
>> +
>> +param_error_exit:
>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> +}
>> +
>> +/* To support it later */
>> +static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
>> + sPAPREnvironment *spapr,
>> + uint32_t token, uint32_t nargs,
>> + target_ulong args, uint32_t nret,
>> + target_ulong rets)
>> +{
>> + int option;
>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
>> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
>> +
>> + if (!sphb || !info->eeh_handler) {
>> + goto param_error_exit;
>> + }
>> +
>> + if ((nargs != 8) || (nret != 1)) {
>> + goto param_error_exit;
>> + }
>> +
>> + option = rtas_ld(args, 7);
>> + switch (option) {
>> + case RTAS_SLOT_TEMP_ERR_LOG:
>> + case RTAS_SLOT_PERM_ERR_LOG:
>> + break;
>> + default:
>> + goto param_error_exit;
>> + }
>> +
>> + rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
>> + return;
>> +
>> +param_error_exit:
>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> +}
>> +
>> static int pci_spapr_swizzle(int slot, int pin)
>> {
>> return (slot + pin) % PCI_NUM_PINS;
>> @@ -953,6 +1180,25 @@ void spapr_pci_rtas_init(void)
>> spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
>> rtas_ibm_change_msi);
>> }
>> +
>> + spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
>> + "ibm,set-eeh-option",
>> + rtas_ibm_set_eeh_option);
>> + spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
>> + "ibm,get-config-addr-info2",
>> + rtas_ibm_get_config_addr_info2);
>> + spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
>> + "ibm,read-slot-reset-state2",
>> + rtas_ibm_read_slot_reset_state2);
>> + spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
>> + "ibm,set-slot-reset",
>> + rtas_ibm_set_slot_reset);
>> + spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
>> + "ibm,configure-pe",
>> + rtas_ibm_configure_pe);
>> + spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
>> + "ibm,slot-error-detail",
>> + rtas_ibm_slot_error_detail);
>> }
>>
>> static void spapr_pci_register_types(void)
>> diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
>> index 14c2ab0..ea39aa6 100644
>> --- a/include/hw/pci-host/spapr.h
>> +++ b/include/hw/pci-host/spapr.h
>> @@ -49,6 +49,7 @@ struct sPAPRPHBClass {
>> PCIHostBridgeClass parent_class;
>>
>> void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
>> + int (*eeh_handler)(sPAPRPHBState *sphb, int req, int opt);
>> };
>>
>> typedef struct spapr_pci_msi {
>> @@ -107,6 +108,12 @@ struct sPAPRPHBVFIOState {
>>
>> #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
>>
>> +/* EEH related requests */
>> +#define RTAS_EEH_REQ_SET_OPTION 0
>> +#define RTAS_EEH_REQ_GET_STATE 1
>> +#define RTAS_EEH_REQ_RESET 2
>> +#define RTAS_EEH_REQ_CONFIGURE 3
>> +
>> static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
>> {
>> return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
>> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
>> index bbba51a..f74c7f2 100644
>> --- a/include/hw/ppc/spapr.h
>> +++ b/include/hw/ppc/spapr.h
>> @@ -338,6 +338,39 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
>> int spapr_allocate_irq(int hint, bool lsi);
>> int spapr_allocate_irq_block(int num, bool lsi, bool msi);
>>
>> +/* ibm,set-eeh-option */
>> +#define RTAS_EEH_DISABLE 0
>> +#define RTAS_EEH_ENABLE 1
>> +#define RTAS_EEH_THAW_IO 2
>> +#define RTAS_EEH_THAW_DMA 3
>> +
>> +/* ibm,get-config-addr-info2 */
>> +#define RTAS_GET_PE_ADDR 0
>> +#define RTAS_GET_PE_MODE 1
>> +#define RTAS_PE_MODE_NONE 0
>> +#define RTAS_PE_MODE_NOT_SHARED 1
>> +#define RTAS_PE_MODE_SHARED 2
>> +
>> +/* ibm,read-slot-reset-state2 */
>> +#define RTAS_EEH_PE_STATE_NORMAL 0
>> +#define RTAS_EEH_PE_STATE_RESET 1
>> +#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
>> +#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
>> +#define RTAS_EEH_PE_STATE_UNAVAIL 5
>> +#define RTAS_EEH_NOT_SUPPORT 0
>> +#define RTAS_EEH_SUPPORT 1
>> +#define RTAS_EEH_PE_UNAVAIL_INFO 1000
>> +#define RTAS_EEH_PE_RECOVER_INFO 0
>> +
>> +/* ibm,set-slot-reset */
>> +#define RTAS_SLOT_RESET_DEACTIVATE 0
>> +#define RTAS_SLOT_RESET_HOT 1
>> +#define RTAS_SLOT_RESET_FUNDAMENTAL 3
>> +
>> +/* ibm,slot-error-detail */
>> +#define RTAS_SLOT_TEMP_ERR_LOG 1
>> +#define RTAS_SLOT_PERM_ERR_LOG 2
>> +
>> /* RTAS return codes */
>> #define RTAS_OUT_SUCCESS 0
>> #define RTAS_OUT_NO_ERRORS_FOUND 1
>> @@ -383,8 +416,14 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
>> #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
>> #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
>> #define RTAS_IBM_EXTENDED_OS_TERM (RTAS_TOKEN_BASE + 0x20)
>
>
>Rebase your set on top ppc-next-2.2 from git://github.com/agraf/qemu.git
>
>RTAS_IBM_EXTENDED_OS_TERM is not there.
>
Ok, I'll rebase. One question: which branch should be used as development
in Alex.G's repository?
remotes/origin/ppc-next
remotes/origin/ppc-next-1.8
remotes/origin/ppc-next-2.1
remotes/origin/ppc-next-2.2
Thanks,
Gavin
>
>> -
>> -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x21)
>> +#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x21)
>> +#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x22)
>> +#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x23)
>> +#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x24)
>> +#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x25)
>> +#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x26)
>> +
>> +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x27)
>>
>> /* RTAS ibm,get-system-parameter token values */
>> #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
>>
>
>
>--
>Alexey
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header
2014-07-16 1:09 ` Alexey Kardashevskiy
@ 2014-07-16 1:16 ` Gavin Shan
2014-07-16 1:32 ` Alexey Kardashevskiy
0 siblings, 1 reply; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 1:16 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: qemu-devel, agraf, Gavin Shan, alex.williamson, qemu-ppc
On Wed, Jul 16, 2014 at 11:09:44AM +1000, Alexey Kardashevskiy wrote:
>On 07/16/2014 10:20 AM, Gavin Shan wrote:
>> This updates kernel header (vfio.h) for EEH support on VFIO PCI
>> devices.
>
>Has this reached kernel upstream? The way linux headers update normally
>happens is you have to run scripts/update-linux-headers.sh against some
>linux kernel tag which you know that it won't change (like v3.16-rc5) and
>post all the changes as a single patch. It is never a header update for a
>specific feature, it is just an update.
>
The kernel part isn't merged yet. I guess that's for 3.17 merge window.
Ok, good to know scripts/update-linux-headers.sh. So this patch should
be dropped and some one run the script to update QEMU (linux-headers
directory) ?
Thanks,
Gavin
>
>>
>> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
>> ---
>> linux-headers/linux/vfio.h | 34 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 34 insertions(+)
>>
>> diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
>> index 26c218e..95b591b 100644
>> --- a/linux-headers/linux/vfio.h
>> +++ b/linux-headers/linux/vfio.h
>> @@ -30,6 +30,9 @@
>> */
>> #define VFIO_DMA_CC_IOMMU 4
>>
>> +/* Check if EEH is supported */
>> +#define VFIO_EEH 5
>> +
>> /*
>> * The IOCTL interface is designed for extensibility by embedding the
>> * structure length (argsz) and flags into structures passed between
>> @@ -455,6 +458,37 @@ struct vfio_iommu_spapr_tce_info {
>>
>> #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
>>
>> +/*
>> + * EEH PE operation struct provides ways to:
>> + * - enable/disable EEH functionality;
>> + * - unfreeze IO/DMA for frozen PE;
>> + * - read PE state;
>> + * - reset PE;
>> + * - configure PE.
>> + */
>> +struct vfio_eeh_pe_op {
>> + __u32 argsz;
>> + __u32 flags;
>> + __u32 op;
>> +};
>> +
>> +#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
>> +#define VFIO_EEH_PE_ENABLE 1 /* Enable EEH functionality */
>> +#define VFIO_EEH_PE_UNFREEZE_IO 2 /* Enable IO for frozen PE */
>> +#define VFIO_EEH_PE_UNFREEZE_DMA 3 /* Enable DMA for frozen PE */
>> +#define VFIO_EEH_PE_GET_STATE 4 /* PE state retrieval */
>> +#define VFIO_EEH_PE_STATE_NORMAL 0 /* PE in functional state */
>> +#define VFIO_EEH_PE_STATE_RESET 1 /* PE reset in progress */
>> +#define VFIO_EEH_PE_STATE_STOPPED 2 /* Stopped DMA and IO */
>> +#define VFIO_EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
>> +#define VFIO_EEH_PE_STATE_UNAVAIL 5 /* State unavailable */
>> +#define VFIO_EEH_PE_RESET_DEACTIVATE 5 /* Deassert PE reset */
>> +#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
>> +#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
>> +#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
>> +
>> +#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
>> +
>> /* ***************************************************************** */
>>
>> #endif /* VFIO_H */
>>
>
>
>--
>Alexey
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls
2014-07-16 1:12 ` Gavin Shan
@ 2014-07-16 1:28 ` Alexey Kardashevskiy
0 siblings, 0 replies; 15+ messages in thread
From: Alexey Kardashevskiy @ 2014-07-16 1:28 UTC (permalink / raw)
To: Gavin Shan; +Cc: alex.williamson, qemu-ppc, qemu-devel, agraf
On 07/16/2014 11:12 AM, Gavin Shan wrote:
> On Wed, Jul 16, 2014 at 11:06:21AM +1000, Alexey Kardashevskiy wrote:
>> On 07/16/2014 10:20 AM, Gavin Shan wrote:
>>> The emulation for EEH RTAS requests from guest isn't covered
>>> by QEMU yet and the patch implements them.
>>>
>>> The patch defines constants used by EEH RTAS calls and adds
>>> callback sPAPRPHBClass::eeh_handler, which is going to be used
>>> this way:
>>>
>>> * RTAS calls are received in spapr_pci.c, sanity check is done
>>> there.
>>> * RTAS handlers handle what they can. If there is something it
>>> cannot handle and sPAPRPHBClass::eeh_handler callback is defined,
>>> it is called.
>>> * sPAPRPHBClass::eeh_handler is only implemented for VFIO now. It
>>> does ioctl() to the IOMMU container fd to complete the call. Error
>>> codes from that ioctl() are transferred back to the guest.
>>>
>>> [aik: defined RTAS tokens for EEH RTAS calls]
>>> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
>>> ---
>>> hw/ppc/spapr_pci.c | 246 ++++++++++++++++++++++++++++++++++++++++++++
>>> include/hw/pci-host/spapr.h | 7 ++
>>> include/hw/ppc/spapr.h | 43 +++++++-
>>> 3 files changed, 294 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
>>> index 230b59c..63394f5 100644
>>> --- a/hw/ppc/spapr_pci.c
>>> +++ b/hw/ppc/spapr_pci.c
>>> @@ -402,6 +402,233 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
>>> rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
>>> }
>>>
>>> +static int rtas_handle_eeh_request(sPAPREnvironment *spapr,
>>> + uint64_t buid, uint32_t req, uint32_t opt)
>>> +{
>>> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
>>> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
>>> +
>>> + if (!sphb || !info->eeh_handler) {
>>> + return -ENOENT;
>>> + }
>>> +
>>> + return info->eeh_handler(sphb, req, opt);
>>> +}
>>> +
>>> +static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args, uint32_t nret,
>>> + target_ulong rets)
>>> +{
>>> + uint32_t addr, option;
>>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>>> + int ret;
>>> +
>>> + if ((nargs != 4) || (nret != 1)) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + addr = rtas_ld(args, 0);
>>> + option = rtas_ld(args, 3);
>>> + switch (option) {
>>> + case RTAS_EEH_ENABLE:
>>> + if (!spapr_pci_find_dev(spapr, buid, addr)) {
>>> + goto param_error_exit;
>>> + }
>>> + break;
>>> + case RTAS_EEH_DISABLE:
>>> + case RTAS_EEH_THAW_IO:
>>> + case RTAS_EEH_THAW_DMA:
>>> + break;
>>> + default:
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + ret = rtas_handle_eeh_request(spapr, buid,
>>> + RTAS_EEH_REQ_SET_OPTION, option);
>>> + if (ret >= 0) {
>>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>>> + return;
>>> + }
>>> +
>>> +param_error_exit:
>>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>>> +}
>>> +
>>> +static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args, uint32_t nret,
>>> + target_ulong rets)
>>> +{
>>> + uint32_t addr, option;
>>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>>> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
>>> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
>>> + PCIDevice *pdev;
>>> +
>>> + if (!sphb || !info->eeh_handler) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + if ((nargs != 4) || (nret != 2)) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + addr = rtas_ld(args, 0);
>>> + option = rtas_ld(args, 3);
>>> + if (option != RTAS_GET_PE_ADDR && option != RTAS_GET_PE_MODE) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + pdev = spapr_pci_find_dev(spapr, buid, addr);
>>> + if (!pdev) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + /*
>>> + * For now, we always have bus level PE whose address
>>> + * has format "00BBSS00". The guest OS might regard
>>> + * PE address 0 as invalid. We avoid that simply by
>>> + * extending it with one.
>>> + */
>>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>>> + if (option == RTAS_GET_PE_ADDR) {
>>> + rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
>>> + } else {
>>> + rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
>>> + }
>>> +
>>> + return;
>>> +
>>> +param_error_exit:
>>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>>> +}
>>> +
>>> +static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args, uint32_t nret,
>>> + target_ulong rets)
>>> +{
>>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>>> + int ret;
>>> +
>>> + if ((nargs != 3) || (nret != 4 && nret != 5)) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_GET_STATE, 0);
>>> + if (ret >= 0) {
>>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>>> + rtas_st(rets, 1, ret);
>>> + rtas_st(rets, 2, RTAS_EEH_SUPPORT);
>>> + rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
>>> + if (nret >= 5) {
>>> + rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
>>> + }
>>> +
>>> + return;
>>> + }
>>> +
>>> +param_error_exit:
>>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>>> +}
>>> +
>>> +static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args, uint32_t nret,
>>> + target_ulong rets)
>>> +{
>>> + uint32_t option;
>>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>>> + int ret;
>>> +
>>> + if ((nargs != 4) || (nret != 1)) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + option = rtas_ld(args, 3);
>>> + switch (option) {
>>> + case RTAS_SLOT_RESET_DEACTIVATE:
>>> + case RTAS_SLOT_RESET_HOT:
>>> + case RTAS_SLOT_RESET_FUNDAMENTAL:
>>> + break;
>>> + default:
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_RESET, option);
>>> + if (ret >= 0) {
>>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>>> + return;
>>> + }
>>> +
>>> +param_error_exit:
>>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>>> +}
>>> +
>>> +static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args, uint32_t nret,
>>> + target_ulong rets)
>>> +{
>>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>>> + int ret;
>>> +
>>> + if ((nargs != 3) || (nret != 1)) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + ret = rtas_handle_eeh_request(spapr, buid, RTAS_EEH_REQ_CONFIGURE, 0);
>>> + if (ret >= 0) {
>>> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>>> + return;
>>> + }
>>> +
>>> +param_error_exit:
>>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>>> +}
>>> +
>>> +/* To support it later */
>>> +static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args, uint32_t nret,
>>> + target_ulong rets)
>>> +{
>>> + int option;
>>> + uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
>>> + sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
>>> + sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
>>> +
>>> + if (!sphb || !info->eeh_handler) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + if ((nargs != 8) || (nret != 1)) {
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + option = rtas_ld(args, 7);
>>> + switch (option) {
>>> + case RTAS_SLOT_TEMP_ERR_LOG:
>>> + case RTAS_SLOT_PERM_ERR_LOG:
>>> + break;
>>> + default:
>>> + goto param_error_exit;
>>> + }
>>> +
>>> + rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
>>> + return;
>>> +
>>> +param_error_exit:
>>> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>>> +}
>>> +
>>> static int pci_spapr_swizzle(int slot, int pin)
>>> {
>>> return (slot + pin) % PCI_NUM_PINS;
>>> @@ -953,6 +1180,25 @@ void spapr_pci_rtas_init(void)
>>> spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
>>> rtas_ibm_change_msi);
>>> }
>>> +
>>> + spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
>>> + "ibm,set-eeh-option",
>>> + rtas_ibm_set_eeh_option);
>>> + spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
>>> + "ibm,get-config-addr-info2",
>>> + rtas_ibm_get_config_addr_info2);
>>> + spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
>>> + "ibm,read-slot-reset-state2",
>>> + rtas_ibm_read_slot_reset_state2);
>>> + spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
>>> + "ibm,set-slot-reset",
>>> + rtas_ibm_set_slot_reset);
>>> + spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
>>> + "ibm,configure-pe",
>>> + rtas_ibm_configure_pe);
>>> + spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
>>> + "ibm,slot-error-detail",
>>> + rtas_ibm_slot_error_detail);
>>> }
>>>
>>> static void spapr_pci_register_types(void)
>>> diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
>>> index 14c2ab0..ea39aa6 100644
>>> --- a/include/hw/pci-host/spapr.h
>>> +++ b/include/hw/pci-host/spapr.h
>>> @@ -49,6 +49,7 @@ struct sPAPRPHBClass {
>>> PCIHostBridgeClass parent_class;
>>>
>>> void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
>>> + int (*eeh_handler)(sPAPRPHBState *sphb, int req, int opt);
>>> };
>>>
>>> typedef struct spapr_pci_msi {
>>> @@ -107,6 +108,12 @@ struct sPAPRPHBVFIOState {
>>>
>>> #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
>>>
>>> +/* EEH related requests */
>>> +#define RTAS_EEH_REQ_SET_OPTION 0
>>> +#define RTAS_EEH_REQ_GET_STATE 1
>>> +#define RTAS_EEH_REQ_RESET 2
>>> +#define RTAS_EEH_REQ_CONFIGURE 3
>>> +
>>> static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
>>> {
>>> return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
>>> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
>>> index bbba51a..f74c7f2 100644
>>> --- a/include/hw/ppc/spapr.h
>>> +++ b/include/hw/ppc/spapr.h
>>> @@ -338,6 +338,39 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
>>> int spapr_allocate_irq(int hint, bool lsi);
>>> int spapr_allocate_irq_block(int num, bool lsi, bool msi);
>>>
>>> +/* ibm,set-eeh-option */
>>> +#define RTAS_EEH_DISABLE 0
>>> +#define RTAS_EEH_ENABLE 1
>>> +#define RTAS_EEH_THAW_IO 2
>>> +#define RTAS_EEH_THAW_DMA 3
>>> +
>>> +/* ibm,get-config-addr-info2 */
>>> +#define RTAS_GET_PE_ADDR 0
>>> +#define RTAS_GET_PE_MODE 1
>>> +#define RTAS_PE_MODE_NONE 0
>>> +#define RTAS_PE_MODE_NOT_SHARED 1
>>> +#define RTAS_PE_MODE_SHARED 2
>>> +
>>> +/* ibm,read-slot-reset-state2 */
>>> +#define RTAS_EEH_PE_STATE_NORMAL 0
>>> +#define RTAS_EEH_PE_STATE_RESET 1
>>> +#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
>>> +#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
>>> +#define RTAS_EEH_PE_STATE_UNAVAIL 5
>>> +#define RTAS_EEH_NOT_SUPPORT 0
>>> +#define RTAS_EEH_SUPPORT 1
>>> +#define RTAS_EEH_PE_UNAVAIL_INFO 1000
>>> +#define RTAS_EEH_PE_RECOVER_INFO 0
>>> +
>>> +/* ibm,set-slot-reset */
>>> +#define RTAS_SLOT_RESET_DEACTIVATE 0
>>> +#define RTAS_SLOT_RESET_HOT 1
>>> +#define RTAS_SLOT_RESET_FUNDAMENTAL 3
>>> +
>>> +/* ibm,slot-error-detail */
>>> +#define RTAS_SLOT_TEMP_ERR_LOG 1
>>> +#define RTAS_SLOT_PERM_ERR_LOG 2
>>> +
>>> /* RTAS return codes */
>>> #define RTAS_OUT_SUCCESS 0
>>> #define RTAS_OUT_NO_ERRORS_FOUND 1
>>> @@ -383,8 +416,14 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
>>> #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
>>> #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
>>> #define RTAS_IBM_EXTENDED_OS_TERM (RTAS_TOKEN_BASE + 0x20)
>>
>>
>> Rebase your set on top ppc-next-2.2 from git://github.com/agraf/qemu.git
>>
>> RTAS_IBM_EXTENDED_OS_TERM is not there.
>>
>
> Ok, I'll rebase. One question: which branch should be used as development
> in Alex.G's repository?
>
> remotes/origin/ppc-next
> remotes/origin/ppc-next-1.8
> remotes/origin/ppc-next-2.1
> remotes/origin/ppc-next-2.2
Normally it would be "ppc-next" but QEMU is in feature freeze now and 2.1
is the closest release so you have to use ppc-next-2.2 (next QEMU version).
Once 2.1 released, "ppc-next-2.2" will become "ppc-next".
>
> Thanks,
> Gavin
>
>>
>>> -
>>> -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x21)
>>> +#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x21)
>>> +#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x22)
>>> +#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x23)
>>> +#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x24)
>>> +#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x25)
>>> +#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x26)
>>> +
>>> +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x27)
>>>
>>> /* RTAS ibm,get-system-parameter token values */
>>> #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
>>>
>>
>>
>> --
>> Alexey
>>
>
--
Alexey
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header
2014-07-16 1:16 ` Gavin Shan
@ 2014-07-16 1:32 ` Alexey Kardashevskiy
2014-07-16 1:40 ` Gavin Shan
0 siblings, 1 reply; 15+ messages in thread
From: Alexey Kardashevskiy @ 2014-07-16 1:32 UTC (permalink / raw)
To: Gavin Shan; +Cc: alex.williamson, qemu-ppc, qemu-devel, agraf
On 07/16/2014 11:16 AM, Gavin Shan wrote:
> On Wed, Jul 16, 2014 at 11:09:44AM +1000, Alexey Kardashevskiy wrote:
>> On 07/16/2014 10:20 AM, Gavin Shan wrote:
>>> This updates kernel header (vfio.h) for EEH support on VFIO PCI
>>> devices.
>>
>> Has this reached kernel upstream? The way linux headers update normally
>> happens is you have to run scripts/update-linux-headers.sh against some
>> linux kernel tag which you know that it won't change (like v3.16-rc5) and
>> post all the changes as a single patch. It is never a header update for a
>> specific feature, it is just an update.
>>
>
> The kernel part isn't merged yet. I guess that's for 3.17 merge window.
> Ok, good to know scripts/update-linux-headers.sh. So this patch should
> be dropped and some one run the script to update QEMU (linux-headers
> directory) ?
Once your changes are in upstream kernel, you wait till kernel tree gets
new "v3.xx-rcX" tag, then you run the script and make a separate patch for
QEMU. Then you wait till it reaches QEMU upstream (because I do not know
who will pull it to what tree, look at git history) or ppc-next (if Alex
pulls it and you are basing your work on ppc-next) and then repost other
patches.
>
> Thanks,
> Gavin
>
>>
>>>
>>> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
>>> ---
>>> linux-headers/linux/vfio.h | 34 ++++++++++++++++++++++++++++++++++
>>> 1 file changed, 34 insertions(+)
>>>
>>> diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
>>> index 26c218e..95b591b 100644
>>> --- a/linux-headers/linux/vfio.h
>>> +++ b/linux-headers/linux/vfio.h
>>> @@ -30,6 +30,9 @@
>>> */
>>> #define VFIO_DMA_CC_IOMMU 4
>>>
>>> +/* Check if EEH is supported */
>>> +#define VFIO_EEH 5
>>> +
>>> /*
>>> * The IOCTL interface is designed for extensibility by embedding the
>>> * structure length (argsz) and flags into structures passed between
>>> @@ -455,6 +458,37 @@ struct vfio_iommu_spapr_tce_info {
>>>
>>> #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
>>>
>>> +/*
>>> + * EEH PE operation struct provides ways to:
>>> + * - enable/disable EEH functionality;
>>> + * - unfreeze IO/DMA for frozen PE;
>>> + * - read PE state;
>>> + * - reset PE;
>>> + * - configure PE.
>>> + */
>>> +struct vfio_eeh_pe_op {
>>> + __u32 argsz;
>>> + __u32 flags;
>>> + __u32 op;
>>> +};
>>> +
>>> +#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
>>> +#define VFIO_EEH_PE_ENABLE 1 /* Enable EEH functionality */
>>> +#define VFIO_EEH_PE_UNFREEZE_IO 2 /* Enable IO for frozen PE */
>>> +#define VFIO_EEH_PE_UNFREEZE_DMA 3 /* Enable DMA for frozen PE */
>>> +#define VFIO_EEH_PE_GET_STATE 4 /* PE state retrieval */
>>> +#define VFIO_EEH_PE_STATE_NORMAL 0 /* PE in functional state */
>>> +#define VFIO_EEH_PE_STATE_RESET 1 /* PE reset in progress */
>>> +#define VFIO_EEH_PE_STATE_STOPPED 2 /* Stopped DMA and IO */
>>> +#define VFIO_EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
>>> +#define VFIO_EEH_PE_STATE_UNAVAIL 5 /* State unavailable */
>>> +#define VFIO_EEH_PE_RESET_DEACTIVATE 5 /* Deassert PE reset */
>>> +#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
>>> +#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
>>> +#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
>>> +
>>> +#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
>>> +
>>> /* ***************************************************************** */
>>>
>>> #endif /* VFIO_H */
>>>
>>
>>
>> --
>> Alexey
>>
>
--
Alexey
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header
2014-07-16 1:32 ` Alexey Kardashevskiy
@ 2014-07-16 1:40 ` Gavin Shan
2014-07-28 12:50 ` Alexander Graf
0 siblings, 1 reply; 15+ messages in thread
From: Gavin Shan @ 2014-07-16 1:40 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: qemu-devel, agraf, Gavin Shan, alex.williamson, qemu-ppc
On Wed, Jul 16, 2014 at 11:32:13AM +1000, Alexey Kardashevskiy wrote:
>On 07/16/2014 11:16 AM, Gavin Shan wrote:
>> On Wed, Jul 16, 2014 at 11:09:44AM +1000, Alexey Kardashevskiy wrote:
>>> On 07/16/2014 10:20 AM, Gavin Shan wrote:
>>>> This updates kernel header (vfio.h) for EEH support on VFIO PCI
>>>> devices.
>>>
>>> Has this reached kernel upstream? The way linux headers update normally
>>> happens is you have to run scripts/update-linux-headers.sh against some
>>> linux kernel tag which you know that it won't change (like v3.16-rc5) and
>>> post all the changes as a single patch. It is never a header update for a
>>> specific feature, it is just an update.
>>>
>>
>> The kernel part isn't merged yet. I guess that's for 3.17 merge window.
>> Ok, good to know scripts/update-linux-headers.sh. So this patch should
>> be dropped and some one run the script to update QEMU (linux-headers
>> directory) ?
>
>
>Once your changes are in upstream kernel, you wait till kernel tree gets
>new "v3.xx-rcX" tag, then you run the script and make a separate patch for
>QEMU. Then you wait till it reaches QEMU upstream (because I do not know
>who will pull it to what tree, look at git history) or ppc-next (if Alex
>pulls it and you are basing your work on ppc-next) and then repost other
>patches.
>
Thanks for detailed explaining, Alexey. I guess I have to suspend a bit
until "v3.17.rc1" is coming out.
Thanks,
Gavin
>>>
>>>>
>>>> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
>>>> ---
>>>> linux-headers/linux/vfio.h | 34 ++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 34 insertions(+)
>>>>
>>>> diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
>>>> index 26c218e..95b591b 100644
>>>> --- a/linux-headers/linux/vfio.h
>>>> +++ b/linux-headers/linux/vfio.h
>>>> @@ -30,6 +30,9 @@
>>>> */
>>>> #define VFIO_DMA_CC_IOMMU 4
>>>>
>>>> +/* Check if EEH is supported */
>>>> +#define VFIO_EEH 5
>>>> +
>>>> /*
>>>> * The IOCTL interface is designed for extensibility by embedding the
>>>> * structure length (argsz) and flags into structures passed between
>>>> @@ -455,6 +458,37 @@ struct vfio_iommu_spapr_tce_info {
>>>>
>>>> #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
>>>>
>>>> +/*
>>>> + * EEH PE operation struct provides ways to:
>>>> + * - enable/disable EEH functionality;
>>>> + * - unfreeze IO/DMA for frozen PE;
>>>> + * - read PE state;
>>>> + * - reset PE;
>>>> + * - configure PE.
>>>> + */
>>>> +struct vfio_eeh_pe_op {
>>>> + __u32 argsz;
>>>> + __u32 flags;
>>>> + __u32 op;
>>>> +};
>>>> +
>>>> +#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
>>>> +#define VFIO_EEH_PE_ENABLE 1 /* Enable EEH functionality */
>>>> +#define VFIO_EEH_PE_UNFREEZE_IO 2 /* Enable IO for frozen PE */
>>>> +#define VFIO_EEH_PE_UNFREEZE_DMA 3 /* Enable DMA for frozen PE */
>>>> +#define VFIO_EEH_PE_GET_STATE 4 /* PE state retrieval */
>>>> +#define VFIO_EEH_PE_STATE_NORMAL 0 /* PE in functional state */
>>>> +#define VFIO_EEH_PE_STATE_RESET 1 /* PE reset in progress */
>>>> +#define VFIO_EEH_PE_STATE_STOPPED 2 /* Stopped DMA and IO */
>>>> +#define VFIO_EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
>>>> +#define VFIO_EEH_PE_STATE_UNAVAIL 5 /* State unavailable */
>>>> +#define VFIO_EEH_PE_RESET_DEACTIVATE 5 /* Deassert PE reset */
>>>> +#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
>>>> +#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
>>>> +#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
>>>> +
>>>> +#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
>>>> +
>>>> /* ***************************************************************** */
>>>>
>>>> #endif /* VFIO_H */
>>>>
>>>
>>>
>>> --
>>> Alexey
>>>
>>
>
>
>--
>Alexey
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public Gavin Shan
@ 2014-07-28 12:49 ` Alexander Graf
2014-07-28 13:52 ` Alexey Kardashevskiy
0 siblings, 1 reply; 15+ messages in thread
From: Alexander Graf @ 2014-07-28 12:49 UTC (permalink / raw)
To: Gavin Shan, qemu-ppc; +Cc: aik, alex.williamson, qemu-devel
On 16.07.14 02:20, Gavin Shan wrote:
> From: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> This makes find_phb()/find_dev() public and changed its names
> to spapr_pci_find_phb()/spapr_pci_find_dev() as they are going to
> be used from other parts of QEMU such as VFIO DDW (dynamic DMA window)
> or VFIO PCI error injection or VFIO EEH handling - in all these
> cases there are RTAS calls which are addressed to BUID+config_addr
> in IEEE1275 format.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Do we need this still?
Alex
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header
2014-07-16 1:40 ` Gavin Shan
@ 2014-07-28 12:50 ` Alexander Graf
0 siblings, 0 replies; 15+ messages in thread
From: Alexander Graf @ 2014-07-28 12:50 UTC (permalink / raw)
To: Gavin Shan, Alexey Kardashevskiy; +Cc: alex.williamson, qemu-ppc, qemu-devel
On 16.07.14 03:40, Gavin Shan wrote:
> On Wed, Jul 16, 2014 at 11:32:13AM +1000, Alexey Kardashevskiy wrote:
>> On 07/16/2014 11:16 AM, Gavin Shan wrote:
>>> On Wed, Jul 16, 2014 at 11:09:44AM +1000, Alexey Kardashevskiy wrote:
>>>> On 07/16/2014 10:20 AM, Gavin Shan wrote:
>>>>> This updates kernel header (vfio.h) for EEH support on VFIO PCI
>>>>> devices.
>>>> Has this reached kernel upstream? The way linux headers update normally
>>>> happens is you have to run scripts/update-linux-headers.sh against some
>>>> linux kernel tag which you know that it won't change (like v3.16-rc5) and
>>>> post all the changes as a single patch. It is never a header update for a
>>>> specific feature, it is just an update.
>>>>
>>> The kernel part isn't merged yet. I guess that's for 3.17 merge window.
>>> Ok, good to know scripts/update-linux-headers.sh. So this patch should
>>> be dropped and some one run the script to update QEMU (linux-headers
>>> directory) ?
>>
>> Once your changes are in upstream kernel, you wait till kernel tree gets
>> new "v3.xx-rcX" tag, then you run the script and make a separate patch for
>> QEMU. Then you wait till it reaches QEMU upstream (because I do not know
>> who will pull it to what tree, look at git history) or ppc-next (if Alex
>> pulls it and you are basing your work on ppc-next) and then repost other
>> patches.
>>
> Thanks for detailed explaining, Alexey. I guess I have to suspend a bit
> until "v3.17.rc1" is coming out.
It's also perfectly fine to keep the kernel header update inside your
patch set, but please make sure to mention which commit it is against.
If I pick it up, I will generate the headers myself though and drop your
patch while applying the rest of the set.
Alex
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public
2014-07-28 12:49 ` Alexander Graf
@ 2014-07-28 13:52 ` Alexey Kardashevskiy
0 siblings, 0 replies; 15+ messages in thread
From: Alexey Kardashevskiy @ 2014-07-28 13:52 UTC (permalink / raw)
To: Alexander Graf, Gavin Shan, qemu-ppc; +Cc: alex.williamson, qemu-devel
On 07/28/2014 10:49 PM, Alexander Graf wrote:
>
> On 16.07.14 02:20, Gavin Shan wrote:
>> From: Alexey Kardashevskiy <aik@ozlabs.ru>
>>
>> This makes find_phb()/find_dev() public and changed its names
>> to spapr_pci_find_phb()/spapr_pci_find_dev() as they are going to
>> be used from other parts of QEMU such as VFIO DDW (dynamic DMA window)
>> or VFIO PCI error injection or VFIO EEH handling - in all these
>> cases there are RTAS calls which are addressed to BUID+config_addr
>> in IEEE1275 format.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> Do we need this still?
Ufff. I missed when this patchet stopped needing this patch :)
Looks to me that this patchset does not need it so I'll repost it for DDW
later.
--
Alexey
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2014-07-28 13:53 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-16 0:20 [Qemu-devel] [PATCH v12 0/4] EEH Support for VFIO Devices Gavin Shan
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 1/4] spapr_pci: Make find_phb()/find_dev() public Gavin Shan
2014-07-28 12:49 ` Alexander Graf
2014-07-28 13:52 ` Alexey Kardashevskiy
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 2/4] sPAPR: Implement EEH RTAS calls Gavin Shan
2014-07-16 1:06 ` Alexey Kardashevskiy
2014-07-16 1:12 ` Gavin Shan
2014-07-16 1:28 ` Alexey Kardashevskiy
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 3/4] headers: Update kernel header Gavin Shan
2014-07-16 1:09 ` Alexey Kardashevskiy
2014-07-16 1:16 ` Gavin Shan
2014-07-16 1:32 ` Alexey Kardashevskiy
2014-07-16 1:40 ` Gavin Shan
2014-07-28 12:50 ` Alexander Graf
2014-07-16 0:20 ` [Qemu-devel] [PATCH v12 4/4] sPAPR: Implement sPAPRPHBClass::eeh_handler Gavin Shan
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