[PATCH 0/3] Add Altera peripheral memories to EDAC framework

[PATCH 0/3] Add Altera peripheral memories to EDAC framework

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.

Thor Thayer (3):
  arm: socfpga: Enable ECC of L2 and OCRAM on startup.
  edac: altera: Add Altera L2 Cache and OCRAM EDAC Support
  arm: dts: Add Altera L2 Cache and OCRAM EDAC

 .../bindings/arm/altera/socfpga-l2-edac.txt        |   15 ++
 .../bindings/arm/altera/socfpga-ocram-edac.txt     |   16 ++
 MAINTAINERS                                        |    7 +
 arch/arm/boot/dts/socfpga.dtsi                     |   20 +-
 arch/arm/configs/socfpga_defconfig                 |    1 +
 arch/arm/mach-socfpga/Makefile                     |    2 +
 arch/arm/mach-socfpga/l2_cache.c                   |   44 ++++
 arch/arm/mach-socfpga/l2_cache.h                   |   28 +++
 arch/arm/mach-socfpga/ocram.c                      |   84 +++++++
 arch/arm/mach-socfpga/ocram.h                      |   28 +++
 arch/arm/mach-socfpga/socfpga.c                    |   13 +-
 drivers/edac/Kconfig                               |   14 ++
 drivers/edac/Makefile                              |    4 +
 drivers/edac/altera_edac_mgr.c                     |  261 ++++++++++++++++++++
 drivers/edac/altera_edac_mgr.h                     |   56 +++++
 drivers/edac/altera_l2_edac.c                      |  130 ++++++++++
 drivers/edac/altera_ocram_edac.c                   |  107 ++++++++
 17 files changed, 828 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/l2_cache.h
 create mode 100644 arch/arm/mach-socfpga/ocram.c
 create mode 100644 arch/arm/mach-socfpga/ocram.h
 create mode 100644 drivers/edac/altera_edac_mgr.c
 create mode 100644 drivers/edac/altera_edac_mgr.h
 create mode 100644 drivers/edac/altera_l2_edac.c
 create mode 100644 drivers/edac/altera_ocram_edac.c

-- 
1.7.9.5

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[PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

This patch enables the ECC for L2 cache and OCRAM on machine
startup. In both cases, the ECC has to be enabled before data
is stored in memory otherwise the ECC will fail on reads.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 MAINTAINERS                        |    6 +++
 arch/arm/configs/socfpga_defconfig |    1 +
 arch/arm/mach-socfpga/Makefile     |    2 +
 arch/arm/mach-socfpga/l2_cache.c   |   44 +++++++++++++++++++
 arch/arm/mach-socfpga/l2_cache.h   |   28 ++++++++++++
 arch/arm/mach-socfpga/ocram.c      |   84 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-socfpga/ocram.h      |   28 ++++++++++++
 arch/arm/mach-socfpga/socfpga.c    |   13 +++++-
 8 files changed, 205 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/l2_cache.h
 create mode 100644 arch/arm/mach-socfpga/ocram.c
 create mode 100644 arch/arm/mach-socfpga/ocram.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5e7866a..9faf1d3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1381,6 +1381,12 @@ M:	Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
 S:	Maintained
 F:	drivers/clk/socfpga/
 
+ARM/SOCFPGA EDAC SUPPORT
+M:	Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
+S:	Maintained
+F:	arch/arm/mach-socfpga/l2_cache.*
+F:	arch/arm/mach-socfpga/ocram.*
+
 ARM/STI ARCHITECTURE
 M:	Srinivas Kandagatla <srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
 M:	Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index d7a5855..e757a33 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -123,3 +123,4 @@ CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC2_HOST=y
 CONFIG_USB_DWC2_PLATFORM=y
+CONFIG_SRAM=y
\ No newline at end of file
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6dd7a93..851a144 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,3 +4,5 @@
 
 obj-y					:= socfpga.o
 obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM) += ocram.o
+obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
new file mode 100644
index 0000000..8e109f3
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+
+#include "l2_cache.h"
+
+void socfpga_init_l2_ecc(void)
+{
+	struct device_node *np;
+	void __iomem  *mapped_l2_edac_addr;
+
+	np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
+	if (!np) {
+		pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
+		return;
+	}
+
+	mapped_l2_edac_addr = of_iomap(np, 0);
+	if (!mapped_l2_edac_addr) {
+		pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
+		return;
+	}
+
+	/* Enable ECC */
+	writel(0x01, mapped_l2_edac_addr);
+
+	pr_debug("SOCFPGA: Success Initializing L2 cache ECC\n");
+}
+
diff --git a/arch/arm/mach-socfpga/l2_cache.h b/arch/arm/mach-socfpga/l2_cache.h
new file mode 100644
index 0000000..58e140d
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MACH_SOCFPGA_L2_CACHE_H
+#define MACH_SOCFPGA_L2_CACHE_H
+
+#ifdef CONFIG_EDAC_ALTERA_L2C
+void socfpga_init_l2_ecc(void);
+#else
+inline void socfpga_init_l2_ecc(void)
+{
+}
+#endif
+
+#endif /* #ifndef MACH_SOCFPGA_L2_CACHE_H */
diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
new file mode 100644
index 0000000..26ec113
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/genalloc.h>
+#include <linux/of_platform.h>
+
+#include "ocram.h"
+
+void socfpga_init_ocram_ecc(void)
+{
+	struct device_node *np;
+	const __be32 *prop;
+	u32 ocr_edac_addr, iram_addr, len;
+	void __iomem  *mapped_ocr_edac_addr;
+	size_t size;
+	struct gen_pool *gp;
+
+	np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
+	if (!np) {
+		pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
+		return;
+	}
+
+	prop = of_get_property(np, "reg", &size);
+	ocr_edac_addr = be32_to_cpup(prop++);
+	len = be32_to_cpup(prop);
+	if (!prop || size < sizeof(*prop)) {
+		pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
+		return;
+	}
+
+	gp = of_get_named_gen_pool(np, "iram", 0);
+	if (!gp) {
+		pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
+		return;
+	}
+
+	np = of_find_compatible_node(NULL, NULL, "mmio-sram");
+	if (!np) {
+		pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
+		return;
+	}
+	/* Determine the OCRAM address and size */
+	prop = of_get_property(np, "reg", &size);
+	iram_addr = be32_to_cpup(prop++);
+	len = be32_to_cpup(prop);
+
+	if (!prop || size < sizeof(*prop)) {
+		pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
+		return;
+	}
+
+	iram_addr = gen_pool_alloc(gp, len);
+	if (iram_addr == 0) {
+		pr_err("SOCFPGA: cannot alloc from gen pool\n");
+		return;
+	}
+
+	memset((void *)iram_addr, 0, len);
+
+	mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
+
+	gen_pool_free(gp, iram_addr, len);
+
+	/* Clear any pending OCRAM ECC interrupts, then enable ECC */
+	writel(0x18, mapped_ocr_edac_addr);
+	writel(0x19, mapped_ocr_edac_addr);
+
+	pr_debug("SOCFPGA: Success Initializing OCRAM\n");
+}
+
diff --git a/arch/arm/mach-socfpga/ocram.h b/arch/arm/mach-socfpga/ocram.h
new file mode 100644
index 0000000..f93cf84
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MACH_SOCFPGA_OCRAM_H
+#define MACH_SOCFPGA_OCRAM_H
+
+#ifdef CONFIG_EDAC_ALTERA_OCRAM
+void socfpga_init_ocram_ecc(void);
+#else
+inline void socfpga_init_ocram_ecc(void)
+{
+}
+#endif
+
+#endif /* #ifndef MACH_SOCFPGA_OCRAM_H */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf383..fb41aca 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation
+ *  Copyright (C) 2012;2014 Altera Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +25,8 @@
 #include <asm/mach/map.h>
 
 #include "core.h"
+#include "l2_cache.h"
+#include "ocram.h"
 
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
@@ -83,6 +85,7 @@ static void __init socfpga_init_irq(void)
 {
 	irqchip_init();
 	socfpga_sysmgr_init();
+	socfpga_init_l2_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
@@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
+static void __init socfpga_cyclone5_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     NULL, NULL);
+	socfpga_init_ocram_ecc();
+}
+
 static const char *altera_dt_match[] = {
 	"altr,socfpga",
 	NULL
@@ -109,6 +119,7 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 	.smp		= smp_ops(socfpga_smp_ops),
 	.map_io		= socfpga_map_io,
 	.init_irq	= socfpga_init_irq,
+	.init_machine	= socfpga_cyclone5_init,
 	.restart	= socfpga_cyclone5_restart,
 	.dt_compat	= altera_dt_match,
 MACHINE_END
-- 
1.7.9.5

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[PATCH 2/3] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC_DEVICE framework. The EDAC
manager abstracts the common probe functionality and
test triggers. The L2 Cache and OCRAM files handle
the specific memory functions.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 .../bindings/arm/altera/socfpga-l2-edac.txt        |   15 ++
 .../bindings/arm/altera/socfpga-ocram-edac.txt     |   16 ++
 MAINTAINERS                                        |    1 +
 drivers/edac/Kconfig                               |   14 ++
 drivers/edac/Makefile                              |    4 +
 drivers/edac/altera_edac_mgr.c                     |  261 ++++++++++++++++++++
 drivers/edac/altera_edac_mgr.h                     |   56 +++++
 drivers/edac/altera_l2_edac.c                      |  130 ++++++++++
 drivers/edac/altera_ocram_edac.c                   |  107 ++++++++
 9 files changed, 604 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
 create mode 100644 drivers/edac/altera_edac_mgr.c
 create mode 100644 drivers/edac/altera_edac_mgr.h
 create mode 100644 drivers/edac/altera_l2_edac.c
 create mode 100644 drivers/edac/altera_ocram_edac.c

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
new file mode 100644
index 0000000..35b19e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
@@ -0,0 +1,15 @@
+Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
+
+Required Properties:
+- compatible : Should be "altr,l2-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt. Note the rising edge type.
+
+Example:
+
+	l2edac@ffd08140 {
+		compatible = "altr,l2-edac";
+		reg = <0xffd08140 0x4>;
+		interrupts = <0 36 1>, <0 37 1>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
new file mode 100644
index 0000000..31ab205
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
@@ -0,0 +1,16 @@
+Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
+
+OCRAM ECC Required Properties:
+- compatible : Should be "altr,ocram-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt. Note the rising edge type.
+
+Example:
+	ocramedac@ffd08144 {
+		compatible = "altr,ocram-edac";
+		reg = <0xffd08144 0x4>;
+		iram = <&ocram>;
+		interrupts = <0 178 1>, <0 179 1>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 9faf1d3..fe9e361 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1386,6 +1386,7 @@ M:	Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
 S:	Maintained
 F:	arch/arm/mach-socfpga/l2_cache.*
 F:	arch/arm/mach-socfpga/ocram.*
+F:	drivers/edac/altera_*
 
 ARM/STI ARCHITECTURE
 M:	Srinivas Kandagatla <srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fd89ca9..77f691b 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -376,4 +376,18 @@ config EDAC_OCTEON_PCI
 	  Support for error detection and correction on the
 	  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_L2C
+	bool "Altera L2 Cache EDAC"
+	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && CACHE_L2X0
+	help
+	  Support for error detection and correction on the
+	  Altera L2 cache Memory for Altera SoCs.
+
+config EDAC_ALTERA_OCRAM
+	bool "Altera On-Chip RAM EDAC"
+	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && SRAM && GENERIC_ALLOCATOR
+	help
+	  Support for error detection and correction on the
+	  Altera On-Chip RAM Memory for Altera SoCs.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index c479a24..7618a35 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -65,3 +65,7 @@ obj-$(CONFIG_EDAC_OCTEON_PC)		+= octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)		+= octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)		+= octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)		+= octeon_edac-pci.o
+
+alt_edac_mgr-y				:= altera_edac_mgr.o
+obj-$(CONFIG_EDAC_ALTERA_L2C)		+= alt_edac_mgr.o altera_l2_edac.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM)		+= alt_edac_mgr.o altera_ocram_edac.o
diff --git a/drivers/edac/altera_edac_mgr.c b/drivers/edac/altera_edac_mgr.c
new file mode 100644
index 0000000..676ccbe
--- /dev/null
+++ b/drivers/edac/altera_edac_mgr.c
@@ -0,0 +1,261 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Adapted from the highbank_l2_edac driver
+ */
+
+#include <linux/ctype.h>
+#include <linux/edac.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include "altera_edac_mgr.h"
+#include "edac_core.h"
+#include "edac_module.h"
+
+static irqreturn_t altr_edac_mgr_handler(int irq, void *dev_id)
+{
+	struct edac_device_ctl_info *dci = dev_id;
+	struct altr_edac_mgr_dev *drvdata = dci->pvt_info;
+	const struct ecc_mgr_prv_data *priv = drvdata->data;
+
+	if (irq == drvdata->sb_irq) {
+		if (priv->ce_clear_mask)
+			writel(priv->ce_clear_mask, drvdata->base);
+		edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
+	}
+	if (irq == drvdata->db_irq) {
+		if (priv->ue_clear_mask)
+			writel(priv->ue_clear_mask, drvdata->base);
+		edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
+		panic("\nEDAC:ECC_MGR[Uncorrectable errors]\n");
+	}
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_EDAC_DEBUG
+ssize_t altr_edac_mgr_trig(struct edac_device_ctl_info *edac_dci,
+			   const char *buffer, size_t count)
+{
+	u32 *ptemp, i, error_mask;
+	int result = 0;
+	unsigned long flags;
+	struct altr_edac_mgr_dev *drvdata = edac_dci->pvt_info;
+	const struct ecc_mgr_prv_data *priv = drvdata->data;
+	void *generic_ptr = edac_dci->dev;
+
+	if (!priv->alloc_mem)
+		return -ENOMEM;
+
+	/* Note that generic_ptr is initialized to the device * but in
+	 * some init_functions, this is overridden and returns data    */
+	ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
+	if (!ptemp) {
+		edac_printk(KERN_ERR, EDAC_MGR,
+			    "Inject: Buffer Allocation error\n");
+		return -ENOMEM;
+	}
+
+	if (count == 3)
+		error_mask = priv->ue_set_mask;
+	else
+		error_mask = priv->ce_set_mask;
+
+	edac_printk(KERN_ALERT, EDAC_MGR,
+		    "Trigger Error Mask (0x%X)\n", error_mask);
+
+	local_irq_save(flags);
+	/* write ECC corrupted data out. */
+	for (i = 0; i < (priv->trig_alloc_sz/sizeof(*ptemp)); i++) {
+		/* Read data so we're in the correct state */
+		rmb();
+		if (ACCESS_ONCE(ptemp[i]))
+			result = -1;
+		/* Toggle Error bit (it is latched), leave ECC enabled */
+		writel(error_mask, drvdata->base);
+		writel(priv->ecc_enable_mask, drvdata->base);
+		ptemp[i] = i;
+	}
+	/* Ensure it has been written out */
+	wmb();
+	local_irq_restore(flags);
+
+	if (result)
+		edac_printk(KERN_ERR, EDAC_MGR, "Mem Not Cleared\n");
+
+	/* Read out written data. ECC error caused here */
+	for (i = 0; i < 16; i++)
+		if (ACCESS_ONCE(ptemp[i]) != i)
+			edac_printk(KERN_ERR, EDAC_MGR, "Mem Doesn't match\n");
+
+	if (priv->free_mem)
+		priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
+
+	return count;
+}
+
+static void altr_set_sysfs_attr(struct edac_device_ctl_info *edac_dci,
+				const struct ecc_mgr_prv_data *priv)
+{
+	struct edac_dev_sysfs_attribute *ecc_attr = priv->eccmgr_sysfs_attr;
+
+	if (ecc_attr) {
+		edac_dci->sysfs_attributes =  ecc_attr;
+		edac_printk(KERN_ERR, EDAC_MGR, "Set SysFS trigger\n");
+	}
+}
+#else
+static void altr_set_sysfs_attr(struct edac_device_ctl_info *edac_dci,
+				const struct ecc_mgr_prv_data *priv)
+{}
+#endif	/* #ifdef CONFIG_EDAC_DEBUG */
+
+static const struct of_device_id altr_edac_mgr_of_match[] = {
+#ifdef CONFIG_EDAC_ALTERA_L2C
+	{ .compatible = "altr,l2-edac", .data = (void *)&l2ecc_data },
+#endif
+#ifdef CONFIG_EDAC_ALTERA_OCRAM
+	{ .compatible = "altr,ocram-edac", .data = (void *)&ocramecc_data },
+#endif
+	{},
+};
+MODULE_DEVICE_TABLE(of, altr_edac_mgr_of_match);
+
+/*
+ * altr_edac_mgr_probe()
+ *	This is a generic EDAC device driver that will support
+ *	various Altera memory devices such as the L2 cache ECC and
+ *	OCRAM ECC as well as the memories for other peripherals.
+ *	Module specific initialization is done by passing the
+ *	function index in the device tree.
+ */
+static int altr_edac_mgr_probe(struct platform_device *pdev)
+{
+	struct edac_device_ctl_info *dci;
+	struct altr_edac_mgr_dev *drvdata;
+	struct resource *r;
+	int res = 0;
+	struct device_node *np = pdev->dev.of_node;
+	char *ecc_name = (char *)np->name;
+	static int dev_instance;
+
+	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
+		return -ENOMEM;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		edac_printk(KERN_ERR, EDAC_MGR,
+			    "Unable to get mem resource\n");
+		return -ENODEV;
+	}
+
+	if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
+				     dev_name(&pdev->dev))) {
+		edac_printk(KERN_ERR, EDAC_MGR,
+			    "%s:Error requesting mem region\n", ecc_name);
+		return -EBUSY;
+	}
+
+	dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
+					 1, ecc_name, 1, 0, NULL, 0,
+					 dev_instance++);
+
+	if (!dci)
+		return -ENOMEM;
+
+	drvdata = dci->pvt_info;
+	dci->dev = &pdev->dev;
+	platform_set_drvdata(pdev, dci);
+	drvdata->edac_dev_name = ecc_name;
+
+	drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+	if (!drvdata->base) {
+		edac_printk(KERN_ERR, EDAC_MGR,
+			    "%s:Unable to map regs\n", ecc_name);
+		return -ENOMEM;
+	}
+
+	/* Get driver specific data for this EDAC device */
+	drvdata->data = of_match_node(altr_edac_mgr_of_match, np)->data;
+
+	/* Check specific dependencies for the module */
+	if (drvdata->data->setup) {
+		res = drvdata->data->setup(pdev, drvdata->base);
+		if (res < 0)
+			goto err;
+	}
+
+	drvdata->sb_irq = platform_get_irq(pdev, 0);
+	res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
+			       altr_edac_mgr_handler,
+			       0, dev_name(&pdev->dev), dci);
+	if (res < 0)
+		goto err;
+
+	drvdata->db_irq = platform_get_irq(pdev, 1);
+	res = devm_request_irq(&pdev->dev, drvdata->db_irq,
+			       altr_edac_mgr_handler,
+			       0, dev_name(&pdev->dev), dci);
+	if (res < 0)
+		goto err;
+
+	dci->mod_name = "ECC_MGR";
+	dci->dev_name = drvdata->edac_dev_name;
+
+	altr_set_sysfs_attr(dci, drvdata->data);
+
+	if (edac_device_add_device(dci))
+		goto err;
+
+	devres_close_group(&pdev->dev, NULL);
+
+	return 0;
+err:
+	devres_release_group(&pdev->dev, NULL);
+	edac_device_free_ctl_info(dci);
+
+	return res;
+}
+
+static int altr_edac_mgr_remove(struct platform_device *pdev)
+{
+	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
+
+	edac_device_del_device(&pdev->dev);
+	edac_device_free_ctl_info(dci);
+
+	return 0;
+}
+
+static struct platform_driver altr_edac_mgr_driver = {
+	.probe =  altr_edac_mgr_probe,
+	.remove = altr_edac_mgr_remove,
+	.driver = {
+		.name = "altr_edac_mgr",
+		.of_match_table = altr_edac_mgr_of_match,
+	},
+};
+module_platform_driver(altr_edac_mgr_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer");
+MODULE_DESCRIPTION("EDAC Driver for Altera SoC ECC Manager");
diff --git a/drivers/edac/altera_edac_mgr.h b/drivers/edac/altera_edac_mgr.h
new file mode 100644
index 0000000..791037c
--- /dev/null
+++ b/drivers/edac/altera_edac_mgr.h
@@ -0,0 +1,56 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ALTERA_EDAC_MGR_H
+#define ALTERA_EDAC_MGR_H
+
+#include <linux/edac.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include "edac_core.h"
+
+#define EDAC_MGR "MGR"
+
+struct ecc_mgr_prv_data {
+	int (*setup)(struct platform_device *pdev, void __iomem *base);
+	int ce_clear_mask;
+	int ue_clear_mask;
+#ifdef CONFIG_EDAC_DEBUG
+	struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
+	void * (*alloc_mem)(size_t size, void **other);
+	void (*free_mem)(void *p, size_t size, void *other);
+	int ecc_enable_mask;
+	int ce_set_mask;
+	int ue_set_mask;
+	int trig_alloc_sz;
+#endif
+};
+
+struct altr_edac_mgr_dev {
+	void __iomem *base;
+	int sb_irq;
+	int db_irq;
+	const struct ecc_mgr_prv_data *data;
+	char *edac_dev_name;
+};
+
+extern const struct ecc_mgr_prv_data l2ecc_data;
+extern const struct ecc_mgr_prv_data ocramecc_data;
+
+ssize_t altr_edac_mgr_trig(struct edac_device_ctl_info *edac_dci,
+			   const char *buffer, size_t count);
+
+#endif	/* #ifndef ALTERA_EDAC_MGR_H */
diff --git a/drivers/edac/altera_l2_edac.c b/drivers/edac/altera_l2_edac.c
new file mode 100644
index 0000000..d3f5d4c
--- /dev/null
+++ b/drivers/edac/altera_l2_edac.c
@@ -0,0 +1,130 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/edac.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include "altera_edac_mgr.h"
+#include "edac_module.h"
+
+/* MPU L2 Register Defines */
+#define ALTR_MPUL2_CONTROL_OFFSET       0x100
+#define ALTR_MPUL2_CTL_CACHE_EN_MASK    0x00000001
+
+/* L2 ECC Management Group Defines */
+#define ALTR_MAN_GRP_L2_ECC_OFFSET      0x00
+#define ALTR_L2_ECC_EN_MASK             0x00000001
+#define ALTR_L2_ECC_INJS_MASK           0x00000002
+#define ALTR_L2_ECC_INJD_MASK           0x00000004
+
+#ifdef CONFIG_EDAC_DEBUG
+static void *l2_alloc_mem(size_t size, void **other)
+{
+	struct device *dev = *other;
+	void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
+
+	if (!ptemp)
+		return NULL;
+
+	/* Make sure everything is written out */
+	wmb();
+	flush_cache_all();
+
+	return ptemp;
+}
+
+static void l2_free_mem(void *p, size_t size, void *other)
+{
+	struct device *dev = other;
+
+	if (dev && p)
+		devm_kfree(dev, p);
+}
+
+static struct edac_dev_sysfs_attribute altr_l2_sysfs_attributes[] = {
+	{
+		.attr = { .name = "altr_l2_trigger",
+			  .mode = (S_IRUGO | S_IWUSR) },
+		.show = NULL,
+		.store = altr_edac_mgr_trig
+	},
+	{
+		.attr = {.name = NULL }
+	}
+};
+#endif	/* #ifdef CONFIG_EDAC_DEBUG */
+
+/*
+ * altr_l2_dependencies()
+ *	Test for L2 cache ECC dependencies upon entry because
+ *	the preloader/UBoot should have initialized the L2
+ *	memory and enabled the ECC.
+ *	Can't turn on ECC here because accessing un-initialized
+ *	memory will cause CE/UE errors possibly causing an ABORT.
+ *	Bail if ECC is not on.
+ *	Test For 1) L2 ECC is enabled and 2) L2 Cache is enabled.
+ */
+static int altr_l2_dependencies(struct platform_device *pdev,
+				void __iomem *base)
+{
+	u32 control;
+	struct regmap *l2_vbase;
+
+	control = readl(base) & ALTR_L2_ECC_EN_MASK;
+	if (!control) {
+		dev_err(&pdev->dev, "L2: No ECC present, or ECC disabled\n");
+		return -ENODEV;
+	}
+
+	l2_vbase = syscon_regmap_lookup_by_compatible("arm,pl310-cache");
+	if (IS_ERR(l2_vbase)) {
+		dev_err(&pdev->dev,
+			"L2 ECC:regmap for arm,pl310-cache lookup failed.\n");
+		return -ENODEV;
+	}
+
+	regmap_read(l2_vbase, ALTR_MPUL2_CONTROL_OFFSET, &control);
+	if (!(control & ALTR_MPUL2_CTL_CACHE_EN_MASK)) {
+		dev_err(&pdev->dev, "L2: Cache disabled\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+const struct ecc_mgr_prv_data l2ecc_data = {
+	.setup = altr_l2_dependencies,
+	.ce_clear_mask = 0,
+	.ue_clear_mask = 0,
+#ifdef CONFIG_EDAC_DEBUG
+	.eccmgr_sysfs_attr = altr_l2_sysfs_attributes,
+	.alloc_mem = l2_alloc_mem,
+	.free_mem = l2_free_mem,
+	.ecc_enable_mask = ALTR_L2_ECC_EN_MASK,
+	.ce_set_mask = (ALTR_L2_ECC_EN_MASK | ALTR_L2_ECC_INJS_MASK),
+	.ue_set_mask = (ALTR_L2_ECC_EN_MASK | ALTR_L2_ECC_INJD_MASK),
+	.trig_alloc_sz = 4 * 1024,
+#endif
+};
+
diff --git a/drivers/edac/altera_ocram_edac.c b/drivers/edac/altera_ocram_edac.c
new file mode 100644
index 0000000..799b22b
--- /dev/null
+++ b/drivers/edac/altera_ocram_edac.c
@@ -0,0 +1,107 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/ctype.h>
+#include <linux/edac.h>
+#include <linux/genalloc.h>
+#include <linux/of.h>
+#include "altera_edac_mgr.h"
+
+/* OCRAM ECC Management Group Defines */
+#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
+#define ALTR_OCR_ECC_EN_MASK            0x00000001
+#define ALTR_OCR_ECC_INJS_MASK          0x00000002
+#define ALTR_OCR_ECC_INJD_MASK          0x00000004
+#define ALTR_OCR_ECC_SERR_MASK          0x00000008
+#define ALTR_OCR_ECC_DERR_MASK          0x00000010
+
+#ifdef CONFIG_EDAC_DEBUG
+static void *ocram_alloc_mem(size_t size, void **other)
+{
+	struct device_node *np;
+	struct gen_pool *gp;
+	void *sram_addr;
+
+	np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
+	if (!np)
+		return NULL;
+
+	gp = of_get_named_gen_pool(np, "iram", 0);
+	if (!gp)
+		return NULL;
+	*other = gp;
+
+	sram_addr = (void *)gen_pool_alloc(gp, size);
+	if (!sram_addr)
+		return NULL;
+
+	memset(sram_addr, 0, size);
+	wmb();	/* Ensure data is written out */
+
+	return sram_addr;
+}
+
+static void ocram_free_mem(void *p, size_t size, void *other)
+{
+	gen_pool_free((struct gen_pool *)other, (u32)p, size);
+}
+
+static struct edac_dev_sysfs_attribute altr_ocr_sysfs_attributes[] = {
+	{
+		.attr = { .name = "altr_ocram_trigger",
+			  .mode = (S_IRUGO | S_IWUSR) },
+		.show = NULL,
+		.store = altr_edac_mgr_trig
+	},
+	{
+		.attr = {.name = NULL }
+	}
+};
+#endif	/* #ifdef CONFIG_EDAC_DEBUG */
+
+/*
+ * altr_ocram_dependencies()
+ *	Test for OCRAM cache ECC dependencies upon entry because
+ *	ECC must be enabled.
+ */
+static int altr_ocram_dependencies(struct platform_device *pdev,
+				   void __iomem *base)
+{
+	u32 control;
+
+	control = readl(base) & ALTR_OCR_ECC_EN_MASK;
+	if (!control) {
+		dev_err(&pdev->dev, "OCRAM: No ECC present, or ECC disabled.\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+const struct ecc_mgr_prv_data ocramecc_data = {
+	.setup = altr_ocram_dependencies,
+	.ce_clear_mask = (ALTR_OCR_ECC_EN_MASK | ALTR_OCR_ECC_SERR_MASK),
+	.ue_clear_mask = (ALTR_OCR_ECC_EN_MASK | ALTR_OCR_ECC_DERR_MASK),
+#ifdef CONFIG_EDAC_DEBUG
+	.eccmgr_sysfs_attr = altr_ocr_sysfs_attributes,
+	.alloc_mem = ocram_alloc_mem,
+	.free_mem = ocram_free_mem,
+	.ecc_enable_mask = ALTR_OCR_ECC_EN_MASK,
+	.ce_set_mask = (ALTR_OCR_ECC_EN_MASK | ALTR_OCR_ECC_INJS_MASK),
+	.ue_set_mask = (ALTR_OCR_ECC_EN_MASK | ALTR_OCR_ECC_INJD_MASK),
+	.trig_alloc_sz = (32 * sizeof(u32)),
+#endif
+};
-- 
1.7.9.5

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[PATCH 3/3] arm: dts: Add Altera L2 Cache and OCRAM EDAC

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Adding the device tree entries needed to support the Altera L2
cache and OCRAM EDAC.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 arch/arm/boot/dts/socfpga.dtsi |   20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4d77ad6..f186957 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -608,7 +608,7 @@
 		};
 
 		L2: l2-cache@fffef000 {
-			compatible = "arm,pl310-cache";
+			compatible = "arm,pl310-cache", "syscon";
 			reg = <0xfffef000 0x1000>;
 			interrupts = <0 38 0x04>;
 			cache-unified;
@@ -628,6 +628,24 @@
 			clock-names = "biu", "ciu";
 		};
 
+		ocram: sram@ffff0000 {
+			compatible = "mmio-sram";
+			reg = <0xffff0000 0x10000>;
+		};
+
+		l2edac@xffd08140 {
+			compatible = "altr,l2-edac";
+			reg = <0xffd08140 0x4>;
+			interrupts = <0 36 1>, <0 37 1>;
+		};
+
+		ocramedac@ffd08144 {
+			compatible = "altr,ocram-edac";
+			reg = <0xffd08144 0x4>;
+			iram = <&ocram>;
+			interrupts = <0 178 1>, <0 179 1>;
+		};
+
 		/* Local timer */
 		timer@fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
-- 
1.7.9.5

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Re: [PATCH 3/3] arm: dts: Add Altera L2 Cache and OCRAM EDAC

[Dinh Nguyen]

On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Adding the device tree entries needed to support the Altera L2
> cache and OCRAM EDAC.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
>  arch/arm/boot/dts/socfpga.dtsi |   20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 4d77ad6..f186957 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -608,7 +608,7 @@
>  		};
>  
>  		L2: l2-cache@fffef000 {
> -			compatible = "arm,pl310-cache";
> +			compatible = "arm,pl310-cache", "syscon";
>  			reg = <0xfffef000 0x1000>;
>  			interrupts = <0 38 0x04>;
>  			cache-unified;
> @@ -628,6 +628,24 @@
>  			clock-names = "biu", "ciu";
>  		};
>  
> +		ocram: sram@ffff0000 {
> +			compatible = "mmio-sram";
> +			reg = <0xffff0000 0x10000>;
> +		};
> +

I sent a patch to add the OCRAM node:
http://www.spinics.net/lists/devicetree/msg51117.html

> +		l2edac@xffd08140 {
Remove the 'x'.
> +			compatible = "altr,l2-edac";
> +			reg = <0xffd08140 0x4>;
> +			interrupts = <0 36 1>, <0 37 1>;
> +		};
> +
> +		ocramedac@ffd08144 {
> +			compatible = "altr,ocram-edac";
> +			reg = <0xffd08144 0x4>;
> +			iram = <&ocram>;
> +			interrupts = <0 178 1>, <0 179 1>;
> +		};
> +
>  		/* Local timer */
>  		timer@fffec600 {
>  			compatible = "arm,cortex-a9-twd-timer";
> 

The documentation for these bindings should be included with this patch.

Dinh
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Re: [PATCH 2/3] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[Mark Rutland]

On Wed, Oct 01, 2014 at 05:31:31PM +0100, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Adding L2 Cache and On-Chip RAM EDAC support for the
> Altera SoCs using the EDAC_DEVICE framework. The EDAC
> manager abstracts the common probe functionality and
> test triggers. The L2 Cache and OCRAM files handle
> the specific memory functions.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
>  .../bindings/arm/altera/socfpga-l2-edac.txt        |   15 ++
>  .../bindings/arm/altera/socfpga-ocram-edac.txt     |   16 ++
>  MAINTAINERS                                        |    1 +
>  drivers/edac/Kconfig                               |   14 ++
>  drivers/edac/Makefile                              |    4 +
>  drivers/edac/altera_edac_mgr.c                     |  261 ++++++++++++++++++++
>  drivers/edac/altera_edac_mgr.h                     |   56 +++++
>  drivers/edac/altera_l2_edac.c                      |  130 ++++++++++
>  drivers/edac/altera_ocram_edac.c                   |  107 ++++++++
>  9 files changed, 604 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
>  create mode 100644 drivers/edac/altera_edac_mgr.c
>  create mode 100644 drivers/edac/altera_edac_mgr.h
>  create mode 100644 drivers/edac/altera_l2_edac.c
>  create mode 100644 drivers/edac/altera_ocram_edac.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
> new file mode 100644
> index 0000000..35b19e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
> @@ -0,0 +1,15 @@
> +Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
> +
> +Required Properties:
> +- compatible : Should be "altr,l2-edac"

That string looks too generic.

Given the EDAC seems to be a portion of the L2, is there not already an
L2 binding?

Just because Linux expects two drivers doesn't mean we should partition
the HW description this way.

> +- reg : Address and size for ECC error interrupt clear registers.
> +- interrupts : Should be single bit error interrupt, then double bit error
> +       interrupt. Note the rising edge type.
> +
> +Example:
> +
> +       l2edac@ffd08140 {
> +               compatible = "altr,l2-edac";
> +               reg = <0xffd08140 0x4>;
> +               interrupts = <0 36 1>, <0 37 1>;
> +       };
> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
> new file mode 100644
> index 0000000..31ab205
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
> @@ -0,0 +1,16 @@
> +Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
> +
> +OCRAM ECC Required Properties:
> +- compatible : Should be "altr,ocram-edac"
> +- reg : Address and size for ECC error interrupt clear registers.
> +- iram : phandle to On-Chip RAM definition.

Why not just describe this in the OCRAM node? Surely the register is
within the OCRAM controller?

Mark.
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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Dinh Nguyen]

On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> This patch enables the ECC for L2 cache and OCRAM on machine
> startup. In both cases, the ECC has to be enabled before data
> is stored in memory otherwise the ECC will fail on reads.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
>  MAINTAINERS                        |    6 +++
>  arch/arm/configs/socfpga_defconfig |    1 +
>  arch/arm/mach-socfpga/Makefile     |    2 +
>  arch/arm/mach-socfpga/l2_cache.c   |   44 +++++++++++++++++++
>  arch/arm/mach-socfpga/l2_cache.h   |   28 ++++++++++++
>  arch/arm/mach-socfpga/ocram.c      |   84 ++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-socfpga/ocram.h      |   28 ++++++++++++
>  arch/arm/mach-socfpga/socfpga.c    |   13 +++++-
>  8 files changed, 205 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-socfpga/l2_cache.c
>  create mode 100644 arch/arm/mach-socfpga/l2_cache.h
>  create mode 100644 arch/arm/mach-socfpga/ocram.c
>  create mode 100644 arch/arm/mach-socfpga/ocram.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5e7866a..9faf1d3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1381,6 +1381,12 @@ M:	Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
>  S:	Maintained
>  F:	drivers/clk/socfpga/
>  
> +ARM/SOCFPGA EDAC SUPPORT
> +M:	Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> +S:	Maintained
> +F:	arch/arm/mach-socfpga/l2_cache.*
> +F:	arch/arm/mach-socfpga/ocram.*
> +
>  ARM/STI ARCHITECTURE
>  M:	Srinivas Kandagatla <srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>  M:	Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
> diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
> index d7a5855..e757a33 100644
> --- a/arch/arm/configs/socfpga_defconfig
> +++ b/arch/arm/configs/socfpga_defconfig
> @@ -123,3 +123,4 @@ CONFIG_USB=y
>  CONFIG_USB_DWC2=y
>  CONFIG_USB_DWC2_HOST=y
>  CONFIG_USB_DWC2_PLATFORM=y
> +CONFIG_SRAM=y
> \ No newline at end of file
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 6dd7a93..851a144 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -4,3 +4,5 @@
>  
>  obj-y					:= socfpga.o
>  obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o
> +obj-$(CONFIG_EDAC_ALTERA_OCRAM) += ocram.o
> +obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
> diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
> new file mode 100644
> index 0000000..8e109f3
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/l2_cache.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +
> +#include "l2_cache.h"
> +
> +void socfpga_init_l2_ecc(void)
> +{
> +	struct device_node *np;
> +	void __iomem  *mapped_l2_edac_addr;
> +
> +	np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
> +	if (!np) {
> +		pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
> +		return;
> +	}
> +
> +	mapped_l2_edac_addr = of_iomap(np, 0);
> +	if (!mapped_l2_edac_addr) {
> +		pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
> +		return;
> +	}
> +
> +	/* Enable ECC */
> +	writel(0x01, mapped_l2_edac_addr);
> +
> +	pr_debug("SOCFPGA: Success Initializing L2 cache ECC\n");
> +}
> +
> diff --git a/arch/arm/mach-socfpga/l2_cache.h b/arch/arm/mach-socfpga/l2_cache.h
> new file mode 100644
> index 0000000..58e140d
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/l2_cache.h
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef MACH_SOCFPGA_L2_CACHE_H
> +#define MACH_SOCFPGA_L2_CACHE_H
> +
> +#ifdef CONFIG_EDAC_ALTERA_L2C
> +void socfpga_init_l2_ecc(void);
> +#else
> +inline void socfpga_init_l2_ecc(void)
> +{
> +}
> +#endif
> +
> +#endif /* #ifndef MACH_SOCFPGA_L2_CACHE_H */
> diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
> new file mode 100644
> index 0000000..26ec113
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/ocram.c
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/genalloc.h>
> +#include <linux/of_platform.h>
> +
> +#include "ocram.h"
> +
> +void socfpga_init_ocram_ecc(void)
> +{
> +	struct device_node *np;
> +	const __be32 *prop;
> +	u32 ocr_edac_addr, iram_addr, len;
> +	void __iomem  *mapped_ocr_edac_addr;
> +	size_t size;
> +	struct gen_pool *gp;
> +
> +	np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
> +	if (!np) {
> +		pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
> +		return;
> +	}
> +
> +	prop = of_get_property(np, "reg", &size);
> +	ocr_edac_addr = be32_to_cpup(prop++);
> +	len = be32_to_cpup(prop);
> +	if (!prop || size < sizeof(*prop)) {
> +		pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
> +		return;
> +	}
> +
> +	gp = of_get_named_gen_pool(np, "iram", 0);
> +	if (!gp) {
> +		pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
> +		return;
> +	}
> +
> +	np = of_find_compatible_node(NULL, NULL, "mmio-sram");
> +	if (!np) {
> +		pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
> +		return;
> +	}
> +	/* Determine the OCRAM address and size */
> +	prop = of_get_property(np, "reg", &size);
> +	iram_addr = be32_to_cpup(prop++);
> +	len = be32_to_cpup(prop);
> +
> +	if (!prop || size < sizeof(*prop)) {
> +		pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
> +		return;
> +	}
> +
> +	iram_addr = gen_pool_alloc(gp, len);
> +	if (iram_addr == 0) {
> +		pr_err("SOCFPGA: cannot alloc from gen pool\n");
> +		return;
> +	}
> +
> +	memset((void *)iram_addr, 0, len);
> +
> +	mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
> +
> +	gen_pool_free(gp, iram_addr, len);
> +
> +	/* Clear any pending OCRAM ECC interrupts, then enable ECC */
> +	writel(0x18, mapped_ocr_edac_addr);
> +	writel(0x19, mapped_ocr_edac_addr);
> +
> +	pr_debug("SOCFPGA: Success Initializing OCRAM\n");
> +}
> +
> diff --git a/arch/arm/mach-socfpga/ocram.h b/arch/arm/mach-socfpga/ocram.h
> new file mode 100644
> index 0000000..f93cf84
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/ocram.h
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef MACH_SOCFPGA_OCRAM_H
> +#define MACH_SOCFPGA_OCRAM_H
> +
> +#ifdef CONFIG_EDAC_ALTERA_OCRAM
> +void socfpga_init_ocram_ecc(void);
> +#else
> +inline void socfpga_init_ocram_ecc(void)
> +{
> +}
> +#endif
> +
> +#endif /* #ifndef MACH_SOCFPGA_OCRAM_H */
> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
> index adbf383..fb41aca 100644
> --- a/arch/arm/mach-socfpga/socfpga.c
> +++ b/arch/arm/mach-socfpga/socfpga.c
> @@ -1,5 +1,5 @@
>  /*
> - *  Copyright (C) 2012 Altera Corporation
> + *  Copyright (C) 2012;2014 Altera Corporation
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> @@ -25,6 +25,8 @@
>  #include <asm/mach/map.h>
>  
>  #include "core.h"
> +#include "l2_cache.h"
> +#include "ocram.h"
>  
>  void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
>  void __iomem *sys_manager_base_addr;
> @@ -83,6 +85,7 @@ static void __init socfpga_init_irq(void)
>  {
>  	irqchip_init();
>  	socfpga_sysmgr_init();
> +	socfpga_init_l2_ecc();
>  }
>  
>  static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
>  	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>  }
>  
> +static void __init socfpga_cyclone5_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table,
> +			     NULL, NULL);

Why is this needed?

Dinh
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Re: [PATCH 3/3] arm: dts: Add Altera L2 Cache and OCRAM EDAC

[Thor Thayer]

On 10/01/2014 11:45 AM, Dinh Nguyen wrote:
>
> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>
>> Adding the device tree entries needed to support the Altera L2
>> cache and OCRAM EDAC.
>>
>> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>> ---
>>   arch/arm/boot/dts/socfpga.dtsi |   20 +++++++++++++++++++-
>>   1 file changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>> index 4d77ad6..f186957 100644
>> --- a/arch/arm/boot/dts/socfpga.dtsi
>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>> @@ -608,7 +608,7 @@
>>   		};
>>   
>>   		L2: l2-cache@fffef000 {
>> -			compatible = "arm,pl310-cache";
>> +			compatible = "arm,pl310-cache", "syscon";
>>   			reg = <0xfffef000 0x1000>;
>>   			interrupts = <0 38 0x04>;
>>   			cache-unified;
>> @@ -628,6 +628,24 @@
>>   			clock-names = "biu", "ciu";
>>   		};
>>   
>> +		ocram: sram@ffff0000 {
>> +			compatible = "mmio-sram";
>> +			reg = <0xffff0000 0x10000>;
>> +		};
>> +
> I sent a patch to add the OCRAM node:
> http://www.spinics.net/lists/devicetree/msg51117.html
>
OK. Thanks.
>> +		l2edac@xffd08140 {
> Remove the 'x'.
Thanks.
>> +			compatible = "altr,l2-edac";
>> +			reg = <0xffd08140 0x4>;
>> +			interrupts = <0 36 1>, <0 37 1>;
>> +		};
>> +
>> +		ocramedac@ffd08144 {
>> +			compatible = "altr,ocram-edac";
>> +			reg = <0xffd08144 0x4>;
>> +			iram = <&ocram>;
>> +			interrupts = <0 178 1>, <0 179 1>;
>> +		};
>> +
>>   		/* Local timer */
>>   		timer@fffec600 {
>>   			compatible = "arm,cortex-a9-twd-timer";
>>
> The documentation for these bindings should be included with this patch.
OK. Thanks.
>
> Dinh

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Re: [PATCH 2/3] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[Thor Thayer]

On 10/01/2014 11:53 AM, Mark Rutland wrote:
> On Wed, Oct 01, 2014 at 05:31:31PM +0100, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>
>> Adding L2 Cache and On-Chip RAM EDAC support for the
>> Altera SoCs using the EDAC_DEVICE framework. The EDAC
>> manager abstracts the common probe functionality and
>> test triggers. The L2 Cache and OCRAM files handle
>> the specific memory functions.
>>
>> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>> ---
>>   .../bindings/arm/altera/socfpga-l2-edac.txt        |   15 ++
>>   .../bindings/arm/altera/socfpga-ocram-edac.txt     |   16 ++
>>   MAINTAINERS                                        |    1 +
>>   drivers/edac/Kconfig                               |   14 ++
>>   drivers/edac/Makefile                              |    4 +
>>   drivers/edac/altera_edac_mgr.c                     |  261 ++++++++++++++++++++
>>   drivers/edac/altera_edac_mgr.h                     |   56 +++++
>>   drivers/edac/altera_l2_edac.c                      |  130 ++++++++++
>>   drivers/edac/altera_ocram_edac.c                   |  107 ++++++++
>>   9 files changed, 604 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
>>   create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
>>   create mode 100644 drivers/edac/altera_edac_mgr.c
>>   create mode 100644 drivers/edac/altera_edac_mgr.h
>>   create mode 100644 drivers/edac/altera_l2_edac.c
>>   create mode 100644 drivers/edac/altera_ocram_edac.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
>> new file mode 100644
>> index 0000000..35b19e3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
>> @@ -0,0 +1,15 @@
>> +Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
>> +
>> +Required Properties:
>> +- compatible : Should be "altr,l2-edac"
> That string looks too generic.
>
> Given the EDAC seems to be a portion of the L2, is there not already an
> L2 binding?
>
> Just because Linux expects two drivers doesn't mean we should partition
> the HW description this way.
Thank you for the quick feedback.
What should the string look like? I was trying to keep it short with the 
altr, prefix but I don't mind changing it to something better.
We're using the ARM PL310 L2 cache controller. The ECC is separate from 
the PL310 IP and is part of the System Manager. This is true of ECC for 
both the L2 and OCRAM.
I followed the Calxeda Highbank L2 EDAC implementation since ours is 
similar. The Calxeda Highbank implementation had a separate binding file 
and a device node under soc.

>> +- reg : Address and size for ECC error interrupt clear registers.
>> +- interrupts : Should be single bit error interrupt, then double bit error
>> +       interrupt. Note the rising edge type.
>> +
>> +Example:
>> +
>> +       l2edac@ffd08140 {
>> +               compatible = "altr,l2-edac";
>> +               reg = <0xffd08140 0x4>;
>> +               interrupts = <0 36 1>, <0 37 1>;
>> +       };
>> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
>> new file mode 100644
>> index 0000000..31ab205
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
>> @@ -0,0 +1,16 @@
>> +Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
>> +
>> +OCRAM ECC Required Properties:
>> +- compatible : Should be "altr,ocram-edac"
>> +- reg : Address and size for ECC error interrupt clear registers.
>> +- iram : phandle to On-Chip RAM definition.
> Why not just describe this in the OCRAM node? Surely the register is
> within the OCRAM controller?
The ECC registers not in the OCRAM controller but they are in the System 
Manager.  Maybe both the L2 cache and OCRAM ECC bindings should live 
there and the device tree node for System Manager would have OCRAM and 
L2 cache sub-nodes.

Thanks,

Thor
> Mark.

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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Thor Thayer]

On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>
> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>
>> This patch enables the ECC for L2 cache and OCRAM on machine
>> startup. In both cases, the ECC has to be enabled before data
>> is stored in memory otherwise the ECC will fail on reads.
>>
>> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>> ---
>>   MAINTAINERS                        |    6 +++
>>   arch/arm/configs/socfpga_defconfig |    1 +
>>   arch/arm/mach-socfpga/Makefile     |    2 +
>>   arch/arm/mach-socfpga/l2_cache.c   |   44 +++++++++++++++++++
>>   arch/arm/mach-socfpga/l2_cache.h   |   28 ++++++++++++
>>   arch/arm/mach-socfpga/ocram.c      |   84 ++++++++++++++++++++++++++++++++++++
>>   arch/arm/mach-socfpga/ocram.h      |   28 ++++++++++++
>>   arch/arm/mach-socfpga/socfpga.c    |   13 +++++-
>>   8 files changed, 205 insertions(+), 1 deletion(-)
>>   create mode 100644 arch/arm/mach-socfpga/l2_cache.c
>>   create mode 100644 arch/arm/mach-socfpga/l2_cache.h
>>   create mode 100644 arch/arm/mach-socfpga/ocram.c
>>   create mode 100644 arch/arm/mach-socfpga/ocram.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 5e7866a..9faf1d3 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1381,6 +1381,12 @@ M:	Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
>>   S:	Maintained
>>   F:	drivers/clk/socfpga/
>>   
>> +ARM/SOCFPGA EDAC SUPPORT
>> +M:	Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>> +S:	Maintained
>> +F:	arch/arm/mach-socfpga/l2_cache.*
>> +F:	arch/arm/mach-socfpga/ocram.*
>> +
>>   ARM/STI ARCHITECTURE
>>   M:	Srinivas Kandagatla <srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>   M:	Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
>> diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
>> index d7a5855..e757a33 100644
>> --- a/arch/arm/configs/socfpga_defconfig
>> +++ b/arch/arm/configs/socfpga_defconfig
>> @@ -123,3 +123,4 @@ CONFIG_USB=y
>>   CONFIG_USB_DWC2=y
>>   CONFIG_USB_DWC2_HOST=y
>>   CONFIG_USB_DWC2_PLATFORM=y
>> +CONFIG_SRAM=y
>> \ No newline at end of file
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index 6dd7a93..851a144 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -4,3 +4,5 @@
>>   
>>   obj-y					:= socfpga.o
>>   obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o
>> +obj-$(CONFIG_EDAC_ALTERA_OCRAM) += ocram.o
>> +obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
>> diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
>> new file mode 100644
>> index 0000000..8e109f3
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/l2_cache.c
>> @@ -0,0 +1,44 @@
>> +/*
>> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/of_address.h>
>> +
>> +#include "l2_cache.h"
>> +
>> +void socfpga_init_l2_ecc(void)
>> +{
>> +	struct device_node *np;
>> +	void __iomem  *mapped_l2_edac_addr;
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
>> +	if (!np) {
>> +		pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
>> +		return;
>> +	}
>> +
>> +	mapped_l2_edac_addr = of_iomap(np, 0);
>> +	if (!mapped_l2_edac_addr) {
>> +		pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
>> +		return;
>> +	}
>> +
>> +	/* Enable ECC */
>> +	writel(0x01, mapped_l2_edac_addr);
>> +
>> +	pr_debug("SOCFPGA: Success Initializing L2 cache ECC\n");
>> +}
>> +
>> diff --git a/arch/arm/mach-socfpga/l2_cache.h b/arch/arm/mach-socfpga/l2_cache.h
>> new file mode 100644
>> index 0000000..58e140d
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/l2_cache.h
>> @@ -0,0 +1,28 @@
>> +/*
>> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef MACH_SOCFPGA_L2_CACHE_H
>> +#define MACH_SOCFPGA_L2_CACHE_H
>> +
>> +#ifdef CONFIG_EDAC_ALTERA_L2C
>> +void socfpga_init_l2_ecc(void);
>> +#else
>> +inline void socfpga_init_l2_ecc(void)
>> +{
>> +}
>> +#endif
>> +
>> +#endif /* #ifndef MACH_SOCFPGA_L2_CACHE_H */
>> diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
>> new file mode 100644
>> index 0000000..26ec113
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/ocram.c
>> @@ -0,0 +1,84 @@
>> +/*
>> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +#include <linux/clk-provider.h>
>> +#include <linux/genalloc.h>
>> +#include <linux/of_platform.h>
>> +
>> +#include "ocram.h"
>> +
>> +void socfpga_init_ocram_ecc(void)
>> +{
>> +	struct device_node *np;
>> +	const __be32 *prop;
>> +	u32 ocr_edac_addr, iram_addr, len;
>> +	void __iomem  *mapped_ocr_edac_addr;
>> +	size_t size;
>> +	struct gen_pool *gp;
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
>> +	if (!np) {
>> +		pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
>> +		return;
>> +	}
>> +
>> +	prop = of_get_property(np, "reg", &size);
>> +	ocr_edac_addr = be32_to_cpup(prop++);
>> +	len = be32_to_cpup(prop);
>> +	if (!prop || size < sizeof(*prop)) {
>> +		pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
>> +		return;
>> +	}
>> +
>> +	gp = of_get_named_gen_pool(np, "iram", 0);
>> +	if (!gp) {
>> +		pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
>> +		return;
>> +	}
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "mmio-sram");
>> +	if (!np) {
>> +		pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
>> +		return;
>> +	}
>> +	/* Determine the OCRAM address and size */
>> +	prop = of_get_property(np, "reg", &size);
>> +	iram_addr = be32_to_cpup(prop++);
>> +	len = be32_to_cpup(prop);
>> +
>> +	if (!prop || size < sizeof(*prop)) {
>> +		pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
>> +		return;
>> +	}
>> +
>> +	iram_addr = gen_pool_alloc(gp, len);
>> +	if (iram_addr == 0) {
>> +		pr_err("SOCFPGA: cannot alloc from gen pool\n");
>> +		return;
>> +	}
>> +
>> +	memset((void *)iram_addr, 0, len);
>> +
>> +	mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
>> +
>> +	gen_pool_free(gp, iram_addr, len);
>> +
>> +	/* Clear any pending OCRAM ECC interrupts, then enable ECC */
>> +	writel(0x18, mapped_ocr_edac_addr);
>> +	writel(0x19, mapped_ocr_edac_addr);
>> +
>> +	pr_debug("SOCFPGA: Success Initializing OCRAM\n");
>> +}
>> +
>> diff --git a/arch/arm/mach-socfpga/ocram.h b/arch/arm/mach-socfpga/ocram.h
>> new file mode 100644
>> index 0000000..f93cf84
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/ocram.h
>> @@ -0,0 +1,28 @@
>> +/*
>> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program.  If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef MACH_SOCFPGA_OCRAM_H
>> +#define MACH_SOCFPGA_OCRAM_H
>> +
>> +#ifdef CONFIG_EDAC_ALTERA_OCRAM
>> +void socfpga_init_ocram_ecc(void);
>> +#else
>> +inline void socfpga_init_ocram_ecc(void)
>> +{
>> +}
>> +#endif
>> +
>> +#endif /* #ifndef MACH_SOCFPGA_OCRAM_H */
>> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
>> index adbf383..fb41aca 100644
>> --- a/arch/arm/mach-socfpga/socfpga.c
>> +++ b/arch/arm/mach-socfpga/socfpga.c
>> @@ -1,5 +1,5 @@
>>   /*
>> - *  Copyright (C) 2012 Altera Corporation
>> + *  Copyright (C) 2012;2014 Altera Corporation
>>    *
>>    * This program is free software; you can redistribute it and/or modify
>>    * it under the terms of the GNU General Public License as published by
>> @@ -25,6 +25,8 @@
>>   #include <asm/mach/map.h>
>>   
>>   #include "core.h"
>> +#include "l2_cache.h"
>> +#include "ocram.h"
>>   
>>   void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
>>   void __iomem *sys_manager_base_addr;
>> @@ -83,6 +85,7 @@ static void __init socfpga_init_irq(void)
>>   {
>>   	irqchip_init();
>>   	socfpga_sysmgr_init();
>> +	socfpga_init_l2_ecc();
>>   }
>>   
>>   static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
>>   	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>   }
>>   
>> +static void __init socfpga_cyclone5_init(void)
>> +{
>> +	of_platform_populate(NULL, of_default_bus_match_table,
>> +			     NULL, NULL);
> Why is this needed?
>
> Dinh
Hi Dinh.

Are you asking why the of_platform_populate() is needed? If so, it is 
used to kick off discovery of devices at the root of the tree.

If you're asking about the ocram.* and l2-cache.* files, they're used to 
enable ECC on startup.

Thor
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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Dinh Nguyen]

On 10/1/14, 4:07 PM, Thor Thayer wrote:
> 
> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>
>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>
[...]
>>>     static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>> char *cmd)
>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>> reboot_mode mode, const char *cmd)
>>>       writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>   }
>>>   +static void __init socfpga_cyclone5_init(void)
>>> +{
>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>> +                 NULL, NULL);
>> Why is this needed?
>>
>> Dinh
> Hi Dinh.
> 
> Are you asking why the of_platform_populate() is needed? If so, it is
> used to kick off discovery of devices at the root of the tree.

I was asking about of_platform populate(). This was removed in this commit:

8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation

Just trying to understand what's the need to add it back?

Dinh
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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Thor Thayer]

On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>
> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>
> [...]
>>>>      static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>> char *cmd)
>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>> reboot_mode mode, const char *cmd)
>>>>        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>    }
>>>>    +static void __init socfpga_cyclone5_init(void)
>>>> +{
>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>> +                 NULL, NULL);
>>> Why is this needed?
>>>
>>> Dinh
>> Hi Dinh.
>>
>> Are you asking why the of_platform_populate() is needed? If so, it is
>> used to kick off discovery of devices at the root of the tree.
> I was asking about of_platform populate(). This was removed in this commit:
>
> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>
> Just trying to understand what's the need to add it back?
>
> Dinh
It is used to kick off discovery of devices at the root of the tree.  
This is needed when .init_machine was defined because we're not using 
the default implementation (which called this function).

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Re: [PATCH 2/3] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[Mark Rutland]

> >> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
> >> @@ -0,0 +1,15 @@
> >> +Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
> >> +
> >> +Required Properties:
> >> +- compatible : Should be "altr,l2-edac"
> > That string looks too generic.
> >
> > Given the EDAC seems to be a portion of the L2, is there not already an
> > L2 binding?
> >
> > Just because Linux expects two drivers doesn't mean we should partition
> > the HW description this way.
> Thank you for the quick feedback.
> What should the string look like? I was trying to keep it short with the 
> altr, prefix but I don't mind changing it to something better.
> We're using the ARM PL310 L2 cache controller. The ECC is separate from 
> the PL310 IP and is part of the System Manager. This is true of ECC for 
> both the L2 and OCRAM.

Ah, I see. Apologies, I assumed that this was part of the L2C.

[...]

> >> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
> >> new file mode 100644
> >> index 0000000..31ab205
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
> >> @@ -0,0 +1,16 @@
> >> +Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
> >> +
> >> +OCRAM ECC Required Properties:
> >> +- compatible : Should be "altr,ocram-edac"
> >> +- reg : Address and size for ECC error interrupt clear registers.
> >> +- iram : phandle to On-Chip RAM definition.
> > Why not just describe this in the OCRAM node? Surely the register is
> > within the OCRAM controller?
> The ECC registers not in the OCRAM controller but they are in the System 
> Manager.  Maybe both the L2 cache and OCRAM ECC bindings should live 
> there and the device tree node for System Manager would have OCRAM and 
> L2 cache sub-nodes.

It certainly sounds like the ECC registers should be described as a
portion of the system manager somehow.

Thanks,
Mark.
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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Dinh Nguyen]

On 10/1/14, 5:18 PM, Thor Thayer wrote:
> 
> On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>>
>> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>>
>> [...]
>>>>>      static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>>> char *cmd)
>>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>>> reboot_mode mode, const char *cmd)
>>>>>        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>>    }
>>>>>    +static void __init socfpga_cyclone5_init(void)
>>>>> +{
>>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>>> +                 NULL, NULL);
>>>> Why is this needed?
>>>>
>>>> Dinh
>>> Hi Dinh.
>>>
>>> Are you asking why the of_platform_populate() is needed? If so, it is
>>> used to kick off discovery of devices at the root of the tree.
>> I was asking about of_platform populate(). This was removed in this
>> commit:
>>
>> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>>
>> Just trying to understand what's the need to add it back?
>>
>> Dinh
> It is used to kick off discovery of devices at the root of the tree. 
> This is needed when .init_machine was defined because we're not using
> the default implementation (which called this function).
> 

Then, can you please add a separate patch to fix up the removal of the call?

Thanks,
Dinh
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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Thor Thayer]

On 10/02/2014 06:38 AM, Dinh Nguyen wrote:
>
> On 10/1/14, 5:18 PM, Thor Thayer wrote:
>> On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>>> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>>>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>>>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>>>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>>>
>>> [...]
>>>>>>       static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>>>> char *cmd)
>>>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>>>> reboot_mode mode, const char *cmd)
>>>>>>         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>>>     }
>>>>>>     +static void __init socfpga_cyclone5_init(void)
>>>>>> +{
>>>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>>>> +                 NULL, NULL);
>>>>> Why is this needed?
>>>>>
>>>>> Dinh
>>>> Hi Dinh.
>>>>
>>>> Are you asking why the of_platform_populate() is needed? If so, it is
>>>> used to kick off discovery of devices at the root of the tree.
>>> I was asking about of_platform populate(). This was removed in this
>>> commit:
>>>
>>> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>>>
>>> Just trying to understand what's the need to add it back?
>>>
>>> Dinh
>> It is used to kick off discovery of devices at the root of the tree.
>> This is needed when .init_machine was defined because we're not using
>> the default implementation (which called this function).
>>
> Then, can you please add a separate patch to fix up the removal of the call?
>
> Thanks,
> Dinh
I don't understand - maybe I'm missing something. This function call is 
needed to kick off discovery at the root of the tree.

When I defined a .init_machine function in our platform code, this 
function needed to be added.

Thor
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Re: Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Masami Hiramatsu]

Hi Dinh,

(2014/10/02 20:38), Dinh Nguyen wrote:
> On 10/1/14, 5:18 PM, Thor Thayer wrote:
>>
>> On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>>>
>>> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>>>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>>>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>>>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>>>
>>> [...]
>>>>>>      static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>>>> char *cmd)
>>>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>>>> reboot_mode mode, const char *cmd)
>>>>>>        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>>>    }
>>>>>>    +static void __init socfpga_cyclone5_init(void)
>>>>>> +{
>>>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>>>> +                 NULL, NULL);
>>>>> Why is this needed?
>>>>>
>>>>> Dinh
>>>> Hi Dinh.
>>>>
>>>> Are you asking why the of_platform_populate() is needed? If so, it is
>>>> used to kick off discovery of devices at the root of the tree.
>>> I was asking about of_platform populate(). This was removed in this
>>> commit:
>>>
>>> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>>>
>>> Just trying to understand what's the need to add it back?
>>>
>>> Dinh
>> It is used to kick off discovery of devices at the root of the tree. 
>> This is needed when .init_machine was defined because we're not using
>> the default implementation (which called this function).
>>
> 
> Then, can you please add a separate patch to fix up the removal of the call?

It seems that this patch does enough reasonable thing.

To initialize ECC on OCRAM, socfpga_init_ocram_ecc() must be invoked
while booting. In that case, he might need this function.

8b5c18f05 is to replace l2x0_of_init() with .l2c_aux_* fields, and
this patch has a different reason to call another init function in
.init_machine. In this case, it is natural to define .init_machine
handler in this patch.

IOW, both use same socfpga_cyclone5_init() for the function name,
but those have different purpose. I think it is not reviving the
old function, but just adding a new function which has same name.

Thank you,

-- 
Masami HIRAMATSU
Software Platform Research Dept. Linux Technology Research Center
Hitachi, Ltd., Yokohama Research Laboratory
E-mail: masami.hiramatsu.pt-FCd8Q96Dh0JBDgjK7y7TUQ@public.gmane.org


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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Dinh Nguyen]

On 10/03/2014 04:51 AM, Masami Hiramatsu wrote:
> Hi Dinh,
> 
> (2014/10/02 20:38), Dinh Nguyen wrote:
>> On 10/1/14, 5:18 PM, Thor Thayer wrote:
>>>
>>> On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>>>>
>>>> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>>>>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>>>>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>>>>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>>>>
>>>> [...]
>>>>>>>      static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>>>>> char *cmd)
>>>>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>>>>> reboot_mode mode, const char *cmd)
>>>>>>>        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>>>>    }
>>>>>>>    +static void __init socfpga_cyclone5_init(void)
>>>>>>> +{
>>>>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>>>>> +                 NULL, NULL);
>>>>>> Why is this needed?
>>>>>>
>>>>>> Dinh
>>>>> Hi Dinh.
>>>>>
>>>>> Are you asking why the of_platform_populate() is needed? If so, it is
>>>>> used to kick off discovery of devices at the root of the tree.
>>>> I was asking about of_platform populate(). This was removed in this
>>>> commit:
>>>>
>>>> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>>>>
>>>> Just trying to understand what's the need to add it back?
>>>>
>>>> Dinh
>>> It is used to kick off discovery of devices at the root of the tree. 
>>> This is needed when .init_machine was defined because we're not using
>>> the default implementation (which called this function).
>>>
>>
>> Then, can you please add a separate patch to fix up the removal of the call?
> 
> It seems that this patch does enough reasonable thing.
> 
> To initialize ECC on OCRAM, socfpga_init_ocram_ecc() must be invoked
> while booting. In that case, he might need this function.
> 
> 8b5c18f05 is to replace l2x0_of_init() with .l2c_aux_* fields, and
> this patch has a different reason to call another init function in
> .init_machine. In this case, it is natural to define .init_machine
> handler in this patch.

8b5c18f05 also removes the need for .init_machine because
of_platform_populate() is now called by common arm code.

> 
> IOW, both use same socfpga_cyclone5_init() for the function name,
> but those have different purpose. I think it is not reviving the
> old function, but just adding a new function which has same name.
> 

So I'm just wondering if the call to socfpga_init_ocram_ecc() can be
done in socfpga_init_irq() along with the call to socfpga_init_l2_ecc(),
so that you don't have to bring back the custom init_machine callback.

Dinh

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Re: [PATCH 2/3] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[Thor Thayer]

On 10/02/2014 05:58 AM, Mark Rutland wrote:
>>>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
>>>> @@ -0,0 +1,15 @@
>>>> +Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
>>>> +
>>>> +Required Properties:
>>>> +- compatible : Should be "altr,l2-edac"
>>> That string looks too generic.
>>>
>>> Given the EDAC seems to be a portion of the L2, is there not already an
>>> L2 binding?
>>>
>>> Just because Linux expects two drivers doesn't mean we should partition
>>> the HW description this way.
>> Thank you for the quick feedback.
>> What should the string look like? I was trying to keep it short with the
>> altr, prefix but I don't mind changing it to something better.
>> We're using the ARM PL310 L2 cache controller. The ECC is separate from
>> the PL310 IP and is part of the System Manager. This is true of ECC for
>> both the L2 and OCRAM.
> Ah, I see. Apologies, I assumed that this was part of the L2C.
>
> [...]
>
>>>> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
>>>> new file mode 100644
>>>> index 0000000..31ab205
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
>>>> @@ -0,0 +1,16 @@
>>>> +Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
>>>> +
>>>> +OCRAM ECC Required Properties:
>>>> +- compatible : Should be "altr,ocram-edac"
>>>> +- reg : Address and size for ECC error interrupt clear registers.
>>>> +- iram : phandle to On-Chip RAM definition.
>>> Why not just describe this in the OCRAM node? Surely the register is
>>> within the OCRAM controller?
>> The ECC registers not in the OCRAM controller but they are in the System
>> Manager.  Maybe both the L2 cache and OCRAM ECC bindings should live
>> there and the device tree node for System Manager would have OCRAM and
>> L2 cache sub-nodes.
> It certainly sounds like the ECC registers should be described as a
> portion of the system manager somehow.
>
> Thanks,
> Mark.
Hi Mark.

After looking at this, it still seems like adding individual nodes as 
shown in this patch makes the most sense.

We don't currently have another driver to use as a parent so I'd need to 
create a driver (System Manager) that only probed these drivers. 
Although that would make the device tree look nicer, it isn't a clean 
solution overall.

Thanks for looking this over and I appreciate your feedback - it made me 
mull over other alternatives.

Thor
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Re: Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Masami Hiramatsu]

(2014/10/04 6:42), Dinh Nguyen wrote:
> On 10/03/2014 04:51 AM, Masami Hiramatsu wrote:
>> Hi Dinh,
>>
>> (2014/10/02 20:38), Dinh Nguyen wrote:
>>> On 10/1/14, 5:18 PM, Thor Thayer wrote:
>>>>
>>>> On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>>>>>
>>>>> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>>>>>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>>>>>> On 10/1/14, 11:31 AM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>>>>>>>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>>>>>
>>>>> [...]
>>>>>>>>      static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>>>>>> char *cmd)
>>>>>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>>>>>> reboot_mode mode, const char *cmd)
>>>>>>>>        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>>>>>    }
>>>>>>>>    +static void __init socfpga_cyclone5_init(void)
>>>>>>>> +{
>>>>>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>>>>>> +                 NULL, NULL);
>>>>>>> Why is this needed?
>>>>>>>
>>>>>>> Dinh
>>>>>> Hi Dinh.
>>>>>>
>>>>>> Are you asking why the of_platform_populate() is needed? If so, it is
>>>>>> used to kick off discovery of devices at the root of the tree.
>>>>> I was asking about of_platform populate(). This was removed in this
>>>>> commit:
>>>>>
>>>>> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>>>>>
>>>>> Just trying to understand what's the need to add it back?
>>>>>
>>>>> Dinh
>>>> It is used to kick off discovery of devices at the root of the tree. 
>>>> This is needed when .init_machine was defined because we're not using
>>>> the default implementation (which called this function).
>>>>
>>>
>>> Then, can you please add a separate patch to fix up the removal of the call?
>>
>> It seems that this patch does enough reasonable thing.
>>
>> To initialize ECC on OCRAM, socfpga_init_ocram_ecc() must be invoked
>> while booting. In that case, he might need this function.
>>
>> 8b5c18f05 is to replace l2x0_of_init() with .l2c_aux_* fields, and
>> this patch has a different reason to call another init function in
>> .init_machine. In this case, it is natural to define .init_machine
>> handler in this patch.
> 
> 8b5c18f05 also removes the need for .init_machine because
> of_platform_populate() is now called by common arm code.
> 
>>
>> IOW, both use same socfpga_cyclone5_init() for the function name,
>> but those have different purpose. I think it is not reviving the
>> old function, but just adding a new function which has same name.
>>
> 
> So I'm just wondering if the call to socfpga_init_ocram_ecc() can be
> done in socfpga_init_irq() along with the call to socfpga_init_l2_ecc(),
> so that you don't have to bring back the custom init_machine callback.

Indeed, it will be better and simpler.

Thank you,

-- 
Masami HIRAMATSU
Software Platform Research Dept. Linux Technology Research Center
Hitachi, Ltd., Yokohama Research Laboratory
E-mail: masami.hiramatsu.pt-FCd8Q96Dh0JBDgjK7y7TUQ@public.gmane.org


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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Masami Hiramatsu]

(2014/10/02 1:31), tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> +void socfpga_init_ocram_ecc(void)
> +{
> +	struct device_node *np;
> +	const __be32 *prop;
> +	u32 ocr_edac_addr, iram_addr, len;
> +	void __iomem  *mapped_ocr_edac_addr;
> +	size_t size;
> +	struct gen_pool *gp;
> +
> +	np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
> +	if (!np) {
> +		pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
> +		return;
> +	}
> +
> +	prop = of_get_property(np, "reg", &size);
> +	ocr_edac_addr = be32_to_cpup(prop++);
> +	len = be32_to_cpup(prop);
> +	if (!prop || size < sizeof(*prop)) {
> +		pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
> +		return;
> +	}
> +
> +	gp = of_get_named_gen_pool(np, "iram", 0);
> +	if (!gp) {
> +		pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
> +		return;
> +	}
> +
> +	np = of_find_compatible_node(NULL, NULL, "mmio-sram");
> +	if (!np) {
> +		pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
> +		return;
> +	}
> +	/* Determine the OCRAM address and size */
> +	prop = of_get_property(np, "reg", &size);
> +	iram_addr = be32_to_cpup(prop++);
> +	len = be32_to_cpup(prop);
> +
> +	if (!prop || size < sizeof(*prop)) {
> +		pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
> +		return;
> +	}
> +
> +	iram_addr = gen_pool_alloc(gp, len);
> +	if (iram_addr == 0) {
> +		pr_err("SOCFPGA: cannot alloc from gen pool\n");
> +		return;
> +	}
> +
> +	memset((void *)iram_addr, 0, len);
> +
> +	mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
> +
> +	gen_pool_free(gp, iram_addr, len);
> +
> +	/* Clear any pending OCRAM ECC interrupts, then enable ECC */
> +	writel(0x18, mapped_ocr_edac_addr);
> +	writel(0x19, mapped_ocr_edac_addr);

Should we better iounmap() here?
It seems no one can use mapped_ocr_edac_addr afterwords.

> +
> +	pr_debug("SOCFPGA: Success Initializing OCRAM\n");
> +}
> +

Thank you,


-- 
Masami HIRAMATSU
Software Platform Research Dept. Linux Technology Research Center
Hitachi, Ltd., Yokohama Research Laboratory
E-mail: masami.hiramatsu.pt-FCd8Q96Dh0JBDgjK7y7TUQ@public.gmane.org


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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Thor Thayer]

On 10/04/2014 11:21 PM, Masami Hiramatsu wrote:
> (2014/10/02 1:31), tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>> +void socfpga_init_ocram_ecc(void)
>> +{
>> +	struct device_node *np;
>> +	const __be32 *prop;
>> +	u32 ocr_edac_addr, iram_addr, len;
>> +	void __iomem  *mapped_ocr_edac_addr;
>> +	size_t size;
>> +	struct gen_pool *gp;
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
>> +	if (!np) {
>> +		pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
>> +		return;
>> +	}
>> +
>> +	prop = of_get_property(np, "reg", &size);
>> +	ocr_edac_addr = be32_to_cpup(prop++);
>> +	len = be32_to_cpup(prop);
>> +	if (!prop || size < sizeof(*prop)) {
>> +		pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
>> +		return;
>> +	}
>> +
>> +	gp = of_get_named_gen_pool(np, "iram", 0);
>> +	if (!gp) {
>> +		pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
>> +		return;
>> +	}
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "mmio-sram");
>> +	if (!np) {
>> +		pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
>> +		return;
>> +	}
>> +	/* Determine the OCRAM address and size */
>> +	prop = of_get_property(np, "reg", &size);
>> +	iram_addr = be32_to_cpup(prop++);
>> +	len = be32_to_cpup(prop);
>> +
>> +	if (!prop || size < sizeof(*prop)) {
>> +		pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
>> +		return;
>> +	}
>> +
>> +	iram_addr = gen_pool_alloc(gp, len);
>> +	if (iram_addr == 0) {
>> +		pr_err("SOCFPGA: cannot alloc from gen pool\n");
>> +		return;
>> +	}
>> +
>> +	memset((void *)iram_addr, 0, len);
>> +
>> +	mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
>> +
>> +	gen_pool_free(gp, iram_addr, len);
>> +
>> +	/* Clear any pending OCRAM ECC interrupts, then enable ECC */
>> +	writel(0x18, mapped_ocr_edac_addr);
>> +	writel(0x19, mapped_ocr_edac_addr);
> Should we better iounmap() here?
> It seems no one can use mapped_ocr_edac_addr afterwords.
>

Yes, I will make this change. Thank you!

>> +
>> +	pr_debug("SOCFPGA: Success Initializing OCRAM\n");
>> +}
>> +
> Thank you,
>
>

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Re: [PATCH 1/3] arm: socfpga: Enable ECC of L2 and OCRAM on startup.

[Thor Thayer]

On 10/04/2014 11:18 PM, Masami Hiramatsu wrote:
> (2014/10/04 6:42), Dinh Nguyen wrote:
>> On 10/03/2014 04:51 AM, Masami Hiramatsu wrote:
>>> Hi Dinh,
>>>
>>> (2014/10/02 20:38), Dinh Nguyen wrote:
>>>> On 10/1/14, 5:18 PM, Thor Thayer wrote:
>>>>> On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
>>>>>> On 10/1/14, 4:07 PM, Thor Thayer wrote:
>>>>>>> On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
>>>>>>>> On 10/1/14, 11:31 AM,tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org  wrote:
>>>>>>>>> From: Thor Thayer<tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>>>>>>>>
>>>>>> [...]
>>>>>>>>>       static void socfpga_cyclone5_restart(enum reboot_mode mode, const
>>>>>>>>> char *cmd)
>>>>>>>>> @@ -98,6 +101,13 @@ static void socfpga_cyclone5_restart(enum
>>>>>>>>> reboot_mode mode, const char *cmd)
>>>>>>>>>         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
>>>>>>>>>     }
>>>>>>>>>     +static void __init socfpga_cyclone5_init(void)
>>>>>>>>> +{
>>>>>>>>> +    of_platform_populate(NULL, of_default_bus_match_table,
>>>>>>>>> +                 NULL, NULL);
>>>>>>>> Why is this needed?
>>>>>>>>
>>>>>>>> Dinh
>>>>>>> Hi Dinh.
>>>>>>>
>>>>>>> Are you asking why the of_platform_populate() is needed? If so, it is
>>>>>>> used to kick off discovery of devices at the root of the tree.
>>>>>> I was asking about of_platform populate(). This was removed in this
>>>>>> commit:
>>>>>>
>>>>>> 8b5c18f05 ARM: l2c: socfpga: convert to generic l2c OF initialisation
>>>>>>
>>>>>> Just trying to understand what's the need to add it back?
>>>>>>
>>>>>> Dinh
>>>>> It is used to kick off discovery of devices at the root of the tree.
>>>>> This is needed when .init_machine was defined because we're not using
>>>>> the default implementation (which called this function).
>>>>>
>>>> Then, can you please add a separate patch to fix up the removal of the call?
>>> It seems that this patch does enough reasonable thing.
>>>
>>> To initialize ECC on OCRAM, socfpga_init_ocram_ecc() must be invoked
>>> while booting. In that case, he might need this function.
>>>
>>> 8b5c18f05 is to replace l2x0_of_init() with .l2c_aux_* fields, and
>>> this patch has a different reason to call another init function in
>>> .init_machine. In this case, it is natural to define .init_machine
>>> handler in this patch.
>> 8b5c18f05 also removes the need for .init_machine because
>> of_platform_populate() is now called by common arm code.
>>
>>> IOW, both use same socfpga_cyclone5_init() for the function name,
>>> but those have different purpose. I think it is not reviving the
>>> old function, but just adding a new function which has same name.
>>>
>> So I'm just wondering if the call to socfpga_init_ocram_ecc() can be
>> done in socfpga_init_irq() along with the call to socfpga_init_l2_ecc(),
>> so that you don't have to bring back the custom init_machine callback.
> Indeed, it will be better and simpler.
>
> Thank you,
>
Hi. I didn't explain this well in my previous comments.

The call to socfpga_init_ocram_ecc() needs to be in .init_machine 
because socfpga_init_ocram_ecc() needs the device tree structure to be 
populated to dereference the sram handle. It is in the .init_machine 
function that the device tree discovery/population process is kicked off 
so it makes sense to add it here.

I originally tried adding socfpga_init_ocram_ecc() in the 
socfpga_init_irq() but the sram phandle couldn't be parsed.

I'm moving the OCRAM addition into a separate patch as requested by Dinh.

Thor

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