All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Suzuki K. Poulose" <Suzuki.Poulose@arm.com>
To: Alexander Kuleshov <kuleshovmail@gmail.com>,
	Catalin Marinas <Catalin.Marinas@arm.com>,
	Will Deacon <Will.Deacon@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing
Date: Fri, 04 Sep 2015 13:00:10 +0100	[thread overview]
Message-ID: <55E987CA.4090302@arm.com> (raw)
In-Reply-To: <1441303911-9421-1-git-send-email-kuleshovmail@gmail.com>

On 03/09/15 19:11, Alexander Kuleshov wrote:
> This patch provides a couple of macros for the testing of processor
> features (crypto and FP/SIMD) like support of SHA1, AES instructions,
> support for FPU and etc. There is already a couple of places in the
> arch/arm64/kernel where these processor features are tested and these
> macros are facilitate this.
>
> Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com>
> ---
>   arch/arm64/include/asm/cpufeature.h | 44 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index c104421..2919455 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -28,7 +28,50 @@
>
>   #define ARM64_NCAPS				4
>
> +/*
> + * ID_AA64ISAR0_EL1 AES, bits [7:4]
> + */
> +#define ID_AA64ISAR0_EL1_AES_MASK	4
> +#define ID_AA64ISAR0_EL1_AES(feature)	\
> +	(((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 1UL)
> +#define ID_AA64ISAR0_EL1_PMULL(feature)	\
> +	(((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 2UL)
> +


There is generic CPUID feature helper queued for 4.3, which can extract
the feature bits

  cpuid_feature_extract_field(feature, shift)

You might want to use it instead. Btw, I have a patch series(waiting for
the merge window, before I post), which changes the way we initialise the
HWCAP bits.

Thanks
Suzuki


WARNING: multiple messages have this Message-ID (diff)
From: Suzuki.Poulose@arm.com (Suzuki K. Poulose)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing
Date: Fri, 04 Sep 2015 13:00:10 +0100	[thread overview]
Message-ID: <55E987CA.4090302@arm.com> (raw)
In-Reply-To: <1441303911-9421-1-git-send-email-kuleshovmail@gmail.com>

On 03/09/15 19:11, Alexander Kuleshov wrote:
> This patch provides a couple of macros for the testing of processor
> features (crypto and FP/SIMD) like support of SHA1, AES instructions,
> support for FPU and etc. There is already a couple of places in the
> arch/arm64/kernel where these processor features are tested and these
> macros are facilitate this.
>
> Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com>
> ---
>   arch/arm64/include/asm/cpufeature.h | 44 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index c104421..2919455 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -28,7 +28,50 @@
>
>   #define ARM64_NCAPS				4
>
> +/*
> + * ID_AA64ISAR0_EL1 AES, bits [7:4]
> + */
> +#define ID_AA64ISAR0_EL1_AES_MASK	4
> +#define ID_AA64ISAR0_EL1_AES(feature)	\
> +	(((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 1UL)
> +#define ID_AA64ISAR0_EL1_PMULL(feature)	\
> +	(((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 2UL)
> +


There is generic CPUID feature helper queued for 4.3, which can extract
the feature bits

  cpuid_feature_extract_field(feature, shift)

You might want to use it instead. Btw, I have a patch series(waiting for
the merge window, before I post), which changes the way we initialise the
HWCAP bits.

Thanks
Suzuki

  parent reply	other threads:[~2015-09-04 12:00 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-03 18:11 [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing Alexander Kuleshov
2015-09-03 18:11 ` Alexander Kuleshov
2015-09-03 18:12 ` [PATCH 2/3] arm64/setup: Use ID_AA64ISAR0_EL1_.* macros Alexander Kuleshov
2015-09-03 18:12   ` Alexander Kuleshov
2015-09-04 11:26   ` Catalin Marinas
2015-09-04 11:26     ` Catalin Marinas
2016-11-07 16:30   ` Suzuki K Poulose
2016-11-07 16:30     ` Suzuki K Poulose
2015-09-03 18:12 ` [PATCH 3/3] arm64/fpsimd: Use ID_AA64PFR0_EL1_.* macros Alexander Kuleshov
2015-09-03 18:12   ` Alexander Kuleshov
2016-11-07 16:31   ` Suzuki K Poulose
2016-11-07 16:31     ` Suzuki K Poulose
2015-09-04 11:25 ` [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing Catalin Marinas
2015-09-04 11:25   ` Catalin Marinas
2015-09-04 12:00 ` Suzuki K. Poulose [this message]
2015-09-04 12:00   ` Suzuki K. Poulose
2015-09-04 12:19   ` Alexander Kuleshov
2015-09-04 12:19     ` Alexander Kuleshov
2015-09-16 14:48     ` Suzuki K. Poulose
2015-09-16 14:48       ` Suzuki K. Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=55E987CA.4090302@arm.com \
    --to=suzuki.poulose@arm.com \
    --cc=Catalin.Marinas@arm.com \
    --cc=Will.Deacon@arm.com \
    --cc=kuleshovmail@gmail.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.