From: Greentime Hu <green.hu@gmail.com> To: greentime@andestech.com, linux-kernel@vger.kernel.org, arnd@arndb.de, linux-arch@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, netdev@vger.kernel.org, deanbo422@gmail.com, devicetree@vger.kernel.org, viro@zeniv.linux.org.uk, dhowells@redhat.com, will.deacon@arm.com, daniel.lezcano@linaro.org, linux-serial@vger.kernel.org Cc: green.hu@gmail.com, Vincent Chen <vincentc@andestech.com> Subject: [PATCH v2 10/35] nds32: Atomic operations Date: Mon, 27 Nov 2017 20:27:57 +0800 [thread overview] Message-ID: <56a24fae3cec68f80c41eebd98fcceb9b137ac64.1511785528.git.green.hu@gmail.com> (raw) In-Reply-To: <cover.1511785528.git.green.hu@gmail.com> In-Reply-To: <cover.1511785528.git.green.hu@gmail.com> From: Greentime Hu <greentime@andestech.com> This patch includes the atomic and futex operations. Many atomic operations use the load-lock word(llw) and store-condition word(scw) operations. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> --- arch/nds32/include/asm/futex.h | 116 +++++++++++++++++++++++ arch/nds32/include/asm/spinlock.h | 184 +++++++++++++++++++++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 arch/nds32/include/asm/futex.h create mode 100644 arch/nds32/include/asm/spinlock.h diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h new file mode 100644 index 0000000..5aa107c --- /dev/null +++ b/arch/nds32/include/asm/futex.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NDS32_FUTEX_H__ +#define __NDS32_FUTEX_H__ + +#include <linux/futex.h> +#include <linux/uaccess.h> +#include <asm/errno.h> + +#define __futex_atomic_ex_table(err_reg) \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4f\n" \ + " .long 2b, 4f\n" \ + " .popsection\n" \ + " .pushsection .fixup,\"ax\"\n" \ + "4: move %0, " err_reg "\n" \ + " j 3b\n" \ + " .popsection" + +#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ + smp_mb(); \ + asm volatile( \ + " movi $ta, #0\n" \ + "1: llw %1, [%2+$ta]\n" \ + " " insn "\n" \ + "2: scw %0, [%2+$ta]\n" \ + " beqz %0, 1b\n" \ + " movi %0, #0\n" \ + "3:\n" \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ + : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \ + : "cc", "memory") +static inline int +futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr, + u32 oldval, u32 newval) +{ + int ret = 0; + u32 val, tmp, flags; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + smp_mb(); + asm volatile (" movi $ta, #0\n" + "1: llw %1, [%6 + $ta]\n" + " sub %3, %1, %4\n" + " cmovz %2, %5, %3\n" + " cmovn %2, %1, %3\n" + "2: scw %2, [%6 + $ta]\n" + " beqz %2, 1b\n" + "3:\n " __futex_atomic_ex_table("%7") + :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags) + :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT) + :"$ta", "memory"); + smp_mb(); + + *uval = val; + return ret; +} + +static inline int +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +{ + int oldval = 0, ret; + + + pagefault_disable(); + switch (op) { + case FUTEX_OP_SET: + __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr, + oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op("add %0, %1, %3", ret, oldval, tmp, uaddr, + oparg); + break; + case FUTEX_OP_OR: + __futex_atomic_op("or %0, %1, %3", ret, oldval, tmp, uaddr, + oparg); + break; + case FUTEX_OP_ANDN: + __futex_atomic_op("and %0, %1, %3", ret, oldval, tmp, uaddr, + ~oparg); + break; + case FUTEX_OP_XOR: + __futex_atomic_op("xor %0, %1, %3", ret, oldval, tmp, uaddr, + oparg); + break; + default: + ret = -ENOSYS; + } + + pagefault_enable(); + + if (!ret) + *oval = oldval; + + return ret; +} +#endif /* __NDS32_FUTEX_H__ */ diff --git a/arch/nds32/include/asm/spinlock.h b/arch/nds32/include/asm/spinlock.h new file mode 100644 index 0000000..ca70437 --- /dev/null +++ b/arch/nds32/include/asm/spinlock.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ASM_SPINLOCK_H +#define __ASM_SPINLOCK_H + +#include <asm/processor.h> + +#define arch_spin_is_locked(x) ((x)->lock != 0) + +#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) + +static inline void arch_spin_lock(arch_spinlock_t * lock) +{ + unsigned long tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "bnez %0, 1b\n" + "movi %0, #0x1\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&lock->lock) + :"memory"); +} + +static inline int arch_spin_trylock(arch_spinlock_t * lock) +{ + unsigned long ret, tmp; + + asm volatile( + "1:\n" + "llw %0, [%2]\n" + "movi %1, #0x1\n" + "scw %1, [%2]\n" + "beqz %1, 1b\n" + :"=&r"(ret), "=&r"(tmp) + :"r"(&lock->lock) + :"memory"); + + return ret == 0; +} + +static inline void arch_spin_unlock(arch_spinlock_t * lock) +{ + asm volatile( + "xor $r15, $r15, $r15\n" + "swi $r15, [%0]\n" + : + :"r"(&lock->lock) + :"memory"); +} + +static inline void arch_write_lock(arch_rwlock_t * rw) +{ + unsigned long tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "bnez %0, 1b\n" + "sethi %0, 0x80000\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&rw->lock) + :"memory"); +} + +static inline void arch_write_unlock(arch_rwlock_t * rw) +{ + asm volatile( + "xor $r15, $r15, $r15\n" + "swi $r15, [%0]\n" + : + :"r"(&rw->lock) + :"memory","$r15"); +} + +#define arch_write_can_lock(x) ((x)->lock == 0) +static inline void arch_read_lock(arch_rwlock_t * rw) +{ + int tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "bltz %0, 1b\n" + "addi %0, %0, #1\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&rw->lock) + :"memory"); +} + +static inline void arch_read_unlock(arch_rwlock_t * rw) +{ + unsigned long tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "addi %0, %0, #-1\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&rw->lock) + :"memory"); +} + +static inline int arch_read_trylock(arch_rwlock_t * rw) +{ + unsigned long ret, tmp; + + asm volatile( + "movi %0, #0x0\n" + "1:\n" + "llw %1, [%2]\n" + "bltz %1, 2f\n" + "addi %1, %1, #1\n" + "scw %1, [%2]\n" + "beqz %1, 1b\n" + "movi %0, #0x1\n" + "j 3f\n" + "2:\n" + "scw %1, [%2]\n" + "3:\n" + :"=&r"(ret), "=&r"(tmp) + :"r"(&rw->lock) + :"memory"); + + return ret; +} + +static inline int arch_write_trylock(arch_rwlock_t * rw) +{ + unsigned long ret, tmp; + + asm volatile( + "movi %0, #0x0\n" + "1:\n" + "llw %1, [%2]\n" + "bnez %1, 2f\n" + "sethi %1, 0x80000\n" + "scw %1, [%2]\n" + "beqz %1, 1b\n" + "movi %0, #0x1\n" + "j 3f\n" + "2:\n" + "scw %1, [%2]\n" + "3:\n" + :"=&r"(ret), "=&r"(tmp) + :"r"(&rw->lock) + :"memory"); + + return ret; +} + +#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) +#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) + +#define arch_read_can_lock(x) ((x)->lock < 0x80000000) + +#define arch_spin_relax(lock) cpu_relax() +#define arch_read_relax(lock) cpu_relax() +#define arch_write_relax(lock) cpu_relax() + +#endif /* __ASM_SPINLOCK_H */ -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> To: greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org, linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org, jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org, marc.zyngier-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, deanbo422-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn@public.gmane.org, dhowells-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Vincent Chen <vincentc-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org> Subject: [PATCH v2 10/35] nds32: Atomic operations Date: Mon, 27 Nov 2017 20:27:57 +0800 [thread overview] Message-ID: <56a24fae3cec68f80c41eebd98fcceb9b137ac64.1511785528.git.green.hu@gmail.com> (raw) In-Reply-To: <cover.1511785528.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> In-Reply-To: <cover.1511785528.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org> This patch includes the atomic and futex operations. Many atomic operations use the load-lock word(llw) and store-condition word(scw) operations. Signed-off-by: Vincent Chen <vincentc-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org> Signed-off-by: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org> --- arch/nds32/include/asm/futex.h | 116 +++++++++++++++++++++++ arch/nds32/include/asm/spinlock.h | 184 +++++++++++++++++++++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 arch/nds32/include/asm/futex.h create mode 100644 arch/nds32/include/asm/spinlock.h diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h new file mode 100644 index 0000000..5aa107c --- /dev/null +++ b/arch/nds32/include/asm/futex.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NDS32_FUTEX_H__ +#define __NDS32_FUTEX_H__ + +#include <linux/futex.h> +#include <linux/uaccess.h> +#include <asm/errno.h> + +#define __futex_atomic_ex_table(err_reg) \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4f\n" \ + " .long 2b, 4f\n" \ + " .popsection\n" \ + " .pushsection .fixup,\"ax\"\n" \ + "4: move %0, " err_reg "\n" \ + " j 3b\n" \ + " .popsection" + +#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ + smp_mb(); \ + asm volatile( \ + " movi $ta, #0\n" \ + "1: llw %1, [%2+$ta]\n" \ + " " insn "\n" \ + "2: scw %0, [%2+$ta]\n" \ + " beqz %0, 1b\n" \ + " movi %0, #0\n" \ + "3:\n" \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ + : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \ + : "cc", "memory") +static inline int +futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr, + u32 oldval, u32 newval) +{ + int ret = 0; + u32 val, tmp, flags; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + smp_mb(); + asm volatile (" movi $ta, #0\n" + "1: llw %1, [%6 + $ta]\n" + " sub %3, %1, %4\n" + " cmovz %2, %5, %3\n" + " cmovn %2, %1, %3\n" + "2: scw %2, [%6 + $ta]\n" + " beqz %2, 1b\n" + "3:\n " __futex_atomic_ex_table("%7") + :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags) + :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT) + :"$ta", "memory"); + smp_mb(); + + *uval = val; + return ret; +} + +static inline int +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +{ + int oldval = 0, ret; + + + pagefault_disable(); + switch (op) { + case FUTEX_OP_SET: + __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr, + oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op("add %0, %1, %3", ret, oldval, tmp, uaddr, + oparg); + break; + case FUTEX_OP_OR: + __futex_atomic_op("or %0, %1, %3", ret, oldval, tmp, uaddr, + oparg); + break; + case FUTEX_OP_ANDN: + __futex_atomic_op("and %0, %1, %3", ret, oldval, tmp, uaddr, + ~oparg); + break; + case FUTEX_OP_XOR: + __futex_atomic_op("xor %0, %1, %3", ret, oldval, tmp, uaddr, + oparg); + break; + default: + ret = -ENOSYS; + } + + pagefault_enable(); + + if (!ret) + *oval = oldval; + + return ret; +} +#endif /* __NDS32_FUTEX_H__ */ diff --git a/arch/nds32/include/asm/spinlock.h b/arch/nds32/include/asm/spinlock.h new file mode 100644 index 0000000..ca70437 --- /dev/null +++ b/arch/nds32/include/asm/spinlock.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ASM_SPINLOCK_H +#define __ASM_SPINLOCK_H + +#include <asm/processor.h> + +#define arch_spin_is_locked(x) ((x)->lock != 0) + +#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) + +static inline void arch_spin_lock(arch_spinlock_t * lock) +{ + unsigned long tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "bnez %0, 1b\n" + "movi %0, #0x1\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&lock->lock) + :"memory"); +} + +static inline int arch_spin_trylock(arch_spinlock_t * lock) +{ + unsigned long ret, tmp; + + asm volatile( + "1:\n" + "llw %0, [%2]\n" + "movi %1, #0x1\n" + "scw %1, [%2]\n" + "beqz %1, 1b\n" + :"=&r"(ret), "=&r"(tmp) + :"r"(&lock->lock) + :"memory"); + + return ret == 0; +} + +static inline void arch_spin_unlock(arch_spinlock_t * lock) +{ + asm volatile( + "xor $r15, $r15, $r15\n" + "swi $r15, [%0]\n" + : + :"r"(&lock->lock) + :"memory"); +} + +static inline void arch_write_lock(arch_rwlock_t * rw) +{ + unsigned long tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "bnez %0, 1b\n" + "sethi %0, 0x80000\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&rw->lock) + :"memory"); +} + +static inline void arch_write_unlock(arch_rwlock_t * rw) +{ + asm volatile( + "xor $r15, $r15, $r15\n" + "swi $r15, [%0]\n" + : + :"r"(&rw->lock) + :"memory","$r15"); +} + +#define arch_write_can_lock(x) ((x)->lock == 0) +static inline void arch_read_lock(arch_rwlock_t * rw) +{ + int tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "bltz %0, 1b\n" + "addi %0, %0, #1\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&rw->lock) + :"memory"); +} + +static inline void arch_read_unlock(arch_rwlock_t * rw) +{ + unsigned long tmp; + + asm volatile( + "1:\n" + "llw %0, [%1]\n" + "addi %0, %0, #-1\n" + "scw %0, [%1]\n" + "beqz %0, 1b\n" + :"=&r"(tmp) + :"r"(&rw->lock) + :"memory"); +} + +static inline int arch_read_trylock(arch_rwlock_t * rw) +{ + unsigned long ret, tmp; + + asm volatile( + "movi %0, #0x0\n" + "1:\n" + "llw %1, [%2]\n" + "bltz %1, 2f\n" + "addi %1, %1, #1\n" + "scw %1, [%2]\n" + "beqz %1, 1b\n" + "movi %0, #0x1\n" + "j 3f\n" + "2:\n" + "scw %1, [%2]\n" + "3:\n" + :"=&r"(ret), "=&r"(tmp) + :"r"(&rw->lock) + :"memory"); + + return ret; +} + +static inline int arch_write_trylock(arch_rwlock_t * rw) +{ + unsigned long ret, tmp; + + asm volatile( + "movi %0, #0x0\n" + "1:\n" + "llw %1, [%2]\n" + "bnez %1, 2f\n" + "sethi %1, 0x80000\n" + "scw %1, [%2]\n" + "beqz %1, 1b\n" + "movi %0, #0x1\n" + "j 3f\n" + "2:\n" + "scw %1, [%2]\n" + "3:\n" + :"=&r"(ret), "=&r"(tmp) + :"r"(&rw->lock) + :"memory"); + + return ret; +} + +#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) +#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) + +#define arch_read_can_lock(x) ((x)->lock < 0x80000000) + +#define arch_spin_relax(lock) cpu_relax() +#define arch_read_relax(lock) cpu_relax() +#define arch_write_relax(lock) cpu_relax() + +#endif /* __ASM_SPINLOCK_H */ -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2017-11-27 13:07 UTC|newest] Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-11-27 12:27 [PATCH v2 00/35] Andes(nds32) Linux Kernel Port Greentime Hu 2017-11-27 12:27 ` [PATCH v2 01/35] nds32: Assembly macros and definitions Greentime Hu 2017-11-27 12:27 ` [PATCH v2 02/35] nds32: Kernel booting and initialization Greentime Hu 2017-11-27 12:27 ` [PATCH v2 03/35] nds32: Exception handling Greentime Hu 2017-11-27 12:27 ` [PATCH v2 04/35] nds32: MMU definitions Greentime Hu 2017-11-27 12:27 ` [PATCH v2 05/35] nds32: MMU initialization Greentime Hu 2017-11-27 12:27 ` [PATCH v2 06/35] nds32: MMU fault handling and page table management Greentime Hu 2017-11-27 13:51 ` Mark Rutland 2017-11-27 13:51 ` Mark Rutland 2017-11-29 7:24 ` Greentime Hu 2017-11-29 7:24 ` Greentime Hu 2017-12-07 16:40 ` Al Viro 2017-12-08 5:26 ` Greentime Hu 2017-12-08 5:26 ` Greentime Hu 2017-11-27 12:27 ` [PATCH v2 07/35] nds32: Cache and TLB routines Greentime Hu 2017-11-27 12:27 ` [PATCH v2 08/35] nds32: Process management Greentime Hu 2017-12-07 16:45 ` Al Viro 2017-12-08 5:27 ` Greentime Hu 2017-11-27 12:27 ` [PATCH v2 09/35] nds32: IRQ handling Greentime Hu 2017-11-27 12:27 ` Greentime Hu [this message] 2017-11-27 12:27 ` [PATCH v2 10/35] nds32: Atomic operations Greentime Hu 2017-11-27 13:57 ` Mark Rutland 2017-11-28 4:24 ` Vincent Chen 2017-11-27 12:27 ` [PATCH v2 11/35] nds32: Device specific operations Greentime Hu 2017-11-27 14:51 ` Arnd Bergmann 2017-11-27 12:27 ` [PATCH v2 12/35] nds32: DMA mapping API Greentime Hu 2017-11-27 12:28 ` [PATCH v2 13/35] nds32: ELF definitions Greentime Hu 2017-11-27 12:28 ` [PATCH v2 14/35] nds32: System calls handling Greentime Hu 2017-11-27 14:46 ` Arnd Bergmann 2017-11-28 2:18 ` Vincent Chen 2017-11-28 9:23 ` Arnd Bergmann 2017-11-27 12:28 ` [PATCH v2 15/35] nds32: VDSO support Greentime Hu 2017-11-27 12:28 ` [PATCH v2 16/35] nds32: Signal handling support Greentime Hu 2017-11-27 14:37 ` Arnd Bergmann 2017-11-27 14:37 ` Arnd Bergmann 2017-11-28 2:21 ` Vincent Chen 2017-11-28 2:21 ` Vincent Chen 2017-11-27 12:28 ` [PATCH v2 17/35] nds32: Library functions Greentime Hu 2017-11-27 12:28 ` [PATCH v2 18/35] nds32: Debugging support Greentime Hu 2017-11-27 14:34 ` Arnd Bergmann 2017-11-28 2:21 ` Vincent Chen 2017-11-28 2:21 ` Vincent Chen 2017-11-27 12:28 ` [PATCH v2 19/35] nds32: L2 cache support Greentime Hu 2017-11-27 14:33 ` Arnd Bergmann 2017-11-29 11:53 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 20/35] nds32: Loadable modules Greentime Hu 2017-11-27 12:28 ` [PATCH v2 21/35] nds32: Generic timers support Greentime Hu 2017-11-27 12:28 ` [PATCH v2 22/35] nds32: Device tree support Greentime Hu 2017-11-27 14:30 ` Arnd Bergmann 2017-11-28 6:54 ` Greentime Hu 2017-11-28 6:54 ` Greentime Hu 2017-11-27 19:07 ` Rob Herring 2017-11-27 19:14 ` Rob Herring 2017-12-02 16:47 ` Greentime Hu 2017-12-02 16:47 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 23/35] nds32: Miscellaneous header files Greentime Hu 2017-11-27 12:28 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 24/35] nds32: defconfig Greentime Hu 2017-11-27 14:27 ` Arnd Bergmann 2017-11-27 12:28 ` [PATCH v2 25/35] nds32: Build infrastructure Greentime Hu 2017-11-27 12:28 ` Greentime Hu 2017-11-27 14:21 ` Arnd Bergmann 2017-11-29 8:39 ` Greentime Hu 2017-11-29 8:58 ` Arnd Bergmann 2017-11-29 9:10 ` Geert Uytterhoeven 2017-11-29 9:25 ` Arnd Bergmann 2017-11-29 11:39 ` Greentime Hu 2017-11-29 11:57 ` Arnd Bergmann 2017-11-29 14:10 ` Greentime Hu 2017-11-29 20:27 ` Arnd Bergmann 2017-11-30 5:48 ` Greentime Hu 2017-11-30 7:52 ` Geert Uytterhoeven 2017-11-30 7:52 ` Geert Uytterhoeven 2017-11-30 9:29 ` Greentime Hu 2017-11-30 9:30 ` Arnd Bergmann 2017-11-30 9:30 ` Arnd Bergmann 2017-11-30 10:01 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 26/35] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller Greentime Hu 2017-11-27 12:28 ` Greentime Hu 2017-11-28 14:05 ` Rob Herring 2017-11-27 12:28 ` [PATCH v2 27/35] irqchip: Andestech Internal Vector Interrupt Controller driver Greentime Hu 2017-11-28 9:37 ` Marc Zyngier 2017-11-28 9:37 ` Marc Zyngier 2017-11-29 15:23 ` Greentime Hu 2017-11-29 15:23 ` Greentime Hu 2017-11-30 10:57 ` Marc Zyngier 2017-11-27 12:28 ` [PATCH v2 28/35] MAINTAINERS: Add nds32 Greentime Hu 2017-11-27 12:28 ` [PATCH v2 29/35] dt-bindings: nds32 CPU Bindings Greentime Hu 2017-11-27 13:42 ` Mark Rutland 2017-11-28 3:18 ` Greentime Hu 2017-11-28 3:18 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 30/35] net: faraday add nds32 support Greentime Hu 2017-11-27 14:15 ` Arnd Bergmann 2017-11-28 2:55 ` Greentime Hu 2017-11-28 2:55 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 31/35] earlycon: add reg-offset to physical address before mapping Greentime Hu 2017-11-28 14:25 ` Greg KH 2017-11-29 5:40 ` Greentime Hu 2017-11-27 12:28 ` [PATCH v2 32/35] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU Greentime Hu 2017-11-27 14:14 ` Arnd Bergmann 2017-11-27 12:28 ` [PATCH v2 33/35] clocksource/drivers/atcpit100: Add andestech atcpit100 timer Greentime Hu 2017-12-01 12:30 ` Linus Walleij 2017-12-01 12:30 ` Linus Walleij 2017-12-07 8:44 ` Daniel Lezcano 2017-11-27 12:28 ` [PATCH v2 34/35] clocksource/drivers/Kconfig: Support " Greentime Hu 2017-11-27 14:11 ` Arnd Bergmann 2017-11-28 2:53 ` Greentime Hu 2017-11-28 2:53 ` Greentime Hu 2017-12-07 8:40 ` Daniel Lezcano 2017-12-07 8:39 ` Daniel Lezcano 2017-12-07 8:39 ` Daniel Lezcano 2017-11-27 12:28 ` [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc Greentime Hu 2017-12-01 12:19 ` Linus Walleij 2017-12-01 12:19 ` Linus Walleij 2017-12-04 1:07 ` 陳建志 2017-12-04 1:07 ` 陳建志
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