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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area
Date: Fri, 30 Jul 2021 15:35:51 +0530	[thread overview]
Message-ID: <576279c5-9f7a-7af1-e5c7-776816e5b378@arm.com> (raw)
In-Reply-To: <20210728135217.591173-4-suzuki.poulose@arm.com>



On 7/28/21 7:22 PM, Suzuki K Poulose wrote:
> Refactor the helper to pad a given AUX buffer area to allow
> "filling" ignore packets, without moving any handle pointers.
> This will be useful in working around errata, where we may
> have to fill the buffer after a session.
> 
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-trbe.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index a0168ad204b3..0af644331b99 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -228,12 +228,18 @@ static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
>   * consumed from the user space. The enabled TRBE buffer area is a moving subset of
>   * the allocated perf auxiliary buffer.
>   */
> +
> +static void __trbe_pad_buf(struct trbe_buf *buf, u64 offset, int len)
> +{
> +	memset((void *)buf->trbe_base + offset, ETE_IGNORE_PACKET, len);
> +}
> +
>  static void trbe_pad_buf(struct perf_output_handle *handle, int len)
>  {
>  	struct trbe_buf *buf = etm_perf_sink_config(handle);
>  	u64 head = PERF_IDX2OFF(handle->head, buf);
>  
> -	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> +	__trbe_pad_buf(buf, head, len);
>  	if (!buf->snapshot)
>  		perf_aux_output_skip(handle, len);
>  }
> 

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area
Date: Fri, 30 Jul 2021 15:35:51 +0530	[thread overview]
Message-ID: <576279c5-9f7a-7af1-e5c7-776816e5b378@arm.com> (raw)
In-Reply-To: <20210728135217.591173-4-suzuki.poulose@arm.com>



On 7/28/21 7:22 PM, Suzuki K Poulose wrote:
> Refactor the helper to pad a given AUX buffer area to allow
> "filling" ignore packets, without moving any handle pointers.
> This will be useful in working around errata, where we may
> have to fill the buffer after a session.
> 
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-trbe.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index a0168ad204b3..0af644331b99 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -228,12 +228,18 @@ static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
>   * consumed from the user space. The enabled TRBE buffer area is a moving subset of
>   * the allocated perf auxiliary buffer.
>   */
> +
> +static void __trbe_pad_buf(struct trbe_buf *buf, u64 offset, int len)
> +{
> +	memset((void *)buf->trbe_base + offset, ETE_IGNORE_PACKET, len);
> +}
> +
>  static void trbe_pad_buf(struct perf_output_handle *handle, int len)
>  {
>  	struct trbe_buf *buf = etm_perf_sink_config(handle);
>  	u64 head = PERF_IDX2OFF(handle->head, buf);
>  
> -	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> +	__trbe_pad_buf(buf, head, len);
>  	if (!buf->snapshot)
>  		perf_aux_output_skip(handle, len);
>  }
> 

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

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  reply	other threads:[~2021-07-30 10:05 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-02  6:43   ` Anshuman Khandual
2021-08-02  6:43     ` Anshuman Khandual
2021-09-07  9:04     ` Suzuki K Poulose
2021-09-07  9:04       ` Suzuki K Poulose
2021-09-09  2:55       ` Anshuman Khandual
2021-09-09  2:55         ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 10:01   ` Anshuman Khandual
2021-07-30 10:01     ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 10:05   ` Anshuman Khandual [this message]
2021-07-30 10:05     ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 10:53   ` Anshuman Khandual
2021-07-30 10:53     ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 11:02   ` Anshuman Khandual
2021-07-30 11:02     ` Anshuman Khandual
2021-07-30 14:29     ` Suzuki K Poulose
2021-07-30 14:29       ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 11:26   ` Anshuman Khandual
2021-07-30 11:26     ` Anshuman Khandual
2021-07-30 14:31     ` Suzuki K Poulose
2021-07-30 14:31       ` Suzuki K Poulose
2021-08-02 11:21   ` Catalin Marinas
2021-08-02 11:21     ` Catalin Marinas
2021-08-02 11:21   ` Catalin Marinas
2021-08-02 11:21     ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-02  7:44   ` Anshuman Khandual
2021-08-02  7:44     ` Anshuman Khandual
2021-08-02 11:22   ` Catalin Marinas
2021-08-02 11:22     ` Catalin Marinas
2021-08-06 12:44   ` Linu Cherian
2021-08-06 12:44     ` Linu Cherian
2021-09-07  9:10     ` Suzuki K Poulose
2021-09-07  9:10       ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-03 10:25   ` Anshuman Khandual
2021-08-03 10:25     ` Anshuman Khandual
2021-09-07  9:58     ` Suzuki K Poulose
2021-09-07  9:58       ` Suzuki K Poulose
2021-09-09  4:21       ` Anshuman Khandual
2021-09-09  4:21         ` Anshuman Khandual
2021-09-09  8:37         ` Suzuki K Poulose
2021-09-09  8:37           ` Suzuki K Poulose
2021-08-06 16:09   ` Linu Cherian
2021-08-06 16:09     ` Linu Cherian
2021-09-07  9:18     ` Suzuki K Poulose
2021-09-07  9:18       ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-02  9:34   ` Anshuman Khandual
2021-08-02  9:34     ` Anshuman Khandual
2021-08-02 11:24   ` Catalin Marinas
2021-08-02 11:24     ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-29  9:55   ` Marc Zyngier
2021-07-29  9:55     ` Marc Zyngier
2021-07-29 10:41     ` Suzuki K Poulose
2021-07-29 10:41       ` Suzuki K Poulose
2021-08-02  9:12       ` Anshuman Khandual
2021-08-02  9:12         ` Anshuman Khandual
2021-08-02  9:35         ` Marc Zyngier
2021-08-02  9:35           ` Marc Zyngier
2021-08-03  3:51           ` Anshuman Khandual
2021-08-03  3:51             ` Anshuman Khandual
2021-09-08 13:39             ` Suzuki K Poulose
2021-09-08 13:39               ` Suzuki K Poulose
2021-08-02 11:27   ` Catalin Marinas
2021-08-02 11:27     ` Catalin Marinas

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