Fwd: Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"

Fwd: Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"

[Major A]

Hi Michal,

The link I sent discusses boards that are externally identical but still 
different, even though they are all labeled Rev1.1.  My understanding is 
that there are differences between boards other than the SODIMM issue 
(from Rev1.0 to Rev1.1).  Don't you have a reasonably new board (I guess 
anything with a 2019 build date should do to test the file that you sent 
me?  I'm pretty sure you only tested it on older boards (still Rev1.1, 
but older).

Cheers,

   Andr?s


On 05/05/2020 09:58, Michal Simek wrote:
> Hi,
> 
> yes there are new sodimms for sure that's why there is separate folder
> for this board revision.
> You can try to generate psu_init for 1.1 from vivado and then ddr
> configuration should be right.
> You can also use psu_init and run memory test on the top to see if ddr
> is configured properly.
> 
> Thanks,
> Michal
> 
> On 05. 05. 20 9:43, Major A wrote:
>> Hi Michal,
>>
>> I appreciate that, thanks for your help.? I mentioned this earlier but
>> never got a reply: can this have something to do with
>>
>>
>> https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/Booting-ZCU-102-from-SD-Card/td-p/926649
>>
>>
>> by any chance?
>>
>> Cheers,
>>
>>  ? Andr?s
>>
>>
>> On 05/05/2020 08:14, Michal Simek wrote:
>>> On 04. 05. 20 16:41, Major A wrote:
>>>> Dear Michal,
>>>>
>>>> There's no output on the console whatsoever.? I tried booting off SD
>>>> directly, and also via JTAG and your script.
>>>
>>> I am out of ideas what can be wrong. It is just working on our revision
>>> 1.1. I can only recommend you to debug it step by step and see where you
>>> end and what can be wrong.
>>> I can imagine that your zcu102 can have older memory module but it is
>>> unlikely if it is new. Or something else is broken there.
>>>
>>> Just keep in your mind that SPL is not supported official recommend boot
>>> flow and it is community driven first stage bootloader.
>>> I can help with brainstorming but you need to debug it self to find out
>>> where the problem is.
>>>
>>> Thanks,
>>> Michal
>>>
> 

Fwd: Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"

[Major A]

Hi Michal,

> can you please try these files in SD boot mode?

Done, here are two logs, both in SD boot mode.

First, log.sd is with SD card inserted (with the image files that 
apparently refuse to work other than the early UART message).

The other file, log.no-sd, is with no card inserted.

Cheers,

    Andr?s

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****** Xilinx System Debugger (XSDB) v2019.2
  **** Build date : Nov  6 2019-22:12:26
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


xsdb% cd
xsdb% cd ../../home/u-boot
xsdb% pwd
C:/home/u-boot
xsdb% source script
attempting to launch hw_server

****** Xilinx hw_server v2019.2
  **** Build date : Nov  6 2019 at 22:12:23
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application



****** Xilinx hw_server v2019.2

  **** Build date : Nov  6 2019 at 22:12:23

    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.



INFO: hw_server application started

INFO: Use Ctrl-C to exit hw_server application




INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121



Downloading Program -- C:/home/u-boot/pmufw.elf
        section, .vectors.reset: 0xffdc0000 - 0xffdc0007
        section, .vectors.sw_exception: 0xffdc0008 - 0xffdc000f
        section, .vectors.interrupt: 0xffdc0010 - 0xffdc0017
        section, .vectors.hw_exception: 0xffdc0020 - 0xffdc0027
        section, .text: 0xffdc0050 - 0xffdd108b
        section, .rodata: 0xffdd108c - 0xffdd31a3
        section, .data: 0xffdd31a4 - 0xffdd749b
        section, .sdata2: 0xffdd749c - 0xffdd749f
        section, .sdata: 0xffdd74a0 - 0xffdd749f
        section, .sbss: 0xffdd74a0 - 0xffdd749f
        section, .bss: 0xffdd74a0 - 0xffddb4cb
        section, .srdata: 0xffddb4cc - 0xffddbdef
        section, .stack: 0xffddbdf0 - 0xffddcdef
        section, .xpbr_serv_ext_tbl: 0xffddf6e0 - 0xffddfadf
100%    0MB   0.2MB/s  00:00
Setting PC to Program Start Address 0xffdd02a0
Successfully downloaded C:/home/u-boot/pmufw.elf
Info: MicroBlaze PMU (target 13) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (External Debug Request)
100%    0MB   0.2MB/s  00:00
Successfully downloaded C:/home/u-boot/spl/u-boot-spl-dtb.bin
Info: Cortex-A53 #0 (target 9) Stopped at 0xfffcc484 (Breakpoint)
udelay() at lib/time.c: 178
178: couldn't open "<u-boot build path>/lib/time.c": no such file or directory
Info: Breakpoint 0 status:
   target 9: {Address: 0xfffcc484 Type: Hardware}
xsdb% Info: Cortex-A53 #0 (target 9) Stopped at 0xfffcc484 (Breakpoint)
178: couldn't open "<u-boot build path>/lib/time.c": no such file or directory
xsdb%