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From: Leonardo Bras <leobras.c@gmail.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Frank Rowand <frowand.list@gmail.com>,
	Alexey Kardashevskiy <aik@ozlabs.ru>,
	devicetree@vger.kernel.org,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	PCI <linux-pci@vger.kernel.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH 1/1] of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses
Date: Wed, 21 Apr 2021 11:14:25 -0300	[thread overview]
Message-ID: <5da23b1199c897b464c7bf7027ac50057d1cb5b6.camel@gmail.com> (raw)
In-Reply-To: <CAL_JsqJXKVUFh9KrJjobn-jE-PFKN0w-V_i3qkfBrpTah4g8Xw@mail.gmail.com>

On Tue, 2021-04-20 at 17:34 -0500, Rob Herring wrote:
> > [...]
> > I think the point here is bus resources not getting the MEM_64 flag,
> > but device resources getting it correctly. Is that supposed to happen?
> 
> I experimented with this on Arm with qemu and it seems fine there too.
> Looks like the BARs are first read and will have bit 2 set by default
> (or hardwired?). Now I'm just wondering why powerpc needs the code it
> has...
> 
> Anyways, I'll apply the patch.
> 
> Rob

Thanks Rob!



WARNING: multiple messages have this Message-ID (diff)
From: Leonardo Bras <leobras.c@gmail.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, Alexey Kardashevskiy <aik@ozlabs.ru>,
	Frank Rowand <frowand.list@gmail.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	PCI <linux-pci@vger.kernel.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH 1/1] of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses
Date: Wed, 21 Apr 2021 11:14:25 -0300	[thread overview]
Message-ID: <5da23b1199c897b464c7bf7027ac50057d1cb5b6.camel@gmail.com> (raw)
In-Reply-To: <CAL_JsqJXKVUFh9KrJjobn-jE-PFKN0w-V_i3qkfBrpTah4g8Xw@mail.gmail.com>

On Tue, 2021-04-20 at 17:34 -0500, Rob Herring wrote:
> > [...]
> > I think the point here is bus resources not getting the MEM_64 flag,
> > but device resources getting it correctly. Is that supposed to happen?
> 
> I experimented with this on Arm with qemu and it seems fine there too.
> Looks like the BARs are first read and will have bit 2 set by default
> (or hardwired?). Now I'm just wondering why powerpc needs the code it
> has...
> 
> Anyways, I'll apply the patch.
> 
> Rob

Thanks Rob!



  reply	other threads:[~2021-04-21 14:14 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-15 18:00 [PATCH 1/1] of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses Leonardo Bras
2021-04-15 18:59 ` Rob Herring
2021-04-15 18:59   ` Rob Herring
2021-04-16 20:57   ` Leonardo Bras
2021-04-16 20:57     ` Leonardo Bras
2021-04-19 15:44     ` Rob Herring
2021-04-19 15:44       ` Rob Herring
2021-04-20  0:35       ` Leonardo Bras
2021-04-20  0:35         ` Leonardo Bras
2021-04-20  1:39         ` Rob Herring
2021-04-20  1:39           ` Rob Herring
2021-04-20  2:02           ` Leonardo Bras
2021-04-20  2:02             ` Leonardo Bras
2021-04-20 22:34             ` Rob Herring
2021-04-20 22:34               ` Rob Herring
2021-04-21 14:14               ` Leonardo Bras [this message]
2021-04-21 14:14                 ` Leonardo Bras
2021-04-16 21:27   ` Leonardo Bras
2021-04-16 21:27     ` Leonardo Bras
2021-06-09 18:50   ` Bjorn Helgaas
2021-06-09 18:50     ` Bjorn Helgaas
2021-04-21 12:51 ` Rob Herring

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