* [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges
@ 2021-09-10 11:33 Pali Rohár
2021-09-20 5:44 ` Stefan Roese
2021-09-24 2:41 ` Tom Rini
0 siblings, 2 replies; 3+ messages in thread
From: Pali Rohár @ 2021-09-10 11:33 UTC (permalink / raw)
To: Simon Glass, Stefan Roese, Phil Sutter; +Cc: u-boot
Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved
and should be zero. So do not set them to non-zero value.
Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers
contain information if 64-bit memory addressing is supported. So preserve
this information when overwriting these registers.
Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information
if 32-bit io addressing is supported. So preserve this information and do
not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and
PCI_IO_LIMIT_UPPER16 registers) when it is unsupported.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/pci_auto.c | 39 +++++++++++++++++++++++++++++----------
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index b128a05dd380..7b6e629cae70 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
+ u8 io_32;
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
@@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+ dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
+ io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Configure bus number registers */
dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
@@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
* I/O space
*/
dm_pci_write_config16(dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
+ ((pci_mem->bus_lower & 0xfff00000) >> 16) &
+ PCI_MEMORY_RANGE_MASK);
cmdstat |= PCI_COMMAND_MEMORY;
}
@@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
* I/O space
*/
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
+ PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
@@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
- dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
- dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
+ prefechable_64);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
+ prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
@@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+ (((pci_io->bus_lower & 0x0000f000) >> 8) &
+ PCI_IO_RANGE_MASK) | io_32);
+ if (io_32 == PCI_IO_RANGE_TYPE_32)
+ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
@@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_mem, 0x100000);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
+ ((pci_mem->bus_lower - 1) >> 16) &
+ PCI_MEMORY_RANGE_MASK);
}
if (pci_prefetch) {
@@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_prefetch, 0x100000);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
+ (((pci_prefetch->bus_lower - 1) >> 16) &
+ PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
@@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
}
if (pci_io) {
+ u8 io_32;
+
+ dm_pci_read_config8(dev, PCI_IO_LIMIT,
+ &io_32);
+ io_32 &= PCI_IO_RANGE_TYPE_MASK;
+
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+ ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
+ PCI_IO_RANGE_MASK) | io_32);
+ if (io_32 == PCI_IO_RANGE_TYPE_32)
+ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges
2021-09-10 11:33 [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges Pali Rohár
@ 2021-09-20 5:44 ` Stefan Roese
2021-09-24 2:41 ` Tom Rini
1 sibling, 0 replies; 3+ messages in thread
From: Stefan Roese @ 2021-09-20 5:44 UTC (permalink / raw)
To: Pali Rohár, Simon Glass, Phil Sutter; +Cc: u-boot, Bin Meng
Added Bin to cc.
On 10.09.21 13:33, Pali Rohár wrote:
> Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved
> and should be zero. So do not set them to non-zero value.
>
> Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers
> contain information if 64-bit memory addressing is supported. So preserve
> this information when overwriting these registers.
>
> Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information
> if 32-bit io addressing is supported. So preserve this information and do
> not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and
> PCI_IO_LIMIT_UPPER16 registers) when it is unsupported.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
> ---
> drivers/pci/pci_auto.c | 39 +++++++++++++++++++++++++++++----------
> 1 file changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
> index b128a05dd380..7b6e629cae70 100644
> --- a/drivers/pci/pci_auto.c
> +++ b/drivers/pci/pci_auto.c
> @@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
> struct pci_region *pci_prefetch;
> struct pci_region *pci_io;
> u16 cmdstat, prefechable_64;
> + u8 io_32;
> struct udevice *ctlr = pci_get_controller(dev);
> struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
>
> @@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
> dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
> dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
> prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
> + dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
> + io_32 &= PCI_IO_RANGE_TYPE_MASK;
>
> /* Configure bus number registers */
> dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
> @@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
> * I/O space
> */
> dm_pci_write_config16(dev, PCI_MEMORY_BASE,
> - (pci_mem->bus_lower & 0xfff00000) >> 16);
> + ((pci_mem->bus_lower & 0xfff00000) >> 16) &
> + PCI_MEMORY_RANGE_MASK);
>
> cmdstat |= PCI_COMMAND_MEMORY;
> }
> @@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
> * I/O space
> */
> dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
> - (pci_prefetch->bus_lower & 0xfff00000) >> 16);
> + (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
> + PCI_PREF_RANGE_MASK) | prefechable_64);
> if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
> #ifdef CONFIG_SYS_PCI_64BIT
> dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
> @@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
> cmdstat |= PCI_COMMAND_MEMORY;
> } else {
> /* We don't support prefetchable memory for now, so disable */
> - dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
> - dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
> + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
> + prefechable_64);
> + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
> + prefechable_64);
> if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
> dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
> dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
> @@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
> pciauto_region_align(pci_io, 0x1000);
>
> dm_pci_write_config8(dev, PCI_IO_BASE,
> - (pci_io->bus_lower & 0x0000f000) >> 8);
> - dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
> + (((pci_io->bus_lower & 0x0000f000) >> 8) &
> + PCI_IO_RANGE_MASK) | io_32);
> + if (io_32 == PCI_IO_RANGE_TYPE_32)
> + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
> (pci_io->bus_lower & 0xffff0000) >> 16);
>
> cmdstat |= PCI_COMMAND_IO;
> @@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
> pciauto_region_align(pci_mem, 0x100000);
>
> dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
> - (pci_mem->bus_lower - 1) >> 16);
> + ((pci_mem->bus_lower - 1) >> 16) &
> + PCI_MEMORY_RANGE_MASK);
> }
>
> if (pci_prefetch) {
> @@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
> pciauto_region_align(pci_prefetch, 0x100000);
>
> dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
> - (pci_prefetch->bus_lower - 1) >> 16);
> + (((pci_prefetch->bus_lower - 1) >> 16) &
> + PCI_PREF_RANGE_MASK) | prefechable_64);
> if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
> #ifdef CONFIG_SYS_PCI_64BIT
> dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
> @@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
> }
>
> if (pci_io) {
> + u8 io_32;
> +
> + dm_pci_read_config8(dev, PCI_IO_LIMIT,
> + &io_32);
> + io_32 &= PCI_IO_RANGE_TYPE_MASK;
> +
> /* Round I/O allocator to 4KB boundary */
> pciauto_region_align(pci_io, 0x1000);
>
> dm_pci_write_config8(dev, PCI_IO_LIMIT,
> - ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
> - dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
> + ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
> + PCI_IO_RANGE_MASK) | io_32);
> + if (io_32 == PCI_IO_RANGE_TYPE_32)
> + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
> ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
> }
> }
>
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges
2021-09-10 11:33 [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges Pali Rohár
2021-09-20 5:44 ` Stefan Roese
@ 2021-09-24 2:41 ` Tom Rini
1 sibling, 0 replies; 3+ messages in thread
From: Tom Rini @ 2021-09-24 2:41 UTC (permalink / raw)
To: Pali Rohár; +Cc: Simon Glass, Stefan Roese, Phil Sutter, u-boot
[-- Attachment #1: Type: text/plain, Size: 845 bytes --]
On Fri, Sep 10, 2021 at 01:33:35PM +0200, Pali Rohár wrote:
> Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved
> and should be zero. So do not set them to non-zero value.
>
> Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers
> contain information if 64-bit memory addressing is supported. So preserve
> this information when overwriting these registers.
>
> Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information
> if 32-bit io addressing is supported. So preserve this information and do
> not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and
> PCI_IO_LIMIT_UPPER16 registers) when it is unsupported.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Reviewed-by: Stefan Roese <sr@denx.de>
Applied to u-boot/next, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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2021-09-10 11:33 [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges Pali Rohár
2021-09-20 5:44 ` Stefan Roese
2021-09-24 2:41 ` Tom Rini
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