From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski@linaro.org>,
<krzysztof.kozlowski+dt@linaro.org>, <vladimir.oltean@nxp.com>,
<grygorii.strashko@ti.com>, <vigneshr@ti.com>, <nsekhar@ti.com>,
<netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kishon@ti.com>,
<s-vadapalli@ti.com>
Subject: Re: [PATCH 6/8] net: ethernet: ti: am65-cpsw: Add support for SGMII mode for J7200 CPSW5G
Date: Thu, 15 Sep 2022 15:05:28 +0530 [thread overview]
Message-ID: <7a5dd6b3-389f-13a2-7c96-8e97e0ab4e55@ti.com> (raw)
In-Reply-To: <YyH2zCscSV5KQtZ9@shell.armlinux.org.uk>
Hello Russell,
On 14/09/22 21:14, Russell King (Oracle) wrote:
> On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote:
>> Add support for SGMII mode in both fixed-link MAC2MAC master mode and
>> MAC2PHY modes for CPSW5G ports.
>>
>> Add SGMII mode to the list of extra_modes in j7200_cpswxg_pdata.
>>
>> The MAC2PHY mode has been tested in fixed-link mode using a bootstrapped
>> PHY. The MAC2MAC mode has been tested by a customer with J7200 SoC on
>> their device.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>> drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++++++++++++++---
>> 1 file changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> index 1739c389af20..3f40178436ff 100644
>> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> @@ -75,7 +75,15 @@
>> #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
>>
>> #define AM65_CPSW_SGMII_CONTROL_REG 0x010
>> +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
>
> This doesn't seem to be used in this patch, should it be part of some
> other patch in the series?
>
>> #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
>> +#define AM65_CPSW_SGMII_CONTROL_MASTER_MODE BIT(5)
>
> Ditto.
>
>> +
>> +#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0))
>> +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12)
>> +#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11)
>> +#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10)
>> +#define MAC2PHY_MR_ADV_ABILITY BIT(0)
>
> Most of the above don't seem to be used, and the only one that seems to
> be used is used in a variable declaration where the variable isn't used,
> and thus us also unused.
>
>>
>> #define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
>> #define AM65_CPSW_CTL_P0_ENABLE BIT(2)
>> @@ -1493,6 +1501,7 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
>> struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
>> phylink_config);
>> struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
>> + u32 mr_adv_ability = MAC2MAC_MR_ADV_ABILITY_BASE;
>
> This doesn't seem to be used; should it be part of a different patch?
>
> I get the impression that most of this patch should be elsewhere in this
> series.
Thank you for pointing it out. These should have been a part of the
previous patch [PATCH 5/8]. Sorry for the confusion. I will fix this in
the v2 series.
Regards,
Siddharth.
WARNING: multiple messages have this Message-ID (diff)
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski@linaro.org>,
<krzysztof.kozlowski+dt@linaro.org>, <vladimir.oltean@nxp.com>,
<grygorii.strashko@ti.com>, <vigneshr@ti.com>, <nsekhar@ti.com>,
<netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kishon@ti.com>,
<s-vadapalli@ti.com>
Subject: Re: [PATCH 6/8] net: ethernet: ti: am65-cpsw: Add support for SGMII mode for J7200 CPSW5G
Date: Thu, 15 Sep 2022 15:05:28 +0530 [thread overview]
Message-ID: <7a5dd6b3-389f-13a2-7c96-8e97e0ab4e55@ti.com> (raw)
In-Reply-To: <YyH2zCscSV5KQtZ9@shell.armlinux.org.uk>
Hello Russell,
On 14/09/22 21:14, Russell King (Oracle) wrote:
> On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote:
>> Add support for SGMII mode in both fixed-link MAC2MAC master mode and
>> MAC2PHY modes for CPSW5G ports.
>>
>> Add SGMII mode to the list of extra_modes in j7200_cpswxg_pdata.
>>
>> The MAC2PHY mode has been tested in fixed-link mode using a bootstrapped
>> PHY. The MAC2MAC mode has been tested by a customer with J7200 SoC on
>> their device.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>> drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++++++++++++++---
>> 1 file changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> index 1739c389af20..3f40178436ff 100644
>> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> @@ -75,7 +75,15 @@
>> #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
>>
>> #define AM65_CPSW_SGMII_CONTROL_REG 0x010
>> +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
>
> This doesn't seem to be used in this patch, should it be part of some
> other patch in the series?
>
>> #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
>> +#define AM65_CPSW_SGMII_CONTROL_MASTER_MODE BIT(5)
>
> Ditto.
>
>> +
>> +#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0))
>> +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12)
>> +#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11)
>> +#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10)
>> +#define MAC2PHY_MR_ADV_ABILITY BIT(0)
>
> Most of the above don't seem to be used, and the only one that seems to
> be used is used in a variable declaration where the variable isn't used,
> and thus us also unused.
>
>>
>> #define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
>> #define AM65_CPSW_CTL_P0_ENABLE BIT(2)
>> @@ -1493,6 +1501,7 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
>> struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
>> phylink_config);
>> struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
>> + u32 mr_adv_ability = MAC2MAC_MR_ADV_ABILITY_BASE;
>
> This doesn't seem to be used; should it be part of a different patch?
>
> I get the impression that most of this patch should be elsewhere in this
> series.
Thank you for pointing it out. These should have been a part of the
previous patch [PATCH 5/8]. Sorry for the confusion. I will fix this in
the v2 series.
Regards,
Siddharth.
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next prev parent reply other threads:[~2022-09-15 9:36 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 9:50 [PATCH 0/8] Add support for J721e CPSW9G and SGMII mode Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 9:50 ` [PATCH 1/8] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J721e CPSW9G Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 16:20 ` Rob Herring
2022-09-14 16:20 ` Rob Herring
2022-09-15 7:28 ` Siddharth Vadapalli
2022-09-15 7:28 ` Siddharth Vadapalli
2022-09-14 16:23 ` Rob Herring
2022-09-14 16:23 ` Rob Herring
2022-09-15 7:40 ` Siddharth Vadapalli
2022-09-15 7:40 ` Siddharth Vadapalli
2022-09-14 9:50 ` [PATCH 2/8] net: ethernet: ti: am65-cpsw: Add support for SERDES configuration Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 15:37 ` Russell King (Oracle)
2022-09-14 15:37 ` Russell King (Oracle)
2022-09-15 8:36 ` Siddharth Vadapalli
2022-09-15 8:36 ` Siddharth Vadapalli
2022-09-14 9:50 ` [PATCH 3/8] net: ethernet: ti: am65-cpsw: Add mac control function Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 15:53 ` Russell King (Oracle)
2022-09-14 15:53 ` Russell King (Oracle)
2022-09-14 9:50 ` [PATCH 4/8] net: ethernet: ti: am65-cpsw: Add mac enable link function Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 15:54 ` Russell King (Oracle)
2022-09-14 15:54 ` Russell King (Oracle)
2022-09-14 9:50 ` [PATCH 5/8] net: ethernet: ti: am65-cpsw: Add support for fixed-link configuration Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 15:41 ` Russell King (Oracle)
2022-09-14 15:41 ` Russell King (Oracle)
2022-09-15 8:59 ` Siddharth Vadapalli
2022-09-15 8:59 ` Siddharth Vadapalli
2022-09-14 16:09 ` Russell King (Oracle)
2022-09-14 16:09 ` Russell King (Oracle)
2022-09-15 9:28 ` Siddharth Vadapalli
2022-09-15 9:28 ` Siddharth Vadapalli
2022-09-15 10:07 ` Russell King (Oracle)
2022-09-15 10:07 ` Russell King (Oracle)
2022-09-16 4:54 ` Siddharth Vadapalli
2022-09-16 4:54 ` Siddharth Vadapalli
2022-09-16 7:20 ` Russell King (Oracle)
2022-09-16 7:20 ` Russell King (Oracle)
2022-09-16 9:03 ` Siddharth Vadapalli
2022-09-16 9:03 ` Siddharth Vadapalli
2022-09-16 9:14 ` Russell King (Oracle)
2022-09-16 9:14 ` Russell King (Oracle)
2022-09-16 9:55 ` Siddharth Vadapalli
2022-09-16 9:55 ` Siddharth Vadapalli
2022-09-14 9:50 ` [PATCH 6/8] net: ethernet: ti: am65-cpsw: Add support for SGMII mode for J7200 CPSW5G Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 15:44 ` Russell King (Oracle)
2022-09-14 15:44 ` Russell King (Oracle)
2022-09-15 9:35 ` Siddharth Vadapalli [this message]
2022-09-15 9:35 ` Siddharth Vadapalli
2022-09-14 16:04 ` Russell King (Oracle)
2022-09-14 16:04 ` Russell King (Oracle)
2022-09-15 9:40 ` Siddharth Vadapalli
2022-09-15 9:40 ` Siddharth Vadapalli
2022-09-14 9:50 ` [PATCH 7/8] net: ethernet: ti: am65-cpsw: Add support for J721e CPSW9G Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-14 9:50 ` [PATCH 8/8] net: ethernet: ti: am65-cpsw: Enable SGMII mode " Siddharth Vadapalli
2022-09-14 9:50 ` Siddharth Vadapalli
2022-09-16 9:57 ` [PATCH 0/8] Add support for J721e CPSW9G and SGMII mode Krzysztof Kozlowski
2022-09-16 9:57 ` Krzysztof Kozlowski
2022-09-16 10:07 ` Siddharth Vadapalli
2022-09-16 10:07 ` Siddharth Vadapalli
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