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From: Zhou Yanjie <zhouyanjie@wanyeetech.com>
To: Mark Brown <broonie@kernel.org>
Cc: tudor.ambarus@microchip.com, p.yadav@ti.com, michael@walle.cc,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
	linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, aidanmacdonald.0x0@gmail.com,
	tmn505@gmail.com, paul@crapouillou.net,
	dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com,
	rick.tyliu@ingenic.com, jinghui.liu@ingenic.com,
	sernia.zhou@foxmail.com, reimu@sudomaker.com
Subject: Re: [PATCH 3/3] SPI: Ingenic: Add SFC support for Ingenic SoCs.
Date: Sun, 24 Jul 2022 01:06:16 +0800	[thread overview]
Message-ID: <89d22457-8c62-e441-3bf4-2734ec2a45e1@wanyeetech.com> (raw)
In-Reply-To: <YtrukeLk9fInqQIL@sirena.org.uk>

Hi Mark,

On 2022/7/23 上午2:38, Mark Brown wrote:
> On Sat, Jul 23, 2022 at 12:48:30AM +0800, 周琰杰 (Zhou Yanjie) wrote:
>
> This looks mostly good, a few small issues though:
>
>> +++ b/drivers/spi/spi-ingenic-sfc.c
>> @@ -0,0 +1,662 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Ingenic SoCs SPI Flash Controller Driver
> Please make the entire comment a C++ one so things look more
> intentional.


I'm sorry, I didn't understand well what you meant :(
Could you please explain a little more detail?


>
>> +static irqreturn_t ingenic_sfc_irq_handler(int irq, void *data)
>> +{
>> +	struct ingenic_sfc *sfc = data;
>> +
>> +	writel(0x1f, sfc->base + SFC_REG_INTC);
>> +
>> +	complete(&sfc->completion);
>> +
>> +	return IRQ_HANDLED;
>> +}
> This doesn't pay any attention to any status registers in the chip so
> won't work if the interrupt is shared and won't notice any error reports
> from the device...


This interrupt is exclusively owned by SFC, do we still
need to perform the operation you said? I haven't done
these operations before because I want to minimize the
overhead and avoid affecting performance.


>
>> +static int ingenic_sfc_setup(struct spi_device *spi)
>> +{
>> +	struct ingenic_sfc *sfc = spi_controller_get_devdata(spi->master);
>> +	unsigned long rate;
>> +	int ret, val;
>> +
>> +	if (!spi->max_speed_hz)
>> +		return -EINVAL;
>> +
>> +	ret = clk_set_rate(sfc->clk, spi->max_speed_hz * 2);
>> +	if (ret)
>> +		return -EINVAL;
> The setup() operation should be safe for use on one device while another
> device is active.  It's not going to be a problem until there's a
> version of the IP with more than one chip select, but that could happen
> some time (and someone might decide to make a board using GPIO chip
> selects...) but this should really go into the data path.


Sure, I will change it in the next version.


>> +	ret = clk_prepare_enable(sfc->clk);
>> +	if (ret)
>> +		goto err_put_master;
> Nothing ever disables this clock.  It might also be nice to enable the
> clock only when the controller is in use, that bit is not super
> important though.


Sure, will add it.


>
>> +	ret = devm_request_irq(&pdev->dev, sfc->irq, ingenic_sfc_irq_handler, 0,
>> +			dev_name(&pdev->dev), sfc);
>> +	if (ret) {
>> +		dev_err(&pdev->dev, "Failed to request irq%d, ret = %d\n", sfc->irq, ret);
>> +		goto err_put_master;
>> +	}
> It's not safe to use devm here...


Sure, will fix it in the next version.


>
>> +	ret = devm_spi_register_controller(&pdev->dev, ctlr);
>> +	if (ret)
>> +		goto err_put_master;
> ...unregistering the controller may free the driver data structure and
> the interrupt handler uses it so we could attempt to use freed data in
> the window between the controller being unregistered and the interrupt
> being freed.


Sure.


Thanks and best regards!



WARNING: multiple messages have this Message-ID (diff)
From: Zhou Yanjie <zhouyanjie@wanyeetech.com>
To: Mark Brown <broonie@kernel.org>
Cc: tudor.ambarus@microchip.com, p.yadav@ti.com, michael@walle.cc,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
	linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, aidanmacdonald.0x0@gmail.com,
	tmn505@gmail.com, paul@crapouillou.net,
	dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com,
	rick.tyliu@ingenic.com, jinghui.liu@ingenic.com,
	sernia.zhou@foxmail.com, reimu@sudomaker.com
Subject: Re: [PATCH 3/3] SPI: Ingenic: Add SFC support for Ingenic SoCs.
Date: Sun, 24 Jul 2022 01:06:16 +0800	[thread overview]
Message-ID: <89d22457-8c62-e441-3bf4-2734ec2a45e1@wanyeetech.com> (raw)
In-Reply-To: <YtrukeLk9fInqQIL@sirena.org.uk>

Hi Mark,

On 2022/7/23 上午2:38, Mark Brown wrote:
> On Sat, Jul 23, 2022 at 12:48:30AM +0800, 周琰杰 (Zhou Yanjie) wrote:
>
> This looks mostly good, a few small issues though:
>
>> +++ b/drivers/spi/spi-ingenic-sfc.c
>> @@ -0,0 +1,662 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Ingenic SoCs SPI Flash Controller Driver
> Please make the entire comment a C++ one so things look more
> intentional.


I'm sorry, I didn't understand well what you meant :(
Could you please explain a little more detail?


>
>> +static irqreturn_t ingenic_sfc_irq_handler(int irq, void *data)
>> +{
>> +	struct ingenic_sfc *sfc = data;
>> +
>> +	writel(0x1f, sfc->base + SFC_REG_INTC);
>> +
>> +	complete(&sfc->completion);
>> +
>> +	return IRQ_HANDLED;
>> +}
> This doesn't pay any attention to any status registers in the chip so
> won't work if the interrupt is shared and won't notice any error reports
> from the device...


This interrupt is exclusively owned by SFC, do we still
need to perform the operation you said? I haven't done
these operations before because I want to minimize the
overhead and avoid affecting performance.


>
>> +static int ingenic_sfc_setup(struct spi_device *spi)
>> +{
>> +	struct ingenic_sfc *sfc = spi_controller_get_devdata(spi->master);
>> +	unsigned long rate;
>> +	int ret, val;
>> +
>> +	if (!spi->max_speed_hz)
>> +		return -EINVAL;
>> +
>> +	ret = clk_set_rate(sfc->clk, spi->max_speed_hz * 2);
>> +	if (ret)
>> +		return -EINVAL;
> The setup() operation should be safe for use on one device while another
> device is active.  It's not going to be a problem until there's a
> version of the IP with more than one chip select, but that could happen
> some time (and someone might decide to make a board using GPIO chip
> selects...) but this should really go into the data path.


Sure, I will change it in the next version.


>> +	ret = clk_prepare_enable(sfc->clk);
>> +	if (ret)
>> +		goto err_put_master;
> Nothing ever disables this clock.  It might also be nice to enable the
> clock only when the controller is in use, that bit is not super
> important though.


Sure, will add it.


>
>> +	ret = devm_request_irq(&pdev->dev, sfc->irq, ingenic_sfc_irq_handler, 0,
>> +			dev_name(&pdev->dev), sfc);
>> +	if (ret) {
>> +		dev_err(&pdev->dev, "Failed to request irq%d, ret = %d\n", sfc->irq, ret);
>> +		goto err_put_master;
>> +	}
> It's not safe to use devm here...


Sure, will fix it in the next version.


>
>> +	ret = devm_spi_register_controller(&pdev->dev, ctlr);
>> +	if (ret)
>> +		goto err_put_master;
> ...unregistering the controller may free the driver data structure and
> the interrupt handler uses it so we could attempt to use freed data in
> the window between the controller being unregistered and the interrupt
> being freed.


Sure.


Thanks and best regards!



______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2022-07-23 17:06 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-22 16:48 [PATCH 0/3] Add SFC support for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2022-07-22 16:48 ` 周琰杰 (Zhou Yanjie)
2022-07-22 16:48 ` [PATCH 1/3] mtd: spi-nor: Use the spi-mem poll status APIs 周琰杰 (Zhou Yanjie)
2022-07-22 16:48   ` 周琰杰 (Zhou Yanjie)
2022-07-23  8:30   ` Sergey Shtylyov
2022-07-23  8:30     ` Sergey Shtylyov
2022-07-22 16:48 ` [PATCH 2/3] dt-bindings: SPI: Add Ingenic SFC bindings 周琰杰 (Zhou Yanjie)
2022-07-22 16:48   ` 周琰杰 (Zhou Yanjie)
2022-07-22 17:46   ` Krzysztof Kozlowski
2022-07-22 17:46     ` Krzysztof Kozlowski
2022-07-23 16:50     ` Zhou Yanjie
2022-07-23 16:50       ` Zhou Yanjie
2022-07-23 17:43       ` Krzysztof Kozlowski
2022-07-23 17:43         ` Krzysztof Kozlowski
2022-07-23 18:47         ` Mike Yang
2022-07-23 18:47           ` Mike Yang
2022-07-23 19:27           ` Mark Brown
2022-07-23 19:27             ` Mark Brown
2022-07-23 20:07             ` Krzysztof Kozlowski
2022-07-23 20:07               ` Krzysztof Kozlowski
2022-07-23 20:49               ` Mike Yang
2022-07-23 20:49                 ` Mike Yang
2022-07-24 15:33                 ` Zhou Yanjie
2022-07-24 15:33                   ` Zhou Yanjie
2022-07-25 18:30                 ` Rob Herring
2022-07-25 18:30                   ` Rob Herring
2022-07-23 20:05           ` Krzysztof Kozlowski
2022-07-23 20:05             ` Krzysztof Kozlowski
2022-07-24 14:52             ` Zhou Yanjie
2022-07-24 14:52               ` Zhou Yanjie
2022-07-22 22:44   ` Rob Herring
2022-07-22 22:44     ` Rob Herring
2022-07-22 16:48 ` [PATCH 3/3] SPI: Ingenic: Add SFC support for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2022-07-22 16:48   ` 周琰杰 (Zhou Yanjie)
2022-07-22 18:07   ` Krzysztof Kozlowski
2022-07-22 18:07     ` Krzysztof Kozlowski
2022-07-23 16:53     ` Zhou Yanjie
2022-07-23 16:53       ` Zhou Yanjie
2022-07-22 18:38   ` Mark Brown
2022-07-22 18:38     ` Mark Brown
2022-07-23 17:06     ` Zhou Yanjie [this message]
2022-07-23 17:06       ` Zhou Yanjie
2022-07-23 19:32       ` Mark Brown
2022-07-23 19:32         ` Mark Brown
2022-07-24  1:24         ` Zhou Yanjie
2022-07-24  1:24           ` Zhou Yanjie
2022-07-22 20:03   ` Paul Cercueil
2022-07-22 20:03     ` Paul Cercueil
2022-07-23 17:26     ` Zhou Yanjie
2022-07-23 17:26       ` Zhou Yanjie
2022-07-23 20:24       ` Paul Cercueil
2022-07-23 20:24         ` Paul Cercueil
2022-07-24 15:29         ` Zhou Yanjie
2022-07-24 15:29           ` Zhou Yanjie
2022-07-23 15:15   ` Christophe JAILLET
2022-07-23 15:15     ` Christophe JAILLET
2022-07-23 15:15     ` Christophe JAILLET
2022-07-24  1:22     ` Zhou Yanjie
2022-07-24  1:22       ` Zhou Yanjie
2022-07-24  0:43   ` kernel test robot
2022-07-24  0:43     ` kernel test robot
2022-07-24  1:28     ` Vanessa Page
2022-07-24  1:28       ` Vanessa Page
2022-07-25 16:58     ` Vanessa Page
2022-07-23 14:47 ` [PATCH 0/3] " Tomasz Maciej Nowak
2022-07-23 14:47   ` Tomasz Maciej Nowak
2022-07-24  1:25   ` Zhou Yanjie
2022-07-24  1:25     ` Zhou Yanjie
2022-07-24  1:28     ` Vanessa Page
2022-07-24  1:28       ` Vanessa Page
2022-07-24  1:28     ` Vanessa Page
2022-07-24  1:28       ` Vanessa Page
2022-07-24  1:30     ` Vanessa Page
2022-07-24  1:30       ` Vanessa Page
2022-07-24  1:32       ` Vee Page
2022-07-24  1:32         ` Vee Page
2022-07-26  6:13         ` Vee Page
2022-07-26  6:13           ` Vee Page

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