* [PATCH v1 0/2] RISC-V: Populate mtval and stval
@ 2021-09-02 23:23 Alistair Francis
2021-09-02 23:23 ` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2021-09-02 23:23 ` [PATCH v1 2/2] target/riscv: Set mtval and stval support Alistair Francis
0 siblings, 2 replies; 11+ messages in thread
From: Alistair Francis @ 2021-09-02 23:23 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Populate mtval and stval when taking an illegal instruction exception if
the features are set for the CPU.
Alistair Francis (2):
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Set mtval and stval support
target/riscv/cpu.h | 6 +++++-
target/riscv/cpu.c | 6 +++++-
target/riscv/cpu_helper.c | 9 +++++++++
target/riscv/translate.c | 33 +++++++++++++++++++--------------
4 files changed, 38 insertions(+), 16 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
2021-09-02 23:23 [PATCH v1 0/2] RISC-V: Populate mtval and stval Alistair Francis
@ 2021-09-02 23:23 ` Alistair Francis
2021-09-03 17:04 ` Richard Henderson
2021-09-04 13:41 ` Bin Meng
2021-09-02 23:23 ` [PATCH v1 2/2] target/riscv: Set mtval and stval support Alistair Francis
1 sibling, 2 replies; 11+ messages in thread
From: Alistair Francis @ 2021-09-02 23:23 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers based on the CPU feature.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 ++++-
target/riscv/cpu_helper.c | 9 +++++++++
target/riscv/translate.c | 33 +++++++++++++++++++--------------
3 files changed, 32 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf1c899c00..6d41a16ae3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -77,7 +77,8 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_MISA
+ RISCV_FEATURE_MISA,
+ RISCV_FEATURE_MTVAL_INST,
};
#define PRIV_VERSION_1_10_0 0x00011000
@@ -130,6 +131,8 @@ struct CPURISCVState {
target_ulong frm;
target_ulong badaddr;
+ target_ulong bins;
+
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f..42edd71c1e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -967,6 +967,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
write_tval = true;
tval = env->badaddr;
break;
+ case RISCV_EXCP_ILLEGAL_INST:
+ if (riscv_feature(env, RISCV_FEATURE_MTVAL_INST)) {
+ /* The stval/mtval register can optionally also be used to
+ * return the faulting instruction bits on an illegal
+ * instruction exception.
+ */
+ tval = env->bins;
+ }
+ break;
default:
break;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e356fc6c46..4221d8e2d5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -173,8 +173,27 @@ static void lookup_and_goto_ptr(DisasContext *ctx)
}
}
+/*
+ * Wrappers for getting reg values.
+ *
+ * The $zero register does not have cpu_gpr[0] allocated -- we supply the
+ * constant zero as a source, and an uninitialized sink as destination.
+ *
+ * Further, we may provide an extension for word operations.
+ */
+static TCGv temp_new(DisasContext *ctx)
+{
+ assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
+ return ctx->temp[ctx->ntemp++] = tcg_temp_new();
+}
+
static void gen_exception_illegal(DisasContext *ctx)
{
+ TCGv tmp = temp_new(ctx);
+
+ tcg_gen_movi_tl(tmp, ctx->opcode);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));
+
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
}
@@ -195,20 +214,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
}
}
-/*
- * Wrappers for getting reg values.
- *
- * The $zero register does not have cpu_gpr[0] allocated -- we supply the
- * constant zero as a source, and an uninitialized sink as destination.
- *
- * Further, we may provide an extension for word operations.
- */
-static TCGv temp_new(DisasContext *ctx)
-{
- assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
- return ctx->temp[ctx->ntemp++] = tcg_temp_new();
-}
-
static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
{
TCGv t;
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 2/2] target/riscv: Set mtval and stval support
2021-09-02 23:23 [PATCH v1 0/2] RISC-V: Populate mtval and stval Alistair Francis
2021-09-02 23:23 ` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
@ 2021-09-02 23:23 ` Alistair Francis
2021-09-03 17:05 ` Richard Henderson
1 sibling, 1 reply; 11+ messages in thread
From: Alistair Francis @ 2021-09-02 23:23 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 6 +++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6d41a16ae3..64ebb593fb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -309,6 +309,7 @@ struct RISCVCPU {
bool mmu;
bool pmp;
bool epmp;
+ bool mtval_inst;
uint64_t resetvec;
} cfg;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579..8b77526c79 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -437,6 +437,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
}
+ if (cpu->cfg.mtval_inst) {
+ set_feature(env, RISCV_FEATURE_MTVAL_INST);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* If only XLEN is set for misa, then set misa from properties */
@@ -600,7 +604,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-
+ DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
2021-09-02 23:23 ` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
@ 2021-09-03 17:04 ` Richard Henderson
2021-09-04 13:41 ` Bin Meng
1 sibling, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2021-09-03 17:04 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: alistair.francis, bmeng.cn, palmer, alistair23
On 9/3/21 1:23 AM, Alistair Francis wrote:
> + target_ulong bins;
Surely uint32_t, at least until 64-bit insn width is required.
> + TCGv tmp = temp_new(ctx);
> +
> + tcg_gen_movi_tl(tmp, ctx->opcode);
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode),
cpu_env, offsetof(CPURISCVState, bins));
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
@ 2021-09-03 17:04 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2021-09-03 17:04 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: bmeng.cn, palmer, alistair.francis, alistair23
On 9/3/21 1:23 AM, Alistair Francis wrote:
> + target_ulong bins;
Surely uint32_t, at least until 64-bit insn width is required.
> + TCGv tmp = temp_new(ctx);
> +
> + tcg_gen_movi_tl(tmp, ctx->opcode);
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode),
cpu_env, offsetof(CPURISCVState, bins));
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support
2021-09-02 23:23 ` [PATCH v1 2/2] target/riscv: Set mtval and stval support Alistair Francis
@ 2021-09-03 17:05 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2021-09-03 17:05 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: alistair.francis, bmeng.cn, palmer, alistair23
On 9/3/21 1:23 AM, Alistair Francis wrote:
> + DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
Dash not underscore for the prop name, I think.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support
@ 2021-09-03 17:05 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2021-09-03 17:05 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: bmeng.cn, palmer, alistair.francis, alistair23
On 9/3/21 1:23 AM, Alistair Francis wrote:
> + DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
Dash not underscore for the prop name, I think.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support
2021-09-03 17:05 ` Richard Henderson
@ 2021-09-03 23:58 ` Bin Meng
-1 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2021-09-03 23:58 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis,
Alistair Francis, Palmer Dabbelt
On Sat, Sep 4, 2021 at 1:06 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/3/21 1:23 AM, Alistair Francis wrote:
> > + DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
>
> Dash not underscore for the prop name, I think.
>
But we also have "priv_spec" :)
The name "mtval_inst" sounds like only for M-mode. Maybe omitting 'm',
and just "tval"?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Set mtval and stval support
@ 2021-09-03 23:58 ` Bin Meng
0 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2021-09-03 23:58 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Palmer Dabbelt, Alistair Francis,
Alistair Francis
On Sat, Sep 4, 2021 at 1:06 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/3/21 1:23 AM, Alistair Francis wrote:
> > + DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
>
> Dash not underscore for the prop name, I think.
>
But we also have "priv_spec" :)
The name "mtval_inst" sounds like only for M-mode. Maybe omitting 'm',
and just "tval"?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
2021-09-02 23:23 ` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
@ 2021-09-04 13:41 ` Bin Meng
2021-09-04 13:41 ` Bin Meng
1 sibling, 0 replies; 11+ messages in thread
From: Bin Meng @ 2021-09-04 13:41 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, Sep 3, 2021 at 7:23 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The stval and mtval registers can optionally contain the faulting
> instruction on an illegal instruction exception. This patch adds support
> for setting the stval and mtval registers based on the CPU feature.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 5 ++++-
> target/riscv/cpu_helper.c | 9 +++++++++
> target/riscv/translate.c | 33 +++++++++++++++++++--------------
> 3 files changed, 32 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bf1c899c00..6d41a16ae3 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -77,7 +77,8 @@ enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> RISCV_FEATURE_EPMP,
> - RISCV_FEATURE_MISA
> + RISCV_FEATURE_MISA,
> + RISCV_FEATURE_MTVAL_INST,
> };
>
> #define PRIV_VERSION_1_10_0 0x00011000
> @@ -130,6 +131,8 @@ struct CPURISCVState {
> target_ulong frm;
>
> target_ulong badaddr;
> + target_ulong bins;
> +
> target_ulong guest_phys_fault_addr;
>
> target_ulong priv_ver;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 968cb8046f..42edd71c1e 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -967,6 +967,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> write_tval = true;
> tval = env->badaddr;
> break;
> + case RISCV_EXCP_ILLEGAL_INST:
> + if (riscv_feature(env, RISCV_FEATURE_MTVAL_INST)) {
> + /* The stval/mtval register can optionally also be used to
nits: incorrect multi-line comment format
> + * return the faulting instruction bits on an illegal
> + * instruction exception.
> + */
> + tval = env->bins;
> + }
> + break;
> default:
> break;
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e356fc6c46..4221d8e2d5 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -173,8 +173,27 @@ static void lookup_and_goto_ptr(DisasContext *ctx)
> }
> }
>
> +/*
> + * Wrappers for getting reg values.
> + *
> + * The $zero register does not have cpu_gpr[0] allocated -- we supply the
> + * constant zero as a source, and an uninitialized sink as destination.
> + *
> + * Further, we may provide an extension for word operations.
> + */
> +static TCGv temp_new(DisasContext *ctx)
> +{
> + assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
> + return ctx->temp[ctx->ntemp++] = tcg_temp_new();
> +}
> +
> static void gen_exception_illegal(DisasContext *ctx)
> {
> + TCGv tmp = temp_new(ctx);
> +
> + tcg_gen_movi_tl(tmp, ctx->opcode);
ctx->opcode is not initialized anywhere.
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));
> +
> generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> }
>
> @@ -195,20 +214,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> }
> }
>
> -/*
> - * Wrappers for getting reg values.
> - *
> - * The $zero register does not have cpu_gpr[0] allocated -- we supply the
> - * constant zero as a source, and an uninitialized sink as destination.
> - *
> - * Further, we may provide an extension for word operations.
> - */
> -static TCGv temp_new(DisasContext *ctx)
> -{
> - assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
> - return ctx->temp[ctx->ntemp++] = tcg_temp_new();
> -}
> -
> static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
> {
> TCGv t;
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
@ 2021-09-04 13:41 ` Bin Meng
0 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2021-09-04 13:41 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Sep 3, 2021 at 7:23 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The stval and mtval registers can optionally contain the faulting
> instruction on an illegal instruction exception. This patch adds support
> for setting the stval and mtval registers based on the CPU feature.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 5 ++++-
> target/riscv/cpu_helper.c | 9 +++++++++
> target/riscv/translate.c | 33 +++++++++++++++++++--------------
> 3 files changed, 32 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bf1c899c00..6d41a16ae3 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -77,7 +77,8 @@ enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> RISCV_FEATURE_EPMP,
> - RISCV_FEATURE_MISA
> + RISCV_FEATURE_MISA,
> + RISCV_FEATURE_MTVAL_INST,
> };
>
> #define PRIV_VERSION_1_10_0 0x00011000
> @@ -130,6 +131,8 @@ struct CPURISCVState {
> target_ulong frm;
>
> target_ulong badaddr;
> + target_ulong bins;
> +
> target_ulong guest_phys_fault_addr;
>
> target_ulong priv_ver;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 968cb8046f..42edd71c1e 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -967,6 +967,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> write_tval = true;
> tval = env->badaddr;
> break;
> + case RISCV_EXCP_ILLEGAL_INST:
> + if (riscv_feature(env, RISCV_FEATURE_MTVAL_INST)) {
> + /* The stval/mtval register can optionally also be used to
nits: incorrect multi-line comment format
> + * return the faulting instruction bits on an illegal
> + * instruction exception.
> + */
> + tval = env->bins;
> + }
> + break;
> default:
> break;
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e356fc6c46..4221d8e2d5 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -173,8 +173,27 @@ static void lookup_and_goto_ptr(DisasContext *ctx)
> }
> }
>
> +/*
> + * Wrappers for getting reg values.
> + *
> + * The $zero register does not have cpu_gpr[0] allocated -- we supply the
> + * constant zero as a source, and an uninitialized sink as destination.
> + *
> + * Further, we may provide an extension for word operations.
> + */
> +static TCGv temp_new(DisasContext *ctx)
> +{
> + assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
> + return ctx->temp[ctx->ntemp++] = tcg_temp_new();
> +}
> +
> static void gen_exception_illegal(DisasContext *ctx)
> {
> + TCGv tmp = temp_new(ctx);
> +
> + tcg_gen_movi_tl(tmp, ctx->opcode);
ctx->opcode is not initialized anywhere.
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));
> +
> generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> }
>
> @@ -195,20 +214,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> }
> }
>
> -/*
> - * Wrappers for getting reg values.
> - *
> - * The $zero register does not have cpu_gpr[0] allocated -- we supply the
> - * constant zero as a source, and an uninitialized sink as destination.
> - *
> - * Further, we may provide an extension for word operations.
> - */
> -static TCGv temp_new(DisasContext *ctx)
> -{
> - assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
> - return ctx->temp[ctx->ntemp++] = tcg_temp_new();
> -}
> -
> static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
> {
> TCGv t;
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-09-04 13:42 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-02 23:23 [PATCH v1 0/2] RISC-V: Populate mtval and stval Alistair Francis
2021-09-02 23:23 ` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2021-09-03 17:04 ` Richard Henderson
2021-09-03 17:04 ` Richard Henderson
2021-09-04 13:41 ` Bin Meng
2021-09-04 13:41 ` Bin Meng
2021-09-02 23:23 ` [PATCH v1 2/2] target/riscv: Set mtval and stval support Alistair Francis
2021-09-03 17:05 ` Richard Henderson
2021-09-03 17:05 ` Richard Henderson
2021-09-03 23:58 ` Bin Meng
2021-09-03 23:58 ` Bin Meng
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