* [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping
@ 2021-08-01 23:41 Philippe Mathieu-Daudé
2021-08-01 23:41 ` [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode Philippe Mathieu-Daudé
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-01 23:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno, Philippe Mathieu-Daudé
Minor cleanups while looking at converting more opcodes to decodetree.
Philippe Mathieu-Daudé (4):
target/mips: Simpify PREF opcode
target/mips: Decode vendor extensions before MIPS ISAs
target/mips: Merge 32-bit/64-bit release6 decodetree definitions
target/mips: Rename 'rtype' as 'r'
target/mips/tcg/mips64r6.decode | 27 --------
target/mips/tcg/msa.decode | 4 +-
.../mips/tcg/{mips32r6.decode => rel6.decode} | 17 ++++-
target/mips/tcg/tx79.decode | 14 ++---
target/mips/tcg/msa_translate.c | 4 +-
target/mips/tcg/rel6_translate.c | 20 +++---
target/mips/tcg/translate.c | 16 +++--
target/mips/tcg/tx79_translate.c | 62 +++++++++----------
target/mips/tcg/meson.build | 3 +-
9 files changed, 72 insertions(+), 95 deletions(-)
delete mode 100644 target/mips/tcg/mips64r6.decode
rename target/mips/tcg/{mips32r6.decode => rel6.decode} (64%)
--
2.31.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode
2021-08-01 23:41 [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
@ 2021-08-01 23:41 ` Philippe Mathieu-Daudé
2021-08-02 19:07 ` Richard Henderson
2021-08-01 23:42 ` [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-01 23:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno, Philippe Mathieu-Daudé
check_insn() checks for any bit in the set, and INSN_R5900 is
just another bit added to the set. No need to special-case it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/translate.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 34a96159d15..05efd25e29d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15738,12 +15738,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case OPC_PREF:
- if (ctx->insn_flags & INSN_R5900) {
- /* Treat as NOP. */
- } else {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
- /* Treat as NOP. */
- }
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900);
+ /* Treat as NOP. */
break;
/* Floating point (COP1). */
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs
2021-08-01 23:41 [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
2021-08-01 23:41 ` [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode Philippe Mathieu-Daudé
@ 2021-08-01 23:42 ` Philippe Mathieu-Daudé
2021-08-02 19:08 ` Richard Henderson
2021-08-01 23:42 ` [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-01 23:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno, Philippe Mathieu-Daudé
In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1
opcodes to decodetree") we misplaced the decoder call. Move
it to the correct place.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 05efd25e29d..9572cc56947 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16093,6 +16093,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Transition to the auto-generated decoder. */
+ /* Vendor extensions */
+ if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
+ return;
+ }
+
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
return;
@@ -16102,9 +16107,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
return;
}
- if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
- return;
- }
if (decode_opc_legacy(env, ctx)) {
return;
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions
2021-08-01 23:41 [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
2021-08-01 23:41 ` [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode Philippe Mathieu-Daudé
2021-08-01 23:42 ` [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs Philippe Mathieu-Daudé
@ 2021-08-01 23:42 ` Philippe Mathieu-Daudé
2021-08-02 19:09 ` Richard Henderson
2021-08-01 23:42 ` [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r' Philippe Mathieu-Daudé
2021-08-06 20:51 ` [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-01 23:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno, Philippe Mathieu-Daudé
We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/mips64r6.decode | 27 -------------------
.../mips/tcg/{mips32r6.decode => rel6.decode} | 13 +++++++++
target/mips/tcg/rel6_translate.c | 16 ++++-------
target/mips/tcg/meson.build | 3 +--
4 files changed, 19 insertions(+), 40 deletions(-)
delete mode 100644 target/mips/tcg/mips64r6.decode
rename target/mips/tcg/{mips32r6.decode => rel6.decode} (69%)
diff --git a/target/mips/tcg/mips64r6.decode b/target/mips/tcg/mips64r6.decode
deleted file mode 100644
index b58d8009ccd..00000000000
--- a/target/mips/tcg/mips64r6.decode
+++ /dev/null
@@ -1,27 +0,0 @@
-# MIPS64 Release 6 instruction set
-#
-# Copyright (C) 2020 Philippe Mathieu-Daudé
-#
-# SPDX-License-Identifier: LGPL-2.1-or-later
-#
-# Reference:
-# MIPS Architecture for Programmers Volume II-A
-# The MIPS64 Instruction Set Reference Manual, Revision 6.06
-# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
-#
-
-&rtype rs rt rd sa !extern
-
-&REMOVED !extern
-
-@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
-
-DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
-
-REMOVED 011010 ----- ----- ---------------- # LDL
-REMOVED 011011 ----- ----- ---------------- # LDR
-REMOVED 101100 ----- ----- ---------------- # SDL
-REMOVED 101101 ----- ----- ---------------- # SDR
-
-REMOVED 110100 ----- ----- ---------------- # LLD
-REMOVED 111100 ----- ----- ---------------- # SCD
diff --git a/target/mips/tcg/mips32r6.decode b/target/mips/tcg/rel6.decode
similarity index 69%
rename from target/mips/tcg/mips32r6.decode
rename to target/mips/tcg/rel6.decode
index 837c991edc5..ed069c51662 100644
--- a/target/mips/tcg/mips32r6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -5,21 +5,29 @@
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Reference:
+#
# MIPS Architecture for Programmers Volume II-A
# The MIPS32 Instruction Set Reference Manual, Revision 6.06
# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
#
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS64 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
&rtype rs rt rd sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+REMOVED 011010 ----- ----- ---------------- # LDL
+REMOVED 011011 ----- ----- ---------------- # LDR
+
REMOVED 011111 ----- ----- ---------- 011001 # LWLE
REMOVED 011111 ----- ----- ---------- 011010 # LWRE
REMOVED 011111 ----- ----- ---------- 100001 # SWLE
@@ -28,9 +36,14 @@ REMOVED 011111 ----- ----- ---------- 100010 # SWRE
REMOVED 100010 ----- ----- ---------------- # LWL
REMOVED 100110 ----- ----- ---------------- # LWR
REMOVED 101010 ----- ----- ---------------- # SWL
+REMOVED 101100 ----- ----- ---------------- # SDL
+REMOVED 101101 ----- ----- ---------------- # SDR
REMOVED 101110 ----- ----- ---------------- # SWR
REMOVED 101111 ----- ----- ---------------- # CACHE
+
REMOVED 110000 ----- ----- ---------------- # LL
REMOVED 110011 ----- ----- ---------------- # PREF
+REMOVED 110100 ----- ----- ---------------- # LLD
REMOVED 111000 ----- ----- ---------------- # SC
+REMOVED 111100 ----- ----- ---------------- # SCD
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 0354370927d..ae2e023a817 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -13,9 +13,8 @@
#include "exec/helper-gen.h"
#include "translate.h"
-/* Include the auto-generated decoder. */
-#include "decode-mips32r6.c.inc"
-#include "decode-mips64r6.c.inc"
+/* Include the auto-generated decoders. */
+#include "decode-rel6.c.inc"
bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
{
@@ -31,13 +30,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
{
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
}
-
-bool decode_isa_rel6(DisasContext *ctx, uint32_t insn)
-{
- if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) {
- return true;
- }
- return decode_mips32r6(ctx, insn);
-}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index bf4001e5741..70fa3dd57df 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -1,6 +1,5 @@
gen = [
- decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
- decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
+ decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
]
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r'
2021-08-01 23:41 [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-08-01 23:42 ` [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions Philippe Mathieu-Daudé
@ 2021-08-01 23:42 ` Philippe Mathieu-Daudé
2021-08-02 19:38 ` Richard Henderson
2021-08-06 20:51 ` [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-01 23:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno, Philippe Mathieu-Daudé
We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 4 +--
target/mips/tcg/rel6.decode | 4 +--
target/mips/tcg/tx79.decode | 14 ++++----
target/mips/tcg/msa_translate.c | 4 +--
target/mips/tcg/rel6_translate.c | 4 +--
target/mips/tcg/tx79_translate.c | 62 ++++++++++++++++----------------
6 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index bf132e36b9b..74d99f6862c 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -11,11 +11,11 @@
# - The MIPS64 SIMD Architecture Module, Revision 1.12
# (Document Number: MD00868-1D-MSA64-AFP-01.12)
-&rtype rs rt rd sa
+&r rs rt rd sa
&msa_bz df wt s16
-@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
index ed069c51662..d6989cf56e8 100644
--- a/target/mips/tcg/rel6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -14,9 +14,9 @@
# The MIPS64 Instruction Set Reference Manual, Revision 6.06
# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
-&rtype rs rt rd sa
+&r rs rt rd sa
-@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index 03a25a5096d..57d87a2076a 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -11,20 +11,20 @@
# when creating helpers common to those for the individual
# instruction patterns.
-&rtype rs rt rd sa
+&r rs rt rd sa
-&itype base rt offset
+&i base rt offset
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
-@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0
-@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0
-@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
-@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r sa=0
+@rt_rd ...... ..... rt:5 rd:5 ..... ...... &r sa=0 rs=0
+@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
+@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
-@ldst ...... base:5 rt:5 offset:16 &itype
+@ldst ...... base:5 rt:5 offset:16 &i
###########################################################################
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index eed2eca6c92..8170a8df26b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -2261,12 +2261,12 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
-static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
}
-static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_DLSA(DisasContext *ctx, arg_r *a)
{
if (TARGET_LONG_BITS != 64) {
return false;
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index ae2e023a817..d631851258a 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -23,12 +23,12 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
return true;
}
-static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
}
-static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_DLSA(DisasContext *ctx, arg_r *a)
{
if (TARGET_LONG_BITS != 64) {
return false;
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 395d6afa1f1..6d51fe17c1a 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -64,28 +64,28 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
* MTLO1 rs Move To LO1 Register
*/
-static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MFHI1(DisasContext *ctx, arg_r *a)
{
gen_store_gpr(cpu_HI[1], a->rd);
return true;
}
-static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MFLO1(DisasContext *ctx, arg_r *a)
{
gen_store_gpr(cpu_LO[1], a->rd);
return true;
}
-static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MTHI1(DisasContext *ctx, arg_r *a)
{
gen_load_gpr(cpu_HI[1], a->rs);
return true;
}
-static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MTLO1(DisasContext *ctx, arg_r *a)
{
gen_load_gpr(cpu_LO[1], a->rs);
@@ -116,7 +116,7 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
*/
-static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
+static bool trans_parallel_arith(DisasContext *ctx, arg_r *a,
void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
{
TCGv_i64 ax, bx;
@@ -146,19 +146,19 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
}
/* Parallel Subtract Byte */
-static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PSUBB(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64);
}
/* Parallel Subtract Halfword */
-static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PSUBH(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64);
}
/* Parallel Subtract Word */
-static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PSUBW(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64);
}
@@ -189,25 +189,25 @@ static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
*/
/* Parallel And */
-static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
+static bool trans_PAND(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_and_i64);
}
/* Parallel Or */
-static bool trans_POR(DisasContext *ctx, arg_rtype *a)
+static bool trans_POR(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_or_i64);
}
/* Parallel Exclusive Or */
-static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
+static bool trans_PXOR(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_xor_i64);
}
/* Parallel Not Or */
-static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
+static bool trans_PNOR(DisasContext *ctx, arg_r *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_nor_i64);
}
@@ -237,7 +237,7 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
* PCEQW rd, rs, rt Parallel Compare for Equal Word
*/
-static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
+static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
TCGCond cond, unsigned wlen)
{
TCGv_i64 c0, c1, ax, bx, t0, t1, t2;
@@ -286,37 +286,37 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
}
/* Parallel Compare for Greater Than Byte */
-static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCGTB(DisasContext *ctx, arg_r *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_GE, 8);
}
/* Parallel Compare for Equal Byte */
-static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCEQB(DisasContext *ctx, arg_r *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8);
}
/* Parallel Compare for Greater Than Halfword */
-static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCGTH(DisasContext *ctx, arg_r *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_GE, 16);
}
/* Parallel Compare for Equal Halfword */
-static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCEQH(DisasContext *ctx, arg_r *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16);
}
/* Parallel Compare for Greater Than Word */
-static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCGTW(DisasContext *ctx, arg_r *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_GE, 32);
}
/* Parallel Compare for Equal Word */
-static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCEQW(DisasContext *ctx, arg_r *a)
{
return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32);
}
@@ -334,7 +334,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
* SQ rt, offset(base) Store Quadword
*/
-static bool trans_LQ(DisasContext *ctx, arg_itype *a)
+static bool trans_LQ(DisasContext *ctx, arg_i *a)
{
TCGv_i64 t0;
TCGv addr;
@@ -369,7 +369,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
return true;
}
-static bool trans_SQ(DisasContext *ctx, arg_itype *a)
+static bool trans_SQ(DisasContext *ctx, arg_i *a)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv addr = tcg_temp_new();
@@ -437,7 +437,7 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a)
*/
/* Parallel Pack to Word */
-static bool trans_PPACW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PPACW(DisasContext *ctx, arg_r *a)
{
TCGv_i64 a0, b0, t0;
@@ -473,7 +473,7 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b)
tcg_gen_deposit_i64(dh, a, b, 0, 32);
}
-static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
+static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen)
{
TCGv_i64 ax, bx;
@@ -514,19 +514,19 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
}
/* Parallel Extend Lower from Byte */
-static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTLB(DisasContext *ctx, arg_r *a)
{
return trans_PEXTLx(ctx, a, 8);
}
/* Parallel Extend Lower from Halfword */
-static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTLH(DisasContext *ctx, arg_r *a)
{
return trans_PEXTLx(ctx, a, 16);
}
/* Parallel Extend Lower from Word */
-static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTLW(DisasContext *ctx, arg_r *a)
{
TCGv_i64 ax, bx;
@@ -549,7 +549,7 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
}
/* Parallel Extend Upper from Word */
-static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTUW(DisasContext *ctx, arg_r *a)
{
TCGv_i64 ax, bx;
@@ -593,7 +593,7 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
*/
/* Parallel Copy Halfword */
-static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
+static bool trans_PCPYH(DisasContext *s, arg_r *a)
{
if (a->rd == 0) {
/* nop */
@@ -615,7 +615,7 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
}
/* Parallel Copy Lower Doubleword */
-static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
+static bool trans_PCPYLD(DisasContext *s, arg_r *a)
{
if (a->rd == 0) {
/* nop */
@@ -638,7 +638,7 @@ static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
}
/* Parallel Copy Upper Doubleword */
-static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
+static bool trans_PCPYUD(DisasContext *s, arg_r *a)
{
if (a->rd == 0) {
/* nop */
@@ -657,7 +657,7 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
}
/* Parallel Rotate 3 Words Left */
-static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
+static bool trans_PROT3W(DisasContext *ctx, arg_r *a)
{
TCGv_i64 ax;
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode
2021-08-01 23:41 ` [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode Philippe Mathieu-Daudé
@ 2021-08-02 19:07 ` Richard Henderson
0 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2021-08-02 19:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 8/1/21 1:41 PM, Philippe Mathieu-Daudé wrote:
> check_insn() checks for any bit in the set, and INSN_R5900 is
> just another bit added to the set. No need to special-case it.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/translate.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs
2021-08-01 23:42 ` [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs Philippe Mathieu-Daudé
@ 2021-08-02 19:08 ` Richard Henderson
0 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2021-08-02 19:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 8/1/21 1:42 PM, Philippe Mathieu-Daudé wrote:
> In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1
> opcodes to decodetree") we misplaced the decoder call. Move
> it to the correct place.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/translate.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions
2021-08-01 23:42 ` [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions Philippe Mathieu-Daudé
@ 2021-08-02 19:09 ` Richard Henderson
0 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2021-08-02 19:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 8/1/21 1:42 PM, Philippe Mathieu-Daudé wrote:
> We don't need to maintain 2 sets of decodetree definitions.
> Merge them into a single file.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/mips64r6.decode | 27 -------------------
> .../mips/tcg/{mips32r6.decode => rel6.decode} | 13 +++++++++
> target/mips/tcg/rel6_translate.c | 16 ++++-------
> target/mips/tcg/meson.build | 3 +--
> 4 files changed, 19 insertions(+), 40 deletions(-)
> delete mode 100644 target/mips/tcg/mips64r6.decode
> rename target/mips/tcg/{mips32r6.decode => rel6.decode} (69%)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r'
2021-08-01 23:42 ` [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r' Philippe Mathieu-Daudé
@ 2021-08-02 19:38 ` Richard Henderson
0 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2021-08-02 19:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 8/1/21 1:42 PM, Philippe Mathieu-Daudé wrote:
> We'll soon have more opcode and decoded arguments, and 'rtype'
> is not very helpful. Naming it simply 'r' ease reviewing the
> .decode files when we have many opcodes.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/msa.decode | 4 +--
> target/mips/tcg/rel6.decode | 4 +--
> target/mips/tcg/tx79.decode | 14 ++++----
> target/mips/tcg/msa_translate.c | 4 +--
> target/mips/tcg/rel6_translate.c | 4 +--
> target/mips/tcg/tx79_translate.c | 62 ++++++++++++++++----------------
> 6 files changed, 46 insertions(+), 46 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping
2021-08-01 23:41 [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-08-01 23:42 ` [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r' Philippe Mathieu-Daudé
@ 2021-08-06 20:51 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-06 20:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 8/2/21 1:41 AM, Philippe Mathieu-Daudé wrote:
> Minor cleanups while looking at converting more opcodes to decodetree.
>
> Philippe Mathieu-Daudé (4):
> target/mips: Simpify PREF opcode
> target/mips: Decode vendor extensions before MIPS ISAs
> target/mips: Merge 32-bit/64-bit release6 decodetree definitions
> target/mips: Rename 'rtype' as 'r'
Thanks, series applied to mips-next tree.
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-08-06 20:52 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-01 23:41 [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
2021-08-01 23:41 ` [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode Philippe Mathieu-Daudé
2021-08-02 19:07 ` Richard Henderson
2021-08-01 23:42 ` [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs Philippe Mathieu-Daudé
2021-08-02 19:08 ` Richard Henderson
2021-08-01 23:42 ` [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions Philippe Mathieu-Daudé
2021-08-02 19:09 ` Richard Henderson
2021-08-01 23:42 ` [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r' Philippe Mathieu-Daudé
2021-08-02 19:38 ` Richard Henderson
2021-08-06 20:51 ` [PATCH-for-6.2 0/4] target/mips: Decodetree housekeeping Philippe Mathieu-Daudé
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