[PATCH v4 0/7] Make hcd-xhci independent of pci hooks

[PATCH v4 0/7] Make hcd-xhci independent of pci hooks

[Sai Pavan Boddu]

This patch series attempts to make 'hcd-xhci' an independent model so
it can be used by both pci and system-bus interface.

Changes for V2:
    Make XHCIState non-qom
    Use container_of functions for retriving pci device instance
    Initialize the AddressSpace pointer in PATCH 1/3 itself
Changes for V3:
    Convert XHCIState to TYPE_DEVICE and register as a child of XHCIPciState.
Changes for V4:
    Add DWC3 usb controller
    Add versal, usb2-reg module
    Connect sysbus xhci to versal virt board

Sai Pavan Boddu (5):
  usb/hcd-xhci: Make dma read/writes hooks pci free
  usb/hcd-xhci: Move qemu-xhci device to hcd-xhci-pci.c
  usb/hcd-xhci: Split pci wrapper for xhci base model
  usb: hcd-xhci-sysbus: Attach xhci to sysbus device
  misc: Add versal-usb2-regs module

Vikram Garhwal (2):
  usb: Add DWC3 model
  Versal: Connect DWC3 controller with virt-versal

 hw/arm/xlnx-versal-virt.c               |  59 ++++
 hw/arm/xlnx-versal.c                    |  38 ++
 hw/misc/Makefile.objs                   |   1 +
 hw/misc/xlnx-versal-usb2-regs.c         | 224 ++++++++++++
 hw/usb/Kconfig                          |  11 +
 hw/usb/Makefile.objs                    |   3 +
 hw/usb/hcd-dwc3.c                       | 606 ++++++++++++++++++++++++++++++++
 hw/usb/hcd-xhci-nec.c                   |  18 +-
 hw/usb/hcd-xhci-pci.c                   | 244 +++++++++++++
 hw/usb/hcd-xhci-pci.h                   |  45 +++
 hw/usb/hcd-xhci-sysbus.c                |  99 ++++++
 hw/usb/hcd-xhci-sysbus.h                |  32 ++
 hw/usb/hcd-xhci.c                       | 260 +++-----------
 hw/usb/hcd-xhci.h                       |  22 +-
 include/hw/arm/xlnx-versal.h            |  14 +
 include/hw/misc/xlnx-versal-usb2-regs.h |  43 +++
 include/hw/usb/hcd-dwc3.h               |  58 +++
 17 files changed, 1552 insertions(+), 225 deletions(-)
 create mode 100644 hw/misc/xlnx-versal-usb2-regs.c
 create mode 100644 hw/usb/hcd-dwc3.c
 create mode 100644 hw/usb/hcd-xhci-pci.c
 create mode 100644 hw/usb/hcd-xhci-pci.h
 create mode 100644 hw/usb/hcd-xhci-sysbus.c
 create mode 100644 hw/usb/hcd-xhci-sysbus.h
 create mode 100644 include/hw/misc/xlnx-versal-usb2-regs.h
 create mode 100644 include/hw/usb/hcd-dwc3.h

-- 
2.7.4

[PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Sai Pavan Boddu]

This patch starts making the hcd-xhci.c pci free, as part of this
restructuring dma read/writes are handled without passing pci object.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/usb/hcd-xhci.c | 24 +++++++++++-------------
 hw/usb/hcd-xhci.h |  3 +++
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 67a18fe..2590f7a 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -495,7 +495,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
 
     assert((len % sizeof(uint32_t)) == 0);
 
-    pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
+    dma_memory_read(xhci->as, addr, buf, len);
 
     for (i = 0; i < (len / sizeof(uint32_t)); i++) {
         buf[i] = le32_to_cpu(buf[i]);
@@ -515,7 +515,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
     for (i = 0; i < n; i++) {
         tmp[i] = cpu_to_le32(buf[i]);
     }
-    pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
+    dma_memory_write(xhci->as, addr, tmp, len);
 }
 
 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
@@ -644,7 +644,6 @@ static void xhci_die(XHCIState *xhci)
 
 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
 {
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
     XHCIInterrupter *intr = &xhci->intr[v];
     XHCITRB ev_trb;
     dma_addr_t addr;
@@ -663,7 +662,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
                                ev_trb.status, ev_trb.control);
 
     addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
-    pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
+    dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE);
 
     intr->er_ep_idx++;
     if (intr->er_ep_idx >= intr->er_size) {
@@ -720,12 +719,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
                                dma_addr_t *addr)
 {
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
     uint32_t link_cnt = 0;
 
     while (1) {
         TRBType type;
-        pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
+        dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE);
         trb->addr = ring->dequeue;
         trb->ccs = ring->ccs;
         le64_to_cpus(&trb->parameter);
@@ -762,7 +760,6 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
 
 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
 {
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
     XHCITRB trb;
     int length = 0;
     dma_addr_t dequeue = ring->dequeue;
@@ -773,7 +770,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
 
     while (1) {
         TRBType type;
-        pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
+        dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE);
         le64_to_cpus(&trb.parameter);
         le32_to_cpus(&trb.status);
         le32_to_cpus(&trb.control);
@@ -828,7 +825,7 @@ static void xhci_er_reset(XHCIState *xhci, int v)
         xhci_die(xhci);
         return;
     }
-    pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
+    dma_memory_read(xhci->as, erstba, &seg, sizeof(seg));
     le32_to_cpus(&seg.addr_low);
     le32_to_cpus(&seg.addr_high);
     le32_to_cpus(&seg.size);
@@ -1440,7 +1437,7 @@ static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
     int i;
 
     xfer->int_req = false;
-    pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
+    qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
     for (i = 0; i < xfer->trb_count; i++) {
         XHCITRB *trb = &xfer->trbs[i];
         dma_addr_t addr;
@@ -2101,7 +2098,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
     assert(slotid >= 1 && slotid <= xhci->numslots);
 
     dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
-    poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
+    poctx = ldq_le_dma(xhci->as, dcbaap + 8 * slotid);
     ictx = xhci_mask64(pictx);
     octx = xhci_mask64(poctx);
 
@@ -2439,7 +2436,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
     /* TODO: actually implement real values here */
     bw_ctx[0] = 0;
     memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
-    pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
+    dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx));
 
     return CC_SUCCESS;
 }
@@ -3431,6 +3428,7 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
     }
 
     usb_xhci_init(xhci);
+    xhci->as = pci_get_address_space(dev);
     xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
 
     memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
@@ -3531,7 +3529,7 @@ static int usb_xhci_post_load(void *opaque, int version_id)
             continue;
         }
         slot->ctx =
-            xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
+            xhci_mask64(ldq_le_dma(xhci->as, dcbaap + 8 * slotid));
         xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
         slot->uport = xhci_lookup_uport(xhci, slot_ctx);
         if (!slot->uport) {
diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
index 946af51..edbd926 100644
--- a/hw/usb/hcd-xhci.h
+++ b/hw/usb/hcd-xhci.h
@@ -22,6 +22,8 @@
 #ifndef HW_USB_HCD_XHCI_H
 #define HW_USB_HCD_XHCI_H
 
+#include "sysemu/dma.h"
+
 #define TYPE_XHCI "base-xhci"
 #define TYPE_NEC_XHCI "nec-usb-xhci"
 #define TYPE_QEMU_XHCI "qemu-xhci"
@@ -189,6 +191,7 @@ struct XHCIState {
 
     USBBus bus;
     MemoryRegion mem;
+    AddressSpace *as;
     MemoryRegion mem_cap;
     MemoryRegion mem_oper;
     MemoryRegion mem_runtime;
-- 
2.7.4

Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Philippe Mathieu-Daudé]

On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> This patch starts making the hcd-xhci.c pci free, as part of this
> restructuring dma read/writes are handled without passing pci object.
> 
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------
>  hw/usb/hcd-xhci.h |  3 +++
>  2 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
> index 67a18fe..2590f7a 100644
> --- a/hw/usb/hcd-xhci.c
> +++ b/hw/usb/hcd-xhci.c
> @@ -495,7 +495,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
>  
>      assert((len % sizeof(uint32_t)) == 0);
>  
> -    pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
> +    dma_memory_read(xhci->as, addr, buf, len);
>  
>      for (i = 0; i < (len / sizeof(uint32_t)); i++) {
>          buf[i] = le32_to_cpu(buf[i]);
> @@ -515,7 +515,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
>      for (i = 0; i < n; i++) {
>          tmp[i] = cpu_to_le32(buf[i]);
>      }
> -    pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
> +    dma_memory_write(xhci->as, addr, tmp, len);
>  }
>  
>  static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
> @@ -644,7 +644,6 @@ static void xhci_die(XHCIState *xhci)
>  
>  static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
>  {
> -    PCIDevice *pci_dev = PCI_DEVICE(xhci);
>      XHCIInterrupter *intr = &xhci->intr[v];
>      XHCITRB ev_trb;
>      dma_addr_t addr;
> @@ -663,7 +662,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
>                                 ev_trb.status, ev_trb.control);
>  
>      addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
> -    pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
> +    dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE);
>  
>      intr->er_ep_idx++;
>      if (intr->er_ep_idx >= intr->er_size) {
> @@ -720,12 +719,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
>  static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
>                                 dma_addr_t *addr)
>  {
> -    PCIDevice *pci_dev = PCI_DEVICE(xhci);
>      uint32_t link_cnt = 0;
>  
>      while (1) {
>          TRBType type;
> -        pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
> +        dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE);
>          trb->addr = ring->dequeue;
>          trb->ccs = ring->ccs;
>          le64_to_cpus(&trb->parameter);
> @@ -762,7 +760,6 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
>  
>  static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
>  {
> -    PCIDevice *pci_dev = PCI_DEVICE(xhci);
>      XHCITRB trb;
>      int length = 0;
>      dma_addr_t dequeue = ring->dequeue;
> @@ -773,7 +770,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
>  
>      while (1) {
>          TRBType type;
> -        pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
> +        dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE);
>          le64_to_cpus(&trb.parameter);
>          le32_to_cpus(&trb.status);
>          le32_to_cpus(&trb.control);
> @@ -828,7 +825,7 @@ static void xhci_er_reset(XHCIState *xhci, int v)
>          xhci_die(xhci);
>          return;
>      }
> -    pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
> +    dma_memory_read(xhci->as, erstba, &seg, sizeof(seg));
>      le32_to_cpus(&seg.addr_low);
>      le32_to_cpus(&seg.addr_high);
>      le32_to_cpus(&seg.size);
> @@ -1440,7 +1437,7 @@ static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
>      int i;
>  
>      xfer->int_req = false;
> -    pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
> +    qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
>      for (i = 0; i < xfer->trb_count; i++) {
>          XHCITRB *trb = &xfer->trbs[i];
>          dma_addr_t addr;
> @@ -2101,7 +2098,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
>      assert(slotid >= 1 && slotid <= xhci->numslots);
>  
>      dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
> -    poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
> +    poctx = ldq_le_dma(xhci->as, dcbaap + 8 * slotid);
>      ictx = xhci_mask64(pictx);
>      octx = xhci_mask64(poctx);
>  
> @@ -2439,7 +2436,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
>      /* TODO: actually implement real values here */
>      bw_ctx[0] = 0;
>      memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
> -    pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
> +    dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx));
>  
>      return CC_SUCCESS;
>  }
> @@ -3431,6 +3428,7 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
>      }
>  
>      usb_xhci_init(xhci);
> +    xhci->as = pci_get_address_space(dev);
>      xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
>  
>      memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
> @@ -3531,7 +3529,7 @@ static int usb_xhci_post_load(void *opaque, int version_id)
>              continue;
>          }
>          slot->ctx =
> -            xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
> +            xhci_mask64(ldq_le_dma(xhci->as, dcbaap + 8 * slotid));
>          xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
>          slot->uport = xhci_lookup_uport(xhci, slot_ctx);
>          if (!slot->uport) {
> diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
> index 946af51..edbd926 100644
> --- a/hw/usb/hcd-xhci.h
> +++ b/hw/usb/hcd-xhci.h
> @@ -22,6 +22,8 @@
>  #ifndef HW_USB_HCD_XHCI_H
>  #define HW_USB_HCD_XHCI_H
>  
> +#include "sysemu/dma.h"

AddressSpace is forward-declared in "qemu/typedefs.h",
so no need to include it here (yes in the sources including
hcd-xhci.h).

With that fixed:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> +
>  #define TYPE_XHCI "base-xhci"
>  #define TYPE_NEC_XHCI "nec-usb-xhci"
>  #define TYPE_QEMU_XHCI "qemu-xhci"
> @@ -189,6 +191,7 @@ struct XHCIState {
>  
>      USBBus bus;
>      MemoryRegion mem;
> +    AddressSpace *as;
>      MemoryRegion mem_cap;
>      MemoryRegion mem_oper;
>      MemoryRegion mem_runtime;
> 

RE: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Sai Pavan Boddu]

Hi Philippe,

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@redhat.com>
> Sent: Tuesday, September 1, 2020 10:05 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell
> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;
> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
> Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>
> Cc: qemu-devel@nongnu.org; Alistair Francis <alistair.francis@wdc.com>;
> Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
> <fangying1@huawei.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci
> free
> 
> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> > This patch starts making the hcd-xhci.c pci free, as part of this
> > restructuring dma read/writes are handled without passing pci object.
> >
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > ---
> >  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h |
> > 3 +++
> >  2 files changed, 14 insertions(+), 13 deletions(-)
> >
> > diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index
> > 67a18fe..2590f7a 100644
> > --- a/hw/usb/hcd-xhci.c
> > +++ b/hw/usb/hcd-xhci.c
> > @@ -495,7 +495,7 @@ static inline void xhci_dma_read_u32s(XHCIState
> > *xhci, dma_addr_t addr,
> >
> >      assert((len % sizeof(uint32_t)) == 0);
> >
> > -    pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
> > +    dma_memory_read(xhci->as, addr, buf, len);
> >
> >      for (i = 0; i < (len / sizeof(uint32_t)); i++) {
> >          buf[i] = le32_to_cpu(buf[i]); @@ -515,7 +515,7 @@ static
> > inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
> >      for (i = 0; i < n; i++) {
> >          tmp[i] = cpu_to_le32(buf[i]);
> >      }
> > -    pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
> > +    dma_memory_write(xhci->as, addr, tmp, len);
> >  }
> >
> >  static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort
> > *uport) @@ -644,7 +644,6 @@ static void xhci_die(XHCIState *xhci)
> >
> >  static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int
> > v)  {
> > -    PCIDevice *pci_dev = PCI_DEVICE(xhci);
> >      XHCIInterrupter *intr = &xhci->intr[v];
> >      XHCITRB ev_trb;
> >      dma_addr_t addr;
> > @@ -663,7 +662,7 @@ static void xhci_write_event(XHCIState *xhci,
> XHCIEvent *event, int v)
> >                                 ev_trb.status, ev_trb.control);
> >
> >      addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
> > -    pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
> > +    dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE);
> >
> >      intr->er_ep_idx++;
> >      if (intr->er_ep_idx >= intr->er_size) { @@ -720,12 +719,11 @@
> > static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,  static
> > TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
> >                                 dma_addr_t *addr)  {
> > -    PCIDevice *pci_dev = PCI_DEVICE(xhci);
> >      uint32_t link_cnt = 0;
> >
> >      while (1) {
> >          TRBType type;
> > -        pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
> > +        dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE);
> >          trb->addr = ring->dequeue;
> >          trb->ccs = ring->ccs;
> >          le64_to_cpus(&trb->parameter); @@ -762,7 +760,6 @@ static
> > TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
> >
> >  static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing
> > *ring)  {
> > -    PCIDevice *pci_dev = PCI_DEVICE(xhci);
> >      XHCITRB trb;
> >      int length = 0;
> >      dma_addr_t dequeue = ring->dequeue; @@ -773,7 +770,7 @@ static
> > int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
> >
> >      while (1) {
> >          TRBType type;
> > -        pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
> > +        dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE);
> >          le64_to_cpus(&trb.parameter);
> >          le32_to_cpus(&trb.status);
> >          le32_to_cpus(&trb.control);
> > @@ -828,7 +825,7 @@ static void xhci_er_reset(XHCIState *xhci, int v)
> >          xhci_die(xhci);
> >          return;
> >      }
> > -    pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
> > +    dma_memory_read(xhci->as, erstba, &seg, sizeof(seg));
> >      le32_to_cpus(&seg.addr_low);
> >      le32_to_cpus(&seg.addr_high);
> >      le32_to_cpus(&seg.size);
> > @@ -1440,7 +1437,7 @@ static int xhci_xfer_create_sgl(XHCITransfer
> *xfer, int in_xfer)
> >      int i;
> >
> >      xfer->int_req = false;
> > -    pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
> > +    qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count,
> > + xhci->as);
> >      for (i = 0; i < xfer->trb_count; i++) {
> >          XHCITRB *trb = &xfer->trbs[i];
> >          dma_addr_t addr;
> > @@ -2101,7 +2098,7 @@ static TRBCCode xhci_address_slot(XHCIState
> *xhci, unsigned int slotid,
> >      assert(slotid >= 1 && slotid <= xhci->numslots);
> >
> >      dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
> > -    poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
> > +    poctx = ldq_le_dma(xhci->as, dcbaap + 8 * slotid);
> >      ictx = xhci_mask64(pictx);
> >      octx = xhci_mask64(poctx);
> >
> > @@ -2439,7 +2436,7 @@ static TRBCCode
> xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
> >      /* TODO: actually implement real values here */
> >      bw_ctx[0] = 0;
> >      memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
> > -    pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
> > +    dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx));
> >
> >      return CC_SUCCESS;
> >  }
> > @@ -3431,6 +3428,7 @@ static void usb_xhci_realize(struct PCIDevice
> *dev, Error **errp)
> >      }
> >
> >      usb_xhci_init(xhci);
> > +    xhci->as = pci_get_address_space(dev);
> >      xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> > xhci_mfwrap_timer, xhci);
> >
> >      memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
> > @@ -3531,7 +3529,7 @@ static int usb_xhci_post_load(void *opaque, int
> version_id)
> >              continue;
> >          }
> >          slot->ctx =
> > -            xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
> > +            xhci_mask64(ldq_le_dma(xhci->as, dcbaap + 8 * slotid));
> >          xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
> >          slot->uport = xhci_lookup_uport(xhci, slot_ctx);
> >          if (!slot->uport) {
> > diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h index
> > 946af51..edbd926 100644
> > --- a/hw/usb/hcd-xhci.h
> > +++ b/hw/usb/hcd-xhci.h
> > @@ -22,6 +22,8 @@
> >  #ifndef HW_USB_HCD_XHCI_H
> >  #define HW_USB_HCD_XHCI_H
> >
> > +#include "sysemu/dma.h"
> 
> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
> include it here (yes in the sources including hcd-xhci.h).
[Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is undefined. 
At this point of the patch, hcd-xhci.h is compiled along with pci.h which would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-xhci we would miss it. Let me know, if its good to add later in the patch series when the split happens.

Regards,
Sai Pavan
> 
> With that fixed:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> 
> > +
> >  #define TYPE_XHCI "base-xhci"
> >  #define TYPE_NEC_XHCI "nec-usb-xhci"
> >  #define TYPE_QEMU_XHCI "qemu-xhci"
> > @@ -189,6 +191,7 @@ struct XHCIState {
> >
> >      USBBus bus;
> >      MemoryRegion mem;
> > +    AddressSpace *as;
> >      MemoryRegion mem_cap;
> >      MemoryRegion mem_oper;
> >      MemoryRegion mem_runtime;
> >

Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Philippe Mathieu-Daudé]

>> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
>>> This patch starts making the hcd-xhci.c pci free, as part of this
>>> restructuring dma read/writes are handled without passing pci object.
>>>
>>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
>>> ---
>>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h |
>>> 3 +++
>>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>>
[...]
>>> --- a/hw/usb/hcd-xhci.h
>>> +++ b/hw/usb/hcd-xhci.h
>>> @@ -22,6 +22,8 @@
>>>  #ifndef HW_USB_HCD_XHCI_H
>>>  #define HW_USB_HCD_XHCI_H
>>>
>>> +#include "sysemu/dma.h"
>>
>> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
>> include it here (yes in the sources including hcd-xhci.h).
> [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is undefined. 
> At this point of the patch, hcd-xhci.h is compiled along with pci.h which would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-xhci we would miss it. Let me know, if its good to add later in the patch series when the split happens.

OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.

Cc'ing David who added dma_addr_t in commit e5332e6334f
("iommu: Introduce IOMMU emulation infrastructure"), it
might be simpler to move its declaration to "qemu/typedefs.h"
too.

So no change needed for this patch.

> 
> Regards,
> Sai Pavan
>>
>> With that fixed:
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>
>>> +
>>>  #define TYPE_XHCI "base-xhci"
>>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
>>>  #define TYPE_QEMU_XHCI "qemu-xhci"
>>> @@ -189,6 +191,7 @@ struct XHCIState {
>>>
>>>      USBBus bus;
>>>      MemoryRegion mem;
>>> +    AddressSpace *as;
>>>      MemoryRegion mem_cap;
>>>      MemoryRegion mem_oper;
>>>      MemoryRegion mem_runtime;
>>>
> 

Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Philippe Mathieu-Daudé]

On 9/8/20 12:30 PM, Philippe Mathieu-Daudé wrote:
>>> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
>>>> This patch starts making the hcd-xhci.c pci free, as part of this
>>>> restructuring dma read/writes are handled without passing pci object.
>>>>
>>>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
>>>> ---
>>>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h |
>>>> 3 +++
>>>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>>>
> [...]
>>>> --- a/hw/usb/hcd-xhci.h
>>>> +++ b/hw/usb/hcd-xhci.h
>>>> @@ -22,6 +22,8 @@
>>>>  #ifndef HW_USB_HCD_XHCI_H
>>>>  #define HW_USB_HCD_XHCI_H
>>>>
>>>> +#include "sysemu/dma.h"
>>>
>>> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
>>> include it here (yes in the sources including hcd-xhci.h).
>> [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is undefined. 
>> At this point of the patch, hcd-xhci.h is compiled along with pci.h which would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-xhci we would miss it. Let me know, if its good to add later in the patch series when the split happens.
> 
> OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.
> 
> Cc'ing David who added dma_addr_t in commit e5332e6334f
> ("iommu: Introduce IOMMU emulation infrastructure"), it
> might be simpler to move its declaration to "qemu/typedefs.h"
> too.

Btw this type should be poisoned for user-mode.

> 
> So no change needed for this patch.
> 
>>
>> Regards,
>> Sai Pavan
>>>
>>> With that fixed:
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>
>>>> +
>>>>  #define TYPE_XHCI "base-xhci"
>>>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
>>>>  #define TYPE_QEMU_XHCI "qemu-xhci"
>>>> @@ -189,6 +191,7 @@ struct XHCIState {
>>>>
>>>>      USBBus bus;
>>>>      MemoryRegion mem;
>>>> +    AddressSpace *as;
>>>>      MemoryRegion mem_cap;
>>>>      MemoryRegion mem_oper;
>>>>      MemoryRegion mem_runtime;
>>>>
>>
> 

RE: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Sai Pavan Boddu]

Hi Philippe,

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@redhat.com>
> Sent: Tuesday, September 8, 2020 4:05 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell
> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;
> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
> Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>; David Gibson <david@gibson.dropbear.id.au>
> Cc: qemu-devel@nongnu.org; Alistair Francis <alistair.francis@wdc.com>;
> Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
> <fangying1@huawei.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci
> free
> 
> On 9/8/20 12:30 PM, Philippe Mathieu-Daudé wrote:
> >>> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> >>>> This patch starts making the hcd-xhci.c pci free, as part of this
> >>>> restructuring dma read/writes are handled without passing pci object.
> >>>>
> >>>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> >>>> ---
> >>>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h
> >>>> |
> >>>> 3 +++
> >>>>  2 files changed, 14 insertions(+), 13 deletions(-)
> >>>>
> > [...]
> >>>> --- a/hw/usb/hcd-xhci.h
> >>>> +++ b/hw/usb/hcd-xhci.h
> >>>> @@ -22,6 +22,8 @@
> >>>>  #ifndef HW_USB_HCD_XHCI_H
> >>>>  #define HW_USB_HCD_XHCI_H
> >>>>
> >>>> +#include "sysemu/dma.h"
> >>>
> >>> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
> >>> include it here (yes in the sources including hcd-xhci.h).
> >> [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is
> undefined.
> >> At this point of the patch, hcd-xhci.h is compiled along with pci.h which
> would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-
> xhci we would miss it. Let me know, if its good to add later in the patch series
> when the split happens.
> >
> > OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.
> >
> > Cc'ing David who added dma_addr_t in commit e5332e6334f
> > ("iommu: Introduce IOMMU emulation infrastructure"), it might be
> > simpler to move its declaration to "qemu/typedefs.h"
> > too.
> 
> Btw this type should be poisoned for user-mode.
[Sai Pavan Boddu] Thanks, I would try to define them in typedefs.h. 
BTW I'm not clear about poisoning then in user-mode. Do you mean hide these defines for user-mode ?

Regards
Sai Pavan
> 
> >
> > So no change needed for this patch.
> >
> >>
> >> Regards,
> >> Sai Pavan
> >>>
> >>> With that fixed:
> >>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>>
> >>>> +
> >>>>  #define TYPE_XHCI "base-xhci"
> >>>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
> >>>>  #define TYPE_QEMU_XHCI "qemu-xhci"
> >>>> @@ -189,6 +191,7 @@ struct XHCIState {
> >>>>
> >>>>      USBBus bus;
> >>>>      MemoryRegion mem;
> >>>> +    AddressSpace *as;
> >>>>      MemoryRegion mem_cap;
> >>>>      MemoryRegion mem_oper;
> >>>>      MemoryRegion mem_runtime;
> >>>>
> >>
> >

Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Philippe Mathieu-Daudé]

On 9/8/20 1:35 PM, Sai Pavan Boddu wrote:
> Hi Philippe,
> 
>> -----Original Message-----
>> From: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Sent: Tuesday, September 8, 2020 4:05 PM
>> To: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;
>> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini
>> <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
>> Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
>> <figlesia@xilinx.com>; David Gibson <david@gibson.dropbear.id.au>
>> Cc: qemu-devel@nongnu.org; Alistair Francis <alistair.francis@wdc.com>;
>> Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
>> <fangying1@huawei.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
>> Zimmerman <pauldzim@gmail.com>
>> Subject: Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci
>> free
>>
>> On 9/8/20 12:30 PM, Philippe Mathieu-Daudé wrote:
>>>>> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
>>>>>> This patch starts making the hcd-xhci.c pci free, as part of this
>>>>>> restructuring dma read/writes are handled without passing pci object.
>>>>>>
>>>>>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
>>>>>> ---
>>>>>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h
>>>>>> |
>>>>>> 3 +++
>>>>>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>>>>>
>>> [...]
>>>>>> --- a/hw/usb/hcd-xhci.h
>>>>>> +++ b/hw/usb/hcd-xhci.h
>>>>>> @@ -22,6 +22,8 @@
>>>>>>  #ifndef HW_USB_HCD_XHCI_H
>>>>>>  #define HW_USB_HCD_XHCI_H
>>>>>>
>>>>>> +#include "sysemu/dma.h"
>>>>>
>>>>> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
>>>>> include it here (yes in the sources including hcd-xhci.h).
>>>> [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is
>> undefined.
>>>> At this point of the patch, hcd-xhci.h is compiled along with pci.h which
>> would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-
>> xhci we would miss it. Let me know, if its good to add later in the patch series
>> when the split happens.
>>>
>>> OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.
>>>
>>> Cc'ing David who added dma_addr_t in commit e5332e6334f
>>> ("iommu: Introduce IOMMU emulation infrastructure"), it might be
>>> simpler to move its declaration to "qemu/typedefs.h"
>>> too.
>>
>> Btw this type should be poisoned for user-mode.
> [Sai Pavan Boddu] Thanks, I would try to define them in typedefs.h. 
> BTW I'm not clear about poisoning then in user-mode. Do you mean hide these defines for user-mode ?

This doesn't "hide" but poison them: if you try to use them the
compiler (cpp actually) will raise an error.

This was not a direct comment for you, more something to discuss
out of the scope of your series ;) No need to try to declare it
poisoned now.

> 
> Regards
> Sai Pavan
>>
>>>
>>> So no change needed for this patch.
>>>
>>>>
>>>> Regards,
>>>> Sai Pavan
>>>>>
>>>>> With that fixed:
>>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>>>
>>>>>> +
>>>>>>  #define TYPE_XHCI "base-xhci"
>>>>>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
>>>>>>  #define TYPE_QEMU_XHCI "qemu-xhci"
>>>>>> @@ -189,6 +191,7 @@ struct XHCIState {
>>>>>>
>>>>>>      USBBus bus;
>>>>>>      MemoryRegion mem;
>>>>>> +    AddressSpace *as;
>>>>>>      MemoryRegion mem_cap;
>>>>>>      MemoryRegion mem_oper;
>>>>>>      MemoryRegion mem_runtime;
>>>>>>
>>>>
>>>
> 

RE: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[Sai Pavan Boddu]

Hi Philippe,

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@redhat.com>
> Sent: Tuesday, September 8, 2020 5:57 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell
> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;
> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
> Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>; David Gibson <david@gibson.dropbear.id.au>
> Cc: qemu-devel@nongnu.org; Alistair Francis <alistair.francis@wdc.com>;
> Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
> <fangying1@huawei.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci
> free
> 
> On 9/8/20 1:35 PM, Sai Pavan Boddu wrote:
> > Hi Philippe,
> >
> >> -----Original Message-----
> >> From: Philippe Mathieu-Daudé <philmd@redhat.com>
> >> Sent: Tuesday, September 8, 2020 4:05 PM
> >> To: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell
> >> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;
> >> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini
> >> <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
> >> Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> >> <figlesia@xilinx.com>; David Gibson <david@gibson.dropbear.id.au>
> >> Cc: qemu-devel@nongnu.org; Alistair Francis
> >> <alistair.francis@wdc.com>; Eduardo Habkost <ehabkost@redhat.com>;
> >> Ying Fang <fangying1@huawei.com>; Vikram Garhwal <fnuv@xilinx.com>;
> >> Paul Zimmerman <pauldzim@gmail.com>
> >> Subject: Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks
> >> pci free
> >>
> >> On 9/8/20 12:30 PM, Philippe Mathieu-Daudé wrote:
> >>>>> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> >>>>>> This patch starts making the hcd-xhci.c pci free, as part of this
> >>>>>> restructuring dma read/writes are handled without passing pci
> object.
> >>>>>>
> >>>>>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> >>>>>> ---
> >>>>>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------
> >>>>>> hw/usb/hcd-xhci.h
> >>>>>> |
> >>>>>> 3 +++
> >>>>>>  2 files changed, 14 insertions(+), 13 deletions(-)
> >>>>>>
> >>> [...]
> >>>>>> --- a/hw/usb/hcd-xhci.h
> >>>>>> +++ b/hw/usb/hcd-xhci.h
> >>>>>> @@ -22,6 +22,8 @@
> >>>>>>  #ifndef HW_USB_HCD_XHCI_H
> >>>>>>  #define HW_USB_HCD_XHCI_H
> >>>>>>
> >>>>>> +#include "sysemu/dma.h"
> >>>>>
> >>>>> AddressSpace is forward-declared in "qemu/typedefs.h", so no need
> >>>>> to include it here (yes in the sources including hcd-xhci.h).
> >>>> [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t
> >>>> " is
> >> undefined.
> >>>> At this point of the patch, hcd-xhci.h is compiled along with pci.h
> >>>> which
> >> would provide 'dma_addr_t', but when we strip the pci wrapper around
> >> hcd- xhci we would miss it. Let me know, if its good to add later in
> >> the patch series when the split happens.
> >>>
> >>> OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.
> >>>
> >>> Cc'ing David who added dma_addr_t in commit e5332e6334f
> >>> ("iommu: Introduce IOMMU emulation infrastructure"), it might be
> >>> simpler to move its declaration to "qemu/typedefs.h"
> >>> too.
> >>
> >> Btw this type should be poisoned for user-mode.
> > [Sai Pavan Boddu] Thanks, I would try to define them in typedefs.h.
> > BTW I'm not clear about poisoning then in user-mode. Do you mean hide
> these defines for user-mode ?
> 
> This doesn't "hide" but poison them: if you try to use them the compiler (cpp
> actually) will raise an error.
> 
> This was not a direct comment for you, more something to discuss out of the
> scope of your series ;) No need to try to declare it poisoned now.
[Sai Pavan Boddu] One more thing, which came up during implementation is dma_memory_read/ dma_memory_write functions which used in this patch would require that header.

Regards,
Sai Pavan
> 
> >
> > Regards
> > Sai Pavan
> >>
> >>>
> >>> So no change needed for this patch.
> >>>
> >>>>
> >>>> Regards,
> >>>> Sai Pavan
> >>>>>
> >>>>> With that fixed:
> >>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>>>>
> >>>>>> +
> >>>>>>  #define TYPE_XHCI "base-xhci"
> >>>>>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
> >>>>>>  #define TYPE_QEMU_XHCI "qemu-xhci"
> >>>>>> @@ -189,6 +191,7 @@ struct XHCIState {
> >>>>>>
> >>>>>>      USBBus bus;
> >>>>>>      MemoryRegion mem;
> >>>>>> +    AddressSpace *as;
> >>>>>>      MemoryRegion mem_cap;
> >>>>>>      MemoryRegion mem_oper;
> >>>>>>      MemoryRegion mem_runtime;
> >>>>>>
> >>>>
> >>>
> >

Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[David Gibson]

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On Tue, Sep 08, 2020 at 12:34:59PM +0200, Philippe Mathieu-Daudé wrote:
> On 9/8/20 12:30 PM, Philippe Mathieu-Daudé wrote:
> >>> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> >>>> This patch starts making the hcd-xhci.c pci free, as part of this
> >>>> restructuring dma read/writes are handled without passing pci object.
> >>>>
> >>>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> >>>> ---
> >>>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h |
> >>>> 3 +++
> >>>>  2 files changed, 14 insertions(+), 13 deletions(-)
> >>>>
> > [...]
> >>>> --- a/hw/usb/hcd-xhci.h
> >>>> +++ b/hw/usb/hcd-xhci.h
> >>>> @@ -22,6 +22,8 @@
> >>>>  #ifndef HW_USB_HCD_XHCI_H
> >>>>  #define HW_USB_HCD_XHCI_H
> >>>>
> >>>> +#include "sysemu/dma.h"
> >>>
> >>> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
> >>> include it here (yes in the sources including hcd-xhci.h).
> >> [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is undefined. 
> >> At this point of the patch, hcd-xhci.h is compiled along with pci.h which would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-xhci we would miss it. Let me know, if its good to add later in the patch series when the split happens.
> > 
> > OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.
> > 
> > Cc'ing David who added dma_addr_t in commit e5332e6334f
> > ("iommu: Introduce IOMMU emulation infrastructure"), it
> > might be simpler to move its declaration to "qemu/typedefs.h"
> > too.
> 
> Btw this type should be poisoned for user-mode.

Yes, yes it should.


> 
> > 
> > So no change needed for this patch.
> > 
> >>
> >> Regards,
> >> Sai Pavan
> >>>
> >>> With that fixed:
> >>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>>
> >>>> +
> >>>>  #define TYPE_XHCI "base-xhci"
> >>>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
> >>>>  #define TYPE_QEMU_XHCI "qemu-xhci"
> >>>> @@ -189,6 +191,7 @@ struct XHCIState {
> >>>>
> >>>>      USBBus bus;
> >>>>      MemoryRegion mem;
> >>>> +    AddressSpace *as;
> >>>>      MemoryRegion mem_cap;
> >>>>      MemoryRegion mem_oper;
> >>>>      MemoryRegion mem_runtime;
> >>>>
> >>
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

[David Gibson]

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On Tue, Sep 08, 2020 at 12:30:17PM +0200, Philippe Mathieu-Daudé wrote:
> >> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> >>> This patch starts making the hcd-xhci.c pci free, as part of this
> >>> restructuring dma read/writes are handled without passing pci object.
> >>>
> >>> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> >>> ---
> >>>  hw/usb/hcd-xhci.c | 24 +++++++++++-------------  hw/usb/hcd-xhci.h |
> >>> 3 +++
> >>>  2 files changed, 14 insertions(+), 13 deletions(-)
> >>>
> [...]
> >>> --- a/hw/usb/hcd-xhci.h
> >>> +++ b/hw/usb/hcd-xhci.h
> >>> @@ -22,6 +22,8 @@
> >>>  #ifndef HW_USB_HCD_XHCI_H
> >>>  #define HW_USB_HCD_XHCI_H
> >>>
> >>> +#include "sysemu/dma.h"
> >>
> >> AddressSpace is forward-declared in "qemu/typedefs.h", so no need to
> >> include it here (yes in the sources including hcd-xhci.h).
> > [Sai Pavan Boddu] Yes you are right!, but without this " dma_addr_t " is undefined. 
> > At this point of the patch, hcd-xhci.h is compiled along with pci.h which would provide 'dma_addr_t', but when we strip the pci wrapper around hcd-xhci we would miss it. Let me know, if its good to add later in the patch series when the split happens.
> 
> OK :( I'd prefer to only include "sysemu/dma.h" in hw/usb/hcd-xhci.c.
> 
> Cc'ing David who added dma_addr_t in commit e5332e6334f
> ("iommu: Introduce IOMMU emulation infrastructure"), it
> might be simpler to move its declaration to "qemu/typedefs.h"
> too.

Moving it to qemu/typedefs.h seems fine to me fwiw.

> 
> So no change needed for this patch.
> 
> > 
> > Regards,
> > Sai Pavan
> >>
> >> With that fixed:
> >> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>
> >>> +
> >>>  #define TYPE_XHCI "base-xhci"
> >>>  #define TYPE_NEC_XHCI "nec-usb-xhci"
> >>>  #define TYPE_QEMU_XHCI "qemu-xhci"
> >>> @@ -189,6 +191,7 @@ struct XHCIState {
> >>>
> >>>      USBBus bus;
> >>>      MemoryRegion mem;
> >>> +    AddressSpace *as;
> >>>      MemoryRegion mem_cap;
> >>>      MemoryRegion mem_oper;
> >>>      MemoryRegion mem_runtime;
> >>>
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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[PATCH v4 2/7] usb/hcd-xhci: Move qemu-xhci device to hcd-xhci-pci.c

[Sai Pavan Boddu]

Move pci specific devices to new file. This set the environment to move all
pci specific hooks in hcd-xhci.c to hcd-xhci-pci.c.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/usb/Kconfig        |  6 +++++
 hw/usb/Makefile.objs  |  1 +
 hw/usb/hcd-xhci-pci.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/usb/hcd-xhci.c     | 41 ++------------------------------
 hw/usb/hcd-xhci.h     |  3 +++
 5 files changed, 78 insertions(+), 39 deletions(-)
 create mode 100644 hw/usb/hcd-xhci-pci.c

diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index d4d8c37..d9965c1 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -36,6 +36,12 @@ config USB_XHCI
     depends on PCI
     select USB
 
+config USB_XHCI_PCI
+    bool
+    default y if PCI_DEVICES
+    depends on PCI
+    select USB_XHCI
+
 config USB_XHCI_NEC
     bool
     default y if PCI_DEVICES
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index e342ff5..029b040 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -11,6 +11,7 @@ common-obj-$(CONFIG_USB_EHCI_PCI) += hcd-ehci-pci.o
 common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
 common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
 common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
+common-obj-$(CONFIG_USB_XHCI_PCI) += hcd-xhci-pci.o
 common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
 common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
 
diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
new file mode 100644
index 0000000..1562757
--- /dev/null
+++ b/hw/usb/hcd-xhci-pci.c
@@ -0,0 +1,66 @@
+/*
+ * USB xHCI controller with PCI bus emulation
+ *
+ * SPDX-FileCopyrightText: 2011 Securiforest
+ * SPDX-FileContributor: Hector Martin <hector@marcansoft.com>
+ * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0
+ * SPDX-FileCopyrightText: 2020 Xilinx
+ * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
+ * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to
+ *                  hcd-xhci-pci.c
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "hw/pci/pci.h"
+#include "hw/qdev-properties.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/msix.h"
+#include "hcd-xhci.h"
+#include "trace.h"
+#include "qapi/error.h"
+
+static void qemu_xhci_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
+    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
+    k->revision     = 0x01;
+}
+
+static void qemu_xhci_instance_init(Object *obj)
+{
+    XHCIState *xhci = XHCI(obj);
+
+    xhci->msi      = ON_OFF_AUTO_OFF;
+    xhci->msix     = ON_OFF_AUTO_AUTO;
+    xhci->numintrs = MAXINTRS;
+    xhci->numslots = MAXSLOTS;
+    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
+}
+
+static const TypeInfo qemu_xhci_info = {
+    .name          = TYPE_QEMU_XHCI,
+    .parent        = TYPE_XHCI,
+    .class_init    = qemu_xhci_class_init,
+    .instance_init = qemu_xhci_instance_init,
+};
+
+static void xhci_register_types(void)
+{
+    type_register_static(&qemu_xhci_info);
+}
+
+type_init(xhci_register_types)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 2590f7a..b15c53b 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -23,7 +23,6 @@
 #include "qemu/timer.h"
 #include "qemu/module.h"
 #include "qemu/queue.h"
-#include "hw/usb.h"
 #include "migration/vmstate.h"
 #include "hw/pci/pci.h"
 #include "hw/qdev-properties.h"
@@ -429,12 +428,12 @@ static const char *ep_state_name(uint32_t state)
                        ARRAY_SIZE(ep_state_names));
 }
 
-static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
+bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
 {
     return xhci->flags & (1 << bit);
 }
 
-static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
+void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
 {
     xhci->flags |= (1 << bit);
 }
@@ -3692,13 +3691,6 @@ static Property xhci_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static void xhci_instance_init(Object *obj)
-{
-    /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
-     * line, therefore, no need to wait to realize like other devices */
-    PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
-}
-
 static void xhci_class_init(ObjectClass *klass, void *data)
 {
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -3718,7 +3710,6 @@ static const TypeInfo xhci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(XHCIState),
     .class_init    = xhci_class_init,
-    .instance_init = xhci_instance_init,
     .abstract      = true,
     .interfaces = (InterfaceInfo[]) {
         { INTERFACE_PCIE_DEVICE },
@@ -3727,37 +3718,9 @@ static const TypeInfo xhci_info = {
     },
 };
 
-static void qemu_xhci_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
-    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
-    k->revision     = 0x01;
-}
-
-static void qemu_xhci_instance_init(Object *obj)
-{
-    XHCIState *xhci = XHCI(obj);
-
-    xhci->msi      = ON_OFF_AUTO_OFF;
-    xhci->msix     = ON_OFF_AUTO_AUTO;
-    xhci->numintrs = MAXINTRS;
-    xhci->numslots = MAXSLOTS;
-    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
-}
-
-static const TypeInfo qemu_xhci_info = {
-    .name          = TYPE_QEMU_XHCI,
-    .parent        = TYPE_XHCI,
-    .class_init    = qemu_xhci_class_init,
-    .instance_init = qemu_xhci_instance_init,
-};
-
 static void xhci_register_types(void)
 {
     type_register_static(&xhci_info);
-    type_register_static(&qemu_xhci_info);
 }
 
 type_init(xhci_register_types)
diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
index edbd926..dd5fcd4 100644
--- a/hw/usb/hcd-xhci.h
+++ b/hw/usb/hcd-xhci.h
@@ -23,6 +23,7 @@
 #define HW_USB_HCD_XHCI_H
 
 #include "sysemu/dma.h"
+#include "hw/usb.h"
 
 #define TYPE_XHCI "base-xhci"
 #define TYPE_NEC_XHCI "nec-usb-xhci"
@@ -232,4 +233,6 @@ struct XHCIState {
     bool nec_quirks;
 };
 
+bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit);
+void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit);
 #endif
-- 
2.7.4

Re: [PATCH v4 2/7] usb/hcd-xhci: Move qemu-xhci device to hcd-xhci-pci.c

[Philippe Mathieu-Daudé]

On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> Move pci specific devices to new file. This set the environment to move all
> pci specific hooks in hcd-xhci.c to hcd-xhci-pci.c.
> 
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
>  hw/usb/Kconfig        |  6 +++++
>  hw/usb/Makefile.objs  |  1 +
>  hw/usb/hcd-xhci-pci.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/usb/hcd-xhci.c     | 41 ++------------------------------
>  hw/usb/hcd-xhci.h     |  3 +++
>  5 files changed, 78 insertions(+), 39 deletions(-)
>  create mode 100644 hw/usb/hcd-xhci-pci.c
> 
> diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
> index d4d8c37..d9965c1 100644
> --- a/hw/usb/Kconfig
> +++ b/hw/usb/Kconfig
> @@ -36,6 +36,12 @@ config USB_XHCI
>      depends on PCI
>      select USB
>  
> +config USB_XHCI_PCI
> +    bool
> +    default y if PCI_DEVICES
> +    depends on PCI
> +    select USB_XHCI
> +
>  config USB_XHCI_NEC
>      bool
>      default y if PCI_DEVICES
> diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
> index e342ff5..029b040 100644
> --- a/hw/usb/Makefile.objs
> +++ b/hw/usb/Makefile.objs
> @@ -11,6 +11,7 @@ common-obj-$(CONFIG_USB_EHCI_PCI) += hcd-ehci-pci.o
>  common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
>  common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
>  common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
> +common-obj-$(CONFIG_USB_XHCI_PCI) += hcd-xhci-pci.o
>  common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
>  common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
>  
> diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
> new file mode 100644
> index 0000000..1562757
> --- /dev/null
> +++ b/hw/usb/hcd-xhci-pci.c
> @@ -0,0 +1,66 @@
> +/*
> + * USB xHCI controller with PCI bus emulation
> + *
> + * SPDX-FileCopyrightText: 2011 Securiforest
> + * SPDX-FileContributor: Hector Martin <hector@marcansoft.com>
> + * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0
> + * SPDX-FileCopyrightText: 2020 Xilinx
> + * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> + * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to
> + *                  hcd-xhci-pci.c
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "hw/pci/pci.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/pci/msi.h"
> +#include "hw/pci/msix.h"
> +#include "hcd-xhci.h"
> +#include "trace.h"
> +#include "qapi/error.h"
> +
> +static void qemu_xhci_class_init(ObjectClass *klass, void *data)
> +{
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
> +    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
> +    k->revision     = 0x01;
> +}
> +
> +static void qemu_xhci_instance_init(Object *obj)
> +{
> +    XHCIState *xhci = XHCI(obj);
> +
> +    xhci->msi      = ON_OFF_AUTO_OFF;
> +    xhci->msix     = ON_OFF_AUTO_AUTO;
> +    xhci->numintrs = MAXINTRS;
> +    xhci->numslots = MAXSLOTS;
> +    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
> +}
> +
> +static const TypeInfo qemu_xhci_info = {
> +    .name          = TYPE_QEMU_XHCI,
> +    .parent        = TYPE_XHCI,
> +    .class_init    = qemu_xhci_class_init,
> +    .instance_init = qemu_xhci_instance_init,
> +};
> +
> +static void xhci_register_types(void)
> +{
> +    type_register_static(&qemu_xhci_info);
> +}
> +
> +type_init(xhci_register_types)
> diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
> index 2590f7a..b15c53b 100644
> --- a/hw/usb/hcd-xhci.c
> +++ b/hw/usb/hcd-xhci.c
> @@ -23,7 +23,6 @@
>  #include "qemu/timer.h"
>  #include "qemu/module.h"
>  #include "qemu/queue.h"
> -#include "hw/usb.h"
>  #include "migration/vmstate.h"
>  #include "hw/pci/pci.h"
>  #include "hw/qdev-properties.h"
> @@ -429,12 +428,12 @@ static const char *ep_state_name(uint32_t state)
>                         ARRAY_SIZE(ep_state_names));
>  }
>  
> -static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
> +bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
>  {
>      return xhci->flags & (1 << bit);
>  }
>  
> -static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
> +void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
>  {
>      xhci->flags |= (1 << bit);
>  }
> @@ -3692,13 +3691,6 @@ static Property xhci_properties[] = {
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> -static void xhci_instance_init(Object *obj)
> -{
> -    /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
> -     * line, therefore, no need to wait to realize like other devices */
> -    PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;

What happened to this flag?

> -}
> -
>  static void xhci_class_init(ObjectClass *klass, void *data)
>  {
>      PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> @@ -3718,7 +3710,6 @@ static const TypeInfo xhci_info = {
>      .parent        = TYPE_PCI_DEVICE,
>      .instance_size = sizeof(XHCIState),
>      .class_init    = xhci_class_init,
> -    .instance_init = xhci_instance_init,
>      .abstract      = true,
>      .interfaces = (InterfaceInfo[]) {
>          { INTERFACE_PCIE_DEVICE },
> @@ -3727,37 +3718,9 @@ static const TypeInfo xhci_info = {
>      },
>  };
>  
> -static void qemu_xhci_class_init(ObjectClass *klass, void *data)
> -{
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
> -    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
> -    k->revision     = 0x01;
> -}
> -
> -static void qemu_xhci_instance_init(Object *obj)
> -{
> -    XHCIState *xhci = XHCI(obj);
> -
> -    xhci->msi      = ON_OFF_AUTO_OFF;
> -    xhci->msix     = ON_OFF_AUTO_AUTO;
> -    xhci->numintrs = MAXINTRS;
> -    xhci->numslots = MAXSLOTS;
> -    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
> -}
> -
> -static const TypeInfo qemu_xhci_info = {
> -    .name          = TYPE_QEMU_XHCI,
> -    .parent        = TYPE_XHCI,
> -    .class_init    = qemu_xhci_class_init,
> -    .instance_init = qemu_xhci_instance_init,
> -};
> -
>  static void xhci_register_types(void)
>  {
>      type_register_static(&xhci_info);
> -    type_register_static(&qemu_xhci_info);
>  }
>  
>  type_init(xhci_register_types)
> diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
> index edbd926..dd5fcd4 100644
> --- a/hw/usb/hcd-xhci.h
> +++ b/hw/usb/hcd-xhci.h
> @@ -23,6 +23,7 @@
>  #define HW_USB_HCD_XHCI_H
>  
>  #include "sysemu/dma.h"
> +#include "hw/usb.h"
>  
>  #define TYPE_XHCI "base-xhci"
>  #define TYPE_NEC_XHCI "nec-usb-xhci"
> @@ -232,4 +233,6 @@ struct XHCIState {
>      bool nec_quirks;
>  };
>  
> +bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit);
> +void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit);
>  #endif
> 

RE: [PATCH v4 2/7] usb/hcd-xhci: Move qemu-xhci device to hcd-xhci-pci.c

[Sai Pavan Boddu]

Hi Philippe,

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@redhat.com>
> Sent: Tuesday, September 1, 2020 10:08 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell
> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;
> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
> Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>
> Cc: qemu-devel@nongnu.org; Alistair Francis <alistair.francis@wdc.com>;
> Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
> <fangying1@huawei.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 2/7] usb/hcd-xhci: Move qemu-xhci device to hcd-
> xhci-pci.c
> 
> On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> > Move pci specific devices to new file. This set the environment to
> > move all pci specific hooks in hcd-xhci.c to hcd-xhci-pci.c.
> >
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > ---
> >  hw/usb/Kconfig        |  6 +++++
> >  hw/usb/Makefile.objs  |  1 +
> >  hw/usb/hcd-xhci-pci.c | 66
> +++++++++++++++++++++++++++++++++++++++++++++++++++
> >  hw/usb/hcd-xhci.c     | 41 ++------------------------------
> >  hw/usb/hcd-xhci.h     |  3 +++
> >  5 files changed, 78 insertions(+), 39 deletions(-)  create mode
> > 100644 hw/usb/hcd-xhci-pci.c
> >
> > diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index d4d8c37..d9965c1
> > 100644
> > --- a/hw/usb/Kconfig
> > +++ b/hw/usb/Kconfig
> > @@ -36,6 +36,12 @@ config USB_XHCI
> >      depends on PCI
> >      select USB
> >
> > +config USB_XHCI_PCI
> > +    bool
> > +    default y if PCI_DEVICES
> > +    depends on PCI
> > +    select USB_XHCI
> > +
> >  config USB_XHCI_NEC
> >      bool
> >      default y if PCI_DEVICES
> > diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs index
> > e342ff5..029b040 100644
> > --- a/hw/usb/Makefile.objs
> > +++ b/hw/usb/Makefile.objs
> > @@ -11,6 +11,7 @@ common-obj-$(CONFIG_USB_EHCI_PCI) += hcd-ehci-
> pci.o
> >  common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
> >  common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
> >  common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
> > +common-obj-$(CONFIG_USB_XHCI_PCI) += hcd-xhci-pci.o
> >  common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
> >  common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
> >
> > diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c new file
> > mode 100644 index 0000000..1562757
> > --- /dev/null
> > +++ b/hw/usb/hcd-xhci-pci.c
> > @@ -0,0 +1,66 @@
> > +/*
> > + * USB xHCI controller with PCI bus emulation
> > + *
> > + * SPDX-FileCopyrightText: 2011 Securiforest
> > + * SPDX-FileContributor: Hector Martin <hector@marcansoft.com>
> > + * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0
> > + * SPDX-FileCopyrightText: 2020 Xilinx
> > + * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > + * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to
> > + *                  hcd-xhci-pci.c
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see
> <http://www.gnu.org/licenses/>.
> > + */
> > +#include "qemu/osdep.h"
> > +#include "hw/pci/pci.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/pci/msi.h"
> > +#include "hw/pci/msix.h"
> > +#include "hcd-xhci.h"
> > +#include "trace.h"
> > +#include "qapi/error.h"
> > +
> > +static void qemu_xhci_class_init(ObjectClass *klass, void *data) {
> > +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> > +
> > +    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
> > +    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
> > +    k->revision     = 0x01;
> > +}
> > +
> > +static void qemu_xhci_instance_init(Object *obj) {
> > +    XHCIState *xhci = XHCI(obj);
> > +
> > +    xhci->msi      = ON_OFF_AUTO_OFF;
> > +    xhci->msix     = ON_OFF_AUTO_AUTO;
> > +    xhci->numintrs = MAXINTRS;
> > +    xhci->numslots = MAXSLOTS;
> > +    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST); }
> > +
> > +static const TypeInfo qemu_xhci_info = {
> > +    .name          = TYPE_QEMU_XHCI,
> > +    .parent        = TYPE_XHCI,
> > +    .class_init    = qemu_xhci_class_init,
> > +    .instance_init = qemu_xhci_instance_init, };
> > +
> > +static void xhci_register_types(void) {
> > +    type_register_static(&qemu_xhci_info);
> > +}
> > +
> > +type_init(xhci_register_types)
> > diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index
> > 2590f7a..b15c53b 100644
> > --- a/hw/usb/hcd-xhci.c
> > +++ b/hw/usb/hcd-xhci.c
> > @@ -23,7 +23,6 @@
> >  #include "qemu/timer.h"
> >  #include "qemu/module.h"
> >  #include "qemu/queue.h"
> > -#include "hw/usb.h"
> >  #include "migration/vmstate.h"
> >  #include "hw/pci/pci.h"
> >  #include "hw/qdev-properties.h"
> > @@ -429,12 +428,12 @@ static const char *ep_state_name(uint32_t state)
> >                         ARRAY_SIZE(ep_state_names));  }
> >
> > -static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
> > +bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
> >  {
> >      return xhci->flags & (1 << bit);
> >  }
> >
> > -static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
> > +void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
> >  {
> >      xhci->flags |= (1 << bit);
> >  }
> > @@ -3692,13 +3691,6 @@ static Property xhci_properties[] = {
> >      DEFINE_PROP_END_OF_LIST(),
> >  };
> >
> > -static void xhci_instance_init(Object *obj) -{
> > -    /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU
> command
> > -     * line, therefore, no need to wait to realize like other devices */
> > -    PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
> 
> What happened to this flag?
[Sai Pavan Boddu] During a patch split this has been moved into patch 3/7. I would make these changes come into one patch.

Regards,
Sai Pavan
> 
> > -}
> > -
> >  static void xhci_class_init(ObjectClass *klass, void *data)  {
> >      PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); @@ -3718,7 +3710,6
> > @@ static const TypeInfo xhci_info = {
> >      .parent        = TYPE_PCI_DEVICE,
> >      .instance_size = sizeof(XHCIState),
> >      .class_init    = xhci_class_init,
> > -    .instance_init = xhci_instance_init,
> >      .abstract      = true,
> >      .interfaces = (InterfaceInfo[]) {
> >          { INTERFACE_PCIE_DEVICE },
> > @@ -3727,37 +3718,9 @@ static const TypeInfo xhci_info = {
> >      },
> >  };
> >
> > -static void qemu_xhci_class_init(ObjectClass *klass, void *data) -{
> > -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> > -
> > -    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
> > -    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
> > -    k->revision     = 0x01;
> > -}
> > -
> > -static void qemu_xhci_instance_init(Object *obj) -{
> > -    XHCIState *xhci = XHCI(obj);
> > -
> > -    xhci->msi      = ON_OFF_AUTO_OFF;
> > -    xhci->msix     = ON_OFF_AUTO_AUTO;
> > -    xhci->numintrs = MAXINTRS;
> > -    xhci->numslots = MAXSLOTS;
> > -    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
> > -}
> > -
> > -static const TypeInfo qemu_xhci_info = {
> > -    .name          = TYPE_QEMU_XHCI,
> > -    .parent        = TYPE_XHCI,
> > -    .class_init    = qemu_xhci_class_init,
> > -    .instance_init = qemu_xhci_instance_init,
> > -};
> > -
> >  static void xhci_register_types(void)  {
> >      type_register_static(&xhci_info);
> > -    type_register_static(&qemu_xhci_info);
> >  }
> >
> >  type_init(xhci_register_types)
> > diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h index
> > edbd926..dd5fcd4 100644
> > --- a/hw/usb/hcd-xhci.h
> > +++ b/hw/usb/hcd-xhci.h
> > @@ -23,6 +23,7 @@
> >  #define HW_USB_HCD_XHCI_H
> >
> >  #include "sysemu/dma.h"
> > +#include "hw/usb.h"
> >
> >  #define TYPE_XHCI "base-xhci"
> >  #define TYPE_NEC_XHCI "nec-usb-xhci"
> > @@ -232,4 +233,6 @@ struct XHCIState {
> >      bool nec_quirks;
> >  };
> >
> > +bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit); void
> > +xhci_set_flag(XHCIState *xhci, enum xhci_flags bit);
> >  #endif
> >

[PATCH v4 3/7] usb/hcd-xhci: Split pci wrapper for xhci base model

[Sai Pavan Boddu]

This patch sets the base to use xhci as sysbus model, for which pci
specific hooks are moved to hcd-xhci-pci.c. As a part of this requirment
msi/msix interrupts handling is moved under XHCIPCIState. Made required
changes for qemu-xhci-nec.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/usb/hcd-xhci-nec.c |  18 ++---
 hw/usb/hcd-xhci-pci.c | 188 +++++++++++++++++++++++++++++++++++++++++++++--
 hw/usb/hcd-xhci-pci.h |  45 ++++++++++++
 hw/usb/hcd-xhci.c     | 197 ++++++++++----------------------------------------
 hw/usb/hcd-xhci.h     |  15 ++--
 5 files changed, 284 insertions(+), 179 deletions(-)
 create mode 100644 hw/usb/hcd-xhci-pci.h

diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c
index e6a5a22..2efa6fa 100644
--- a/hw/usb/hcd-xhci-nec.c
+++ b/hw/usb/hcd-xhci-nec.c
@@ -25,17 +25,17 @@
 #include "hw/pci/pci.h"
 #include "hw/qdev-properties.h"
 
-#include "hcd-xhci.h"
+#include "hcd-xhci-pci.h"
 
 static Property nec_xhci_properties[] = {
-    DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO),
-    DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO),
-    DEFINE_PROP_BIT("superspeed-ports-first",
-                    XHCIState, flags, XHCI_FLAG_SS_FIRST, true),
-    DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags,
+    DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
+    DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO),
+    DEFINE_PROP_BIT("superspeed-ports-first", XHCIPciState,
+                    xhci.flags, XHCI_FLAG_SS_FIRST, true),
+    DEFINE_PROP_BIT("force-pcie-endcap", XHCIPciState, xhci.flags,
                     XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
-    DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
-    DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
+    DEFINE_PROP_UINT32("intrs", XHCIPciState, xhci.numintrs, MAXINTRS),
+    DEFINE_PROP_UINT32("slots", XHCIPciState, xhci.numslots, MAXSLOTS),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -52,7 +52,7 @@ static void nec_xhci_class_init(ObjectClass *klass, void *data)
 
 static const TypeInfo nec_xhci_info = {
     .name          = TYPE_NEC_XHCI,
-    .parent        = TYPE_XHCI,
+    .parent        = TYPE_XHCI_PCI,
     .class_init    = nec_xhci_class_init,
 };
 
diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
index 1562757..15d288c 100644
--- a/hw/usb/hcd-xhci-pci.c
+++ b/hw/usb/hcd-xhci-pci.c
@@ -25,12 +25,188 @@
 #include "qemu/osdep.h"
 #include "hw/pci/pci.h"
 #include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
 #include "hw/pci/msi.h"
 #include "hw/pci/msix.h"
-#include "hcd-xhci.h"
+#include "hcd-xhci-pci.h"
 #include "trace.h"
 #include "qapi/error.h"
 
+#define OFF_MSIX_TABLE  0x3000
+#define OFF_MSIX_PBA    0x3800
+
+static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
+{
+    XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
+    PCIDevice *pci_dev = PCI_DEVICE(s);
+
+    if (!msix_enabled(pci_dev)) {
+        return;
+    }
+    if (enable == !!s->msix_used[n]) {
+        return;
+    }
+    if (enable) {
+        trace_usb_xhci_irq_msix_use(n);
+        msix_vector_use(pci_dev, n);
+        s->msix_used[n] = 1;
+    } else {
+        trace_usb_xhci_irq_msix_unuse(n);
+        msix_vector_unuse(pci_dev, n);
+        s->msix_used[n] = 0;
+    }
+}
+
+static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
+{
+    XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
+    PCIDevice *pci_dev = PCI_DEVICE(s);
+
+    if (n == 0 &&
+        !(msix_enabled(pci_dev) ||
+         msi_enabled(pci_dev))) {
+        pci_set_irq(pci_dev, level);
+    }
+    if (msix_enabled(pci_dev)) {
+        msix_notify(pci_dev, n);
+        return;
+    }
+
+    if (msi_enabled(pci_dev)) {
+        msi_notify(pci_dev, n);
+        return;
+    }
+}
+
+static void xhci_pci_reset(DeviceState *dev)
+{
+    XHCIPciState *s = XHCI_PCI(dev);
+
+    device_legacy_reset(DEVICE(&s->xhci));
+}
+
+static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
+{
+    int ret;
+    Error *err = NULL;
+    XHCIPciState *s = XHCI_PCI(dev);
+
+    dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
+    dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
+    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
+    dev->config[0x60] = 0x30; /* release number */
+
+    object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
+    s->xhci.intr_update = xhci_pci_intr_update;
+    s->xhci.intr_raise = xhci_pci_intr_raise;
+    object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
+        s->xhci.nec_quirks = true;
+    }
+
+    if (s->msi != ON_OFF_AUTO_OFF) {
+        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
+        /*
+         * Any error other than -ENOTSUP(board's MSI support is broken)
+         * is a programming error
+         */
+        assert(!ret || ret == -ENOTSUP);
+        if (ret && s->msi == ON_OFF_AUTO_ON) {
+            /* Can't satisfy user's explicit msi=on request, fail */
+            error_append_hint(&err, "You have to use msi=auto (default) or "
+                    "msi=off with this machine type.\n");
+            error_propagate(errp, err);
+            return;
+        }
+        assert(!err || s->msi == ON_OFF_AUTO_AUTO);
+        /* With msi=auto, we fall back to MSI off silently */
+        error_free(err);
+    }
+    pci_register_bar(dev, 0,
+                     PCI_BASE_ADDRESS_SPACE_MEMORY |
+                     PCI_BASE_ADDRESS_MEM_TYPE_64,
+                     &s->xhci.mem);
+
+    if (pci_bus_is_express(pci_get_bus(dev)) ||
+        xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
+        ret = pcie_endpoint_cap_init(dev, 0xa0);
+        assert(ret > 0);
+    }
+
+    if (s->msix != ON_OFF_AUTO_OFF) {
+        /* TODO check for errors, and should fail when msix=on */
+        msix_init(dev, s->xhci.numintrs,
+                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
+                  &s->xhci.mem, 0, OFF_MSIX_PBA,
+                  0x90, NULL);
+    }
+    s->xhci.as = pci_get_address_space(dev);
+}
+
+static void usb_xhci_pci_exit(PCIDevice *dev)
+{
+    XHCIPciState *s = XHCI_PCI(dev);
+    /* destroy msix memory region */
+    if (dev->msix_table && dev->msix_pba
+        && dev->msix_entry_used) {
+        msix_uninit(dev, &s->xhci.mem, &s->xhci.mem);
+    }
+}
+
+static const VMStateDescription vmstate_xhci_pci = {
+    .name = "xhci-pci",
+    .version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(parent_obj, XHCIPciState),
+        VMSTATE_MSIX(parent_obj, XHCIPciState),
+        VMSTATE_UINT8_ARRAY(msix_used, XHCIPciState, MAXINTRS),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void xhci_instance_init(Object *obj)
+{
+    XHCIPciState *s = XHCI_PCI(obj);
+    /*
+     * QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
+     * line, therefore, no need to wait to realize like other devices
+     */
+    PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
+    object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
+    qdev_alias_all_properties(DEVICE(&s->xhci), obj);
+}
+
+static void xhci_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset   = xhci_pci_reset;
+    dc->vmsd    = &vmstate_xhci_pci;
+    set_bit(DEVICE_CATEGORY_USB, dc->categories);
+    k->realize      = usb_xhci_pci_realize;
+    k->exit         = usb_xhci_pci_exit;
+    k->class_id     = PCI_CLASS_SERIAL_USB;
+}
+
+static const TypeInfo xhci_pci_info = {
+    .name          = TYPE_XHCI_PCI,
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(XHCIPciState),
+    .class_init    = xhci_class_init,
+    .instance_init = xhci_instance_init,
+    .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+        { }
+    },
+};
+
 static void qemu_xhci_class_init(ObjectClass *klass, void *data)
 {
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -42,10 +218,11 @@ static void qemu_xhci_class_init(ObjectClass *klass, void *data)
 
 static void qemu_xhci_instance_init(Object *obj)
 {
-    XHCIState *xhci = XHCI(obj);
+    XHCIPciState *s = XHCI_PCI(obj);
+    XHCIState *xhci = &s->xhci;
 
-    xhci->msi      = ON_OFF_AUTO_OFF;
-    xhci->msix     = ON_OFF_AUTO_AUTO;
+    s->msi      = ON_OFF_AUTO_OFF;
+    s->msix     = ON_OFF_AUTO_AUTO;
     xhci->numintrs = MAXINTRS;
     xhci->numslots = MAXSLOTS;
     xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
@@ -53,13 +230,14 @@ static void qemu_xhci_instance_init(Object *obj)
 
 static const TypeInfo qemu_xhci_info = {
     .name          = TYPE_QEMU_XHCI,
-    .parent        = TYPE_XHCI,
+    .parent        = TYPE_XHCI_PCI,
     .class_init    = qemu_xhci_class_init,
     .instance_init = qemu_xhci_instance_init,
 };
 
 static void xhci_register_types(void)
 {
+    type_register_static(&xhci_pci_info);
     type_register_static(&qemu_xhci_info);
 }
 
diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
new file mode 100644
index 0000000..e7c005e
--- /dev/null
+++ b/hw/usb/hcd-xhci-pci.h
@@ -0,0 +1,45 @@
+/*
+ * USB xHCI controller emulation
+ *
+ * Copyright (c) 2011 Securiforest
+ * Date: 2011-05-11 ;  Author: Hector Martin <hector@marcansoft.com>
+ * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
+ * Date: 2020-01-1; Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
+ * PCI hooks are moved from XHCIState to XHCIPciState
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_USB_HCD_XHCI_PCI_H
+#define HW_USB_HCD_XHCI_PCI_H
+
+#include "hw/usb.h"
+#include "hcd-xhci.h"
+
+#define TYPE_XHCI_PCI "pci-xhci"
+#define XHCI_PCI(obj) \
+    OBJECT_CHECK(XHCIPciState, (obj), TYPE_XHCI_PCI)
+
+
+typedef struct XHCIPciState {
+    /*< private >*/
+    PCIDevice parent_obj;
+    /*< public >*/
+    XHCIState xhci;
+    OnOffAuto msi;
+    OnOffAuto msix;
+    uint8_t msix_used[MAXINTRS];
+} XHCIPciState;
+
+#endif
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index b15c53b..d5c6c2d 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -24,10 +24,7 @@
 #include "qemu/module.h"
 #include "qemu/queue.h"
 #include "migration/vmstate.h"
-#include "hw/pci/pci.h"
 #include "hw/qdev-properties.h"
-#include "hw/pci/msi.h"
-#include "hw/pci/msix.h"
 #include "trace.h"
 #include "qapi/error.h"
 
@@ -56,8 +53,6 @@
 #define OFF_OPER        LEN_CAP
 #define OFF_RUNTIME     0x1000
 #define OFF_DOORBELL    0x2000
-#define OFF_MSIX_TABLE  0x3000
-#define OFF_MSIX_PBA    0x3800
 /* must be power of 2 */
 #define LEN_REGS        0x4000
 
@@ -547,54 +542,28 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
     return &xhci->ports[index];
 }
 
-static void xhci_intx_update(XHCIState *xhci)
+static void xhci_intr_update(XHCIState *xhci, int v)
 {
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
     int level = 0;
 
-    if (msix_enabled(pci_dev) ||
-        msi_enabled(pci_dev)) {
-        return;
-    }
-
-    if (xhci->intr[0].iman & IMAN_IP &&
-        xhci->intr[0].iman & IMAN_IE &&
-        xhci->usbcmd & USBCMD_INTE) {
-        level = 1;
-    }
-
-    trace_usb_xhci_irq_intx(level);
-    pci_set_irq(pci_dev, level);
-}
-
-static void xhci_msix_update(XHCIState *xhci, int v)
-{
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
-    bool enabled;
-
-    if (!msix_enabled(pci_dev)) {
-        return;
-    }
-
-    enabled = xhci->intr[v].iman & IMAN_IE;
-    if (enabled == xhci->intr[v].msix_used) {
-        return;
+    if (v == 0) {
+        if (xhci->intr[0].iman & IMAN_IP &&
+            xhci->intr[0].iman & IMAN_IE &&
+            xhci->usbcmd & USBCMD_INTE) {
+            level = 1;
+        }
+        if (xhci->intr_raise) {
+            xhci->intr_raise(xhci, 0, level);
+        }
     }
-
-    if (enabled) {
-        trace_usb_xhci_irq_msix_use(v);
-        msix_vector_use(pci_dev, v);
-        xhci->intr[v].msix_used = true;
-    } else {
-        trace_usb_xhci_irq_msix_unuse(v);
-        msix_vector_unuse(pci_dev, v);
-        xhci->intr[v].msix_used = false;
+    if (xhci->intr_update) {
+        xhci->intr_update(xhci, v,
+                     xhci->intr[v].iman & IMAN_IE);
     }
 }
 
 static void xhci_intr_raise(XHCIState *xhci, int v)
 {
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
     bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
 
     xhci->intr[v].erdp_low |= ERDP_EHB;
@@ -611,22 +580,8 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
     if (!(xhci->usbcmd & USBCMD_INTE)) {
         return;
     }
-
-    if (msix_enabled(pci_dev)) {
-        trace_usb_xhci_irq_msix(v);
-        msix_notify(pci_dev, v);
-        return;
-    }
-
-    if (msi_enabled(pci_dev)) {
-        trace_usb_xhci_irq_msi(v);
-        msi_notify(pci_dev, v);
-        return;
-    }
-
-    if (v == 0) {
-        trace_usb_xhci_irq_intx(1);
-        pci_irq_assert(pci_dev);
+    if (xhci->intr_raise) {
+        xhci->intr_raise(xhci, v, true);
     }
 }
 
@@ -2714,7 +2669,6 @@ static void xhci_reset(DeviceState *dev)
         xhci->intr[i].erstba_high = 0;
         xhci->intr[i].erdp_low = 0;
         xhci->intr[i].erdp_high = 0;
-        xhci->intr[i].msix_used = 0;
 
         xhci->intr[i].er_ep_idx = 0;
         xhci->intr[i].er_pcs = 1;
@@ -2936,8 +2890,7 @@ static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
 static void xhci_oper_write(void *ptr, hwaddr reg,
                             uint64_t val, unsigned size)
 {
-    XHCIState *xhci = ptr;
-    DeviceState *d = DEVICE(ptr);
+    XHCIState *xhci = XHCI(ptr);
 
     trace_usb_xhci_oper_write(reg, val);
 
@@ -2959,15 +2912,15 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
         xhci->usbcmd = val & 0xc0f;
         xhci_mfwrap_update(xhci);
         if (val & USBCMD_HCRST) {
-            xhci_reset(d);
+            xhci_reset(DEVICE(xhci));
         }
-        xhci_intx_update(xhci);
+        xhci_intr_update(xhci, 0);
         break;
 
     case 0x04: /* USBSTS */
         /* these bits are write-1-to-clear */
         xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
-        xhci_intx_update(xhci);
+        xhci_intr_update(xhci, 0);
         break;
 
     case 0x14: /* DNCTRL */
@@ -3070,10 +3023,7 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
         }
         intr->iman &= ~IMAN_IE;
         intr->iman |= val & IMAN_IE;
-        if (v == 0) {
-            xhci_intx_update(xhci);
-        }
-        xhci_msix_update(xhci, v);
+        xhci_intr_update(xhci, v);
         break;
     case 0x04: /* IMOD */
         intr->imod = val;
@@ -3318,7 +3268,6 @@ static USBBusOps xhci_bus_ops = {
 
 static void usb_xhci_init(XHCIState *xhci)
 {
-    DeviceState *dev = DEVICE(xhci);
     XHCIPort *port;
     unsigned int i, usbports, speedmask;
 
@@ -3333,7 +3282,7 @@ static void usb_xhci_init(XHCIState *xhci)
     usbports = MAX(xhci->numports_2, xhci->numports_3);
     xhci->numports = xhci->numports_2 + xhci->numports_3;
 
-    usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
+    usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
 
     for (i = 0; i < usbports; i++) {
         speedmask = 0;
@@ -3373,21 +3322,12 @@ static void usb_xhci_init(XHCIState *xhci)
     }
 }
 
-static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
+static void usb_xhci_realize(DeviceState *dev, Error **errp)
 {
-    int i, ret;
-    Error *err = NULL;
+    int i;
 
     XHCIState *xhci = XHCI(dev);
 
-    dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
-    dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
-    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
-    dev->config[0x60] = 0x30; /* release number */
-
-    if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
-        xhci->nec_quirks = true;
-    }
     if (xhci->numintrs > MAXINTRS) {
         xhci->numintrs = MAXINTRS;
     }
@@ -3409,36 +3349,18 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
         xhci->max_pstreams_mask = 0;
     }
 
-    if (xhci->msi != ON_OFF_AUTO_OFF) {
-        ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
-        /* Any error other than -ENOTSUP(board's MSI support is broken)
-         * is a programming error */
-        assert(!ret || ret == -ENOTSUP);
-        if (ret && xhci->msi == ON_OFF_AUTO_ON) {
-            /* Can't satisfy user's explicit msi=on request, fail */
-            error_append_hint(&err, "You have to use msi=auto (default) or "
-                    "msi=off with this machine type.\n");
-            error_propagate(errp, err);
-            return;
-        }
-        assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
-        /* With msi=auto, we fall back to MSI off silently */
-        error_free(err);
-    }
-
     usb_xhci_init(xhci);
-    xhci->as = pci_get_address_space(dev);
     xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
 
-    memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
-    memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
+    memory_region_init(&xhci->mem, OBJECT(dev), "xhci", LEN_REGS);
+    memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
                           "capabilities", LEN_CAP);
-    memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
+    memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
                           "operational", 0x400);
-    memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
-                          "runtime", LEN_RUNTIME);
-    memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
-                          "doorbell", LEN_DOORBELL);
+    memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
+                           xhci, "runtime", LEN_RUNTIME);
+    memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
+                           xhci, "doorbell", LEN_DOORBELL);
 
     memory_region_add_subregion(&xhci->mem, 0,            &xhci->mem_cap);
     memory_region_add_subregion(&xhci->mem, OFF_OPER,     &xhci->mem_oper);
@@ -3449,31 +3371,13 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
         XHCIPort *port = &xhci->ports[i];
         uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
         port->xhci = xhci;
-        memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
+        memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
                               port->name, 0x10);
         memory_region_add_subregion(&xhci->mem, offset, &port->mem);
     }
-
-    pci_register_bar(dev, 0,
-                     PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
-                     &xhci->mem);
-
-    if (pci_bus_is_express(pci_get_bus(dev)) ||
-        xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
-        ret = pcie_endpoint_cap_init(dev, 0xa0);
-        assert(ret > 0);
-    }
-
-    if (xhci->msix != ON_OFF_AUTO_OFF) {
-        /* TODO check for errors, and should fail when msix=on */
-        msix_init(dev, xhci->numintrs,
-                  &xhci->mem, 0, OFF_MSIX_TABLE,
-                  &xhci->mem, 0, OFF_MSIX_PBA,
-                  0x90, NULL);
-    }
 }
 
-static void usb_xhci_exit(PCIDevice *dev)
+static void usb_xhci_unrealize(DeviceState *dev)
 {
     int i;
     XHCIState *xhci = XHCI(dev);
@@ -3500,19 +3404,12 @@ static void usb_xhci_exit(PCIDevice *dev)
         memory_region_del_subregion(&xhci->mem, &port->mem);
     }
 
-    /* destroy msix memory region */
-    if (dev->msix_table && dev->msix_pba
-        && dev->msix_entry_used) {
-        msix_uninit(dev, &xhci->mem, &xhci->mem);
-    }
-
     usb_bus_release(&xhci->bus);
 }
 
 static int usb_xhci_post_load(void *opaque, int version_id)
 {
     XHCIState *xhci = opaque;
-    PCIDevice *pci_dev = PCI_DEVICE(xhci);
     XHCISlot *slot;
     XHCIEPContext *epctx;
     dma_addr_t dcbaap, pctx;
@@ -3558,11 +3455,7 @@ static int usb_xhci_post_load(void *opaque, int version_id)
     }
 
     for (intr = 0; intr < xhci->numintrs; intr++) {
-        if (xhci->intr[intr].msix_used) {
-            msix_vector_use(pci_dev, intr);
-        } else {
-            msix_vector_unuse(pci_dev, intr);
-        }
+        xhci_intr_update(xhci, intr);
     }
 
     return 0;
@@ -3631,7 +3524,6 @@ static const VMStateDescription vmstate_xhci_intr = {
         VMSTATE_UINT32(erdp_high,     XHCIInterrupter),
 
         /* state */
-        VMSTATE_BOOL(msix_used,       XHCIInterrupter),
         VMSTATE_BOOL(er_pcs,          XHCIInterrupter),
         VMSTATE_UINT64(er_start,      XHCIInterrupter),
         VMSTATE_UINT32(er_size,       XHCIInterrupter),
@@ -3654,9 +3546,6 @@ static const VMStateDescription vmstate_xhci = {
     .version_id = 1,
     .post_load = usb_xhci_post_load,
     .fields = (VMStateField[]) {
-        VMSTATE_PCI_DEVICE(parent_obj, XHCIState),
-        VMSTATE_MSIX(parent_obj, XHCIState),
-
         VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
                                      vmstate_xhci_port, XHCIPort),
         VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
@@ -3688,34 +3577,28 @@ static Property xhci_properties[] = {
                     XHCI_FLAG_ENABLE_STREAMS, true),
     DEFINE_PROP_UINT32("p2",    XHCIState, numports_2, 4),
     DEFINE_PROP_UINT32("p3",    XHCIState, numports_3, 4),
+    DEFINE_PROP_LINK("host",    XHCIState, hostOpaque, TYPE_DEVICE,
+                     DeviceState *),
     DEFINE_PROP_END_OF_LIST(),
 };
 
 static void xhci_class_init(ObjectClass *klass, void *data)
 {
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
     DeviceClass *dc = DEVICE_CLASS(klass);
 
+    dc->realize = usb_xhci_realize;
+    dc->unrealize = usb_xhci_unrealize;
+    dc->reset   = xhci_reset;
     dc->vmsd    = &vmstate_xhci;
     device_class_set_props(dc, xhci_properties);
-    dc->reset   = xhci_reset;
-    set_bit(DEVICE_CATEGORY_USB, dc->categories);
-    k->realize      = usb_xhci_realize;
-    k->exit         = usb_xhci_exit;
-    k->class_id     = PCI_CLASS_SERIAL_USB;
+    dc->user_creatable = false;
 }
 
 static const TypeInfo xhci_info = {
     .name          = TYPE_XHCI,
-    .parent        = TYPE_PCI_DEVICE,
+    .parent        = TYPE_DEVICE,
     .instance_size = sizeof(XHCIState),
     .class_init    = xhci_class_init,
-    .abstract      = true,
-    .interfaces = (InterfaceInfo[]) {
-        { INTERFACE_PCIE_DEVICE },
-        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
-        { }
-    },
 };
 
 static void xhci_register_types(void)
diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
index dd5fcd4..fea1761 100644
--- a/hw/usb/hcd-xhci.h
+++ b/hw/usb/hcd-xhci.h
@@ -171,7 +171,7 @@ typedef struct XHCIInterrupter {
     uint32_t erdp_low;
     uint32_t erdp_high;
 
-    bool msix_used, er_pcs;
+    bool er_pcs;
 
     dma_addr_t er_start;
     uint32_t er_size;
@@ -185,10 +185,8 @@ typedef struct XHCIInterrupter {
 
 } XHCIInterrupter;
 
-struct XHCIState {
-    /*< private >*/
-    PCIDevice parent_obj;
-    /*< public >*/
+typedef struct XHCIState {
+    DeviceState parent;
 
     USBBus bus;
     MemoryRegion mem;
@@ -205,8 +203,9 @@ struct XHCIState {
     uint32_t numslots;
     uint32_t flags;
     uint32_t max_pstreams_mask;
-    OnOffAuto msi;
-    OnOffAuto msix;
+    void (*intr_update)(XHCIState *s, int n, bool enable);
+    void (*intr_raise)(XHCIState *s, int n, bool level);
+    DeviceState *hostOpaque;
 
     /* Operational Registers */
     uint32_t usbcmd;
@@ -231,7 +230,7 @@ struct XHCIState {
     XHCIRing cmd_ring;
 
     bool nec_quirks;
-};
+} XHCIState;
 
 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit);
 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit);
-- 
2.7.4

[PATCH v4 4/7] usb: hcd-xhci-sysbus: Attach xhci to sysbus device

[Sai Pavan Boddu]

Use XHCI as sysbus device, add memory region property to get the
address space instance for dma read/write.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/usb/Kconfig           |  5 +++
 hw/usb/Makefile.objs     |  1 +
 hw/usb/hcd-xhci-sysbus.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++
 hw/usb/hcd-xhci-sysbus.h | 32 ++++++++++++++++
 hw/usb/hcd-xhci.h        |  1 +
 5 files changed, 138 insertions(+)
 create mode 100644 hw/usb/hcd-xhci-sysbus.c
 create mode 100644 hw/usb/hcd-xhci-sysbus.h

diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index d9965c1..a251501 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -48,6 +48,11 @@ config USB_XHCI_NEC
     depends on PCI
     select USB_XHCI
 
+config USB_XHCI_SYSBUS
+    bool
+    default y if USB_XHCI
+    select USB
+
 config USB_MUSB
     bool
     select USB
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index 029b040..f16a3c3 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
 common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
 common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
 common-obj-$(CONFIG_USB_XHCI_PCI) += hcd-xhci-pci.o
+common-obj-$(CONFIG_USB_XHCI_SYSBUS) += hcd-xhci-sysbus.o
 common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
 common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
 
diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c
new file mode 100644
index 0000000..d5b4656
--- /dev/null
+++ b/hw/usb/hcd-xhci-sysbus.c
@@ -0,0 +1,99 @@
+/*
+ * USB xHCI controller for system-bus interface
+ * Based on hcd-echi-sysbus.c
+
+ * SPDX-FileCopyrightText: 2020 Xilinx
+ * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+#include "qapi/error.h"
+#include "hcd-xhci-sysbus.h"
+#include "hw/irq.h"
+
+static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
+{
+    XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
+
+    qemu_set_irq(s->irq[n], level);
+}
+
+void xhci_sysbus_reset(DeviceState *dev)
+{
+    XHCISysbusState *s = XHCI_SYSBUS(dev);
+
+    device_legacy_reset(DEVICE(&s->xhci));
+}
+
+static void xhci_sysbus_realize(DeviceState *dev, Error **errp)
+{
+    XHCISysbusState *s = XHCI_SYSBUS(dev);
+    Error *err = NULL;
+
+    object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
+    object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    s->irq = g_new0(qemu_irq, s->xhci.numintrs);
+    qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ,
+                             s->xhci.numintrs);
+    if (s->xhci.dma_mr) {
+        s->xhci.as =  g_malloc0(sizeof(AddressSpace));
+        address_space_init(s->xhci.as, s->xhci.dma_mr, NULL);
+    } else {
+        s->xhci.as = &address_space_memory;
+    }
+
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem);
+}
+
+static void xhci_sysbus_instance_init(Object *obj)
+{
+    XHCISysbusState *s = XHCI_SYSBUS(obj);
+
+    object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
+    qdev_alias_all_properties(DEVICE(&s->xhci), obj);
+
+    object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
+                             (Object **)&s->xhci.dma_mr,
+                             qdev_prop_allow_set_link_before_realize,
+                             OBJ_PROP_LINK_STRONG);
+    s->xhci.intr_update = NULL;
+    s->xhci.intr_raise = xhci_sysbus_intr_raise;
+}
+
+static Property xhci_sysbus_props[] = {
+    DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, MAXINTRS),
+    DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, MAXSLOTS),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xhci_sysbus_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = xhci_sysbus_reset;
+    dc->realize = xhci_sysbus_realize;
+    device_class_set_props(dc, xhci_sysbus_props);
+}
+
+static const TypeInfo xhci_sysbus_info = {
+    .name          = TYPE_XHCI_SYSBUS,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(XHCISysbusState),
+    .class_init    = xhci_sysbus_class_init,
+    .instance_init = xhci_sysbus_instance_init
+};
+
+static void xhci_sysbus_register_types(void)
+{
+    type_register_static(&xhci_sysbus_info);
+}
+
+type_init(xhci_sysbus_register_types);
diff --git a/hw/usb/hcd-xhci-sysbus.h b/hw/usb/hcd-xhci-sysbus.h
new file mode 100644
index 0000000..a308753
--- /dev/null
+++ b/hw/usb/hcd-xhci-sysbus.h
@@ -0,0 +1,32 @@
+/*
+ * USB xHCI controller for system-bus interface
+ *
+ * SPDX-FileCopyrightText: 2020 Xilinx
+ * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
+ * SPDX-sourceInfo: Based on hcd-echi-sysbus
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_USB_HCD_XHCI_SYSBUS_H
+#define HW_USB_HCD_XHCI_SYSBUS_H
+
+#include "hw/usb.h"
+#include "hcd-xhci.h"
+#include "hw/sysbus.h"
+
+#define TYPE_XHCI_SYSBUS "sysbus-xhci"
+#define XHCI_SYSBUS(obj) \
+    OBJECT_CHECK(XHCISysbusState, (obj), TYPE_XHCI_SYSBUS)
+
+
+typedef struct XHCISysbusState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+    XHCIState xhci;
+    qemu_irq *irq;
+} XHCISysbusState;
+
+void xhci_sysbus_reset(DeviceState *dev);
+#endif
diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
index fea1761..b951df4 100644
--- a/hw/usb/hcd-xhci.h
+++ b/hw/usb/hcd-xhci.h
@@ -190,6 +190,7 @@ typedef struct XHCIState {
 
     USBBus bus;
     MemoryRegion mem;
+    MemoryRegion *dma_mr;
     AddressSpace *as;
     MemoryRegion mem_cap;
     MemoryRegion mem_oper;
-- 
2.7.4

Re: [PATCH v4 4/7] usb: hcd-xhci-sysbus: Attach xhci to sysbus device

[Philippe Mathieu-Daudé]

On 8/28/20 9:19 PM, Sai Pavan Boddu wrote:
> Use XHCI as sysbus device, add memory region property to get the
> address space instance for dma read/write.
> 
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
>  hw/usb/Kconfig           |  5 +++
>  hw/usb/Makefile.objs     |  1 +
>  hw/usb/hcd-xhci-sysbus.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/usb/hcd-xhci-sysbus.h | 32 ++++++++++++++++

Please consider using scripts/git.orderfile to ease review
(less scrolling required by reviewer).

>  hw/usb/hcd-xhci.h        |  1 +
>  5 files changed, 138 insertions(+)
...

> diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c
> new file mode 100644
> index 0000000..d5b4656
> --- /dev/null
> +++ b/hw/usb/hcd-xhci-sysbus.c
> @@ -0,0 +1,99 @@
> +/*
> + * USB xHCI controller for system-bus interface
> + * Based on hcd-echi-sysbus.c
> +
> + * SPDX-FileCopyrightText: 2020 Xilinx
> + * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#include "qemu/osdep.h"
> +#include "hw/qdev-properties.h"
> +#include "migration/vmstate.h"
> +#include "trace.h"
> +#include "qapi/error.h"
> +#include "hcd-xhci-sysbus.h"
> +#include "hw/irq.h"
> +
> +static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
> +{
> +    XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
> +
> +    qemu_set_irq(s->irq[n], level);
> +}
> +
> +void xhci_sysbus_reset(DeviceState *dev)
> +{
> +    XHCISysbusState *s = XHCI_SYSBUS(dev);
> +
> +    device_legacy_reset(DEVICE(&s->xhci));

Documentation comment:

"This function is deprecated and will be removed when it becomes unused.
 Please use device_cold_reset() now."

> +}
> +

[PATCH v4 5/7] misc: Add versal-usb2-regs module

[Sai Pavan Boddu]

This is a dummy module to emulate control registers of versal usb2
controller.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
---
 hw/misc/Makefile.objs                   |   1 +
 hw/misc/xlnx-versal-usb2-regs.c         | 224 ++++++++++++++++++++++++++++++++
 include/hw/misc/xlnx-versal-usb2-regs.h |  43 ++++++
 3 files changed, 268 insertions(+)
 create mode 100644 hw/misc/xlnx-versal-usb2-regs.c
 create mode 100644 include/hw/misc/xlnx-versal-usb2-regs.h

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 6be3d25..6d12ca7 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -64,6 +64,7 @@ common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
 common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
 common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
+common-obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal-usb2-regs.o
 common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
 common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
 common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o
diff --git a/hw/misc/xlnx-versal-usb2-regs.c b/hw/misc/xlnx-versal-usb2-regs.c
new file mode 100644
index 0000000..244cda2
--- /dev/null
+++ b/hw/misc/xlnx-versal-usb2-regs.c
@@ -0,0 +1,224 @@
+/*
+ * QEMU model of the XlnxUsb2Regs Register control block/Status for USB2.0 IP
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Autogenerated by xregqemu.py 2020-04-08.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "migration/vmstate.h"
+#include "hw/misc/xlnx-versal-usb2-regs.h"
+
+#ifndef XILINX_USB2_REGS_ERR_DEBUG
+#define XILINX_USB2_REGS_ERR_DEBUG 0
+#endif
+
+#define TYPE_XILINX_USB2_REGS "xlnx.usb2_regs"
+
+#define XILINX_USB2_REGS(obj) \
+     OBJECT_CHECK(XlnxUsb2Regs, (obj), TYPE_XILINX_USB2_REGS)
+
+REG32(BUS_FILTER, 0x30)
+    FIELD(BUS_FILTER, BYPASS, 0, 4)
+REG32(PORT, 0x34)
+    FIELD(PORT, HOST_SMI_BAR_WR, 4, 1)
+    FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1)
+    FIELD(PORT, HOST_MSI_ENABLE, 2, 1)
+    FIELD(PORT, PWR_CTRL_PRSNT, 1, 1)
+    FIELD(PORT, HUB_PERM_ATTACH, 0, 1)
+REG32(JITTER_ADJUST, 0x38)
+    FIELD(JITTER_ADJUST, FLADJ, 0, 6)
+REG32(BIGENDIAN, 0x40)
+    FIELD(BIGENDIAN, ENDIAN_GS, 0, 1)
+REG32(COHERENCY, 0x44)
+    FIELD(COHERENCY, USB_COHERENCY, 0, 1)
+REG32(XHC_BME, 0x48)
+    FIELD(XHC_BME, XHC_BME, 0, 1)
+REG32(REG_CTRL, 0x60)
+    FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x64)
+    FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1)
+    FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1)
+REG32(IR_MASK, 0x68)
+    FIELD(IR_MASK, HOST_SYS_ERR, 1, 1)
+    FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1)
+REG32(IR_ENABLE, 0x6c)
+    FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1)
+    FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1)
+REG32(IR_DISABLE, 0x70)
+    FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1)
+    FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1)
+REG32(USB3, 0x78)
+
+static void ir_update_irq(XlnxUsb2Regs *s)
+{
+    bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+    qemu_set_irq(s->irq_ir, pending);
+}
+
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxUsb2Regs *s = XILINX_USB2_REGS(reg->opaque);
+    /*
+     * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
+     * May be combine both the modules.
+     */
+    ir_update_irq(s);
+}
+
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxUsb2Regs *s = XILINX_USB2_REGS(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_IR_MASK] &= ~val;
+    ir_update_irq(s);
+    return 0;
+}
+
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxUsb2Regs *s = XILINX_USB2_REGS(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_IR_MASK] |= val;
+    ir_update_irq(s);
+    return 0;
+}
+
+static const RegisterAccessInfo usb2_regs_regs_info[] = {
+    {   .name = "BUS_FILTER",  .addr = A_BUS_FILTER,
+        .rsvd = 0xfffffff0,
+    },{ .name = "PORT",  .addr = A_PORT,
+        .rsvd = 0xffffffe0,
+    },{ .name = "JITTER_ADJUST",  .addr = A_JITTER_ADJUST,
+        .reset = 0x20,
+        .rsvd = 0xffffffc0,
+    },{ .name = "BIGENDIAN",  .addr = A_BIGENDIAN,
+        .rsvd = 0xfffffffe,
+    },{ .name = "COHERENCY",  .addr = A_COHERENCY,
+        .rsvd = 0xfffffffe,
+    },{ .name = "XHC_BME",  .addr = A_XHC_BME,
+        .reset = 0x1,
+        .rsvd = 0xfffffffe,
+    },{ .name = "REG_CTRL",  .addr = A_REG_CTRL,
+        .rsvd = 0xfffffffe,
+    },{ .name = "IR_STATUS",  .addr = A_IR_STATUS,
+        .rsvd = 0xfffffffc,
+        .w1c = 0x3,
+        .post_write = ir_status_postw,
+    },{ .name = "IR_MASK",  .addr = A_IR_MASK,
+        .reset = 0x3,
+        .rsvd = 0xfffffffc,
+        .ro = 0x3,
+    },{ .name = "IR_ENABLE",  .addr = A_IR_ENABLE,
+        .rsvd = 0xfffffffc,
+        .pre_write = ir_enable_prew,
+    },{ .name = "IR_DISABLE",  .addr = A_IR_DISABLE,
+        .rsvd = 0xfffffffc,
+        .pre_write = ir_disable_prew,
+    },{ .name = "USB3",  .addr = A_USB3,
+    }
+};
+
+static void usb2_regs_reset(DeviceState *dev)
+{
+    XlnxUsb2Regs *s = XILINX_USB2_REGS(dev);
+    unsigned int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+        register_reset(&s->regs_info[i]);
+    }
+
+    ir_update_irq(s);
+}
+
+static const MemoryRegionOps usb2_regs_ops = {
+    .read = register_read_memory,
+    .write = register_write_memory,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static void usb2_regs_init(Object *obj)
+{
+    XlnxUsb2Regs *s = XILINX_USB2_REGS(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    RegisterInfoArray *reg_array;
+
+    memory_region_init(&s->iomem, obj, TYPE_XILINX_USB2_REGS,
+                       USB2_REGS_R_MAX * 4);
+    reg_array =
+        register_init_block32(DEVICE(obj), usb2_regs_regs_info,
+                              ARRAY_SIZE(usb2_regs_regs_info),
+                              s->regs_info, s->regs,
+                              &usb2_regs_ops,
+                              XILINX_USB2_REGS_ERR_DEBUG,
+                              USB2_REGS_R_MAX * 4);
+    memory_region_add_subregion(&s->iomem,
+                                0x0,
+                                &reg_array->mem);
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(sbd, &s->irq_ir);
+}
+
+static const VMStateDescription vmstate_usb2_regs = {
+    .name = TYPE_XILINX_USB2_REGS,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, XlnxUsb2Regs, USB2_REGS_R_MAX),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static void usb2_regs_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = usb2_regs_reset;
+    dc->vmsd = &vmstate_usb2_regs;
+}
+
+static const TypeInfo usb2_regs_info = {
+    .name          = TYPE_XILINX_USB2_REGS,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(XlnxUsb2Regs),
+    .class_init    = usb2_regs_class_init,
+    .instance_init = usb2_regs_init,
+};
+
+static void usb2_regs_register_types(void)
+{
+    type_register_static(&usb2_regs_info);
+}
+
+type_init(usb2_regs_register_types)
diff --git a/include/hw/misc/xlnx-versal-usb2-regs.h b/include/hw/misc/xlnx-versal-usb2-regs.h
new file mode 100644
index 0000000..4c5dc02
--- /dev/null
+++ b/include/hw/misc/xlnx-versal-usb2-regs.h
@@ -0,0 +1,43 @@
+/*
+ * QEMU model of the XlnxUsb2Regs Register control block/Status for USB2.0 IP
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Autogenerated by xregqemu.py 2020-04-08.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef _XLNX_USB2_REGS_H_
+#define _XLNX_USB2_REGS_H_
+
+#define USB2_REGS_R_MAX ((0x78 / 4) + 1)
+
+typedef struct XlnxUsb2Regs {
+    SysBusDevice parent_obj;
+    MemoryRegion iomem;
+    qemu_irq irq_ir;
+
+    uint32_t regs[USB2_REGS_R_MAX];
+    RegisterInfo regs_info[USB2_REGS_R_MAX];
+} XlnxUsb2Regs;
+
+#endif
+
+
-- 
2.7.4

Re: [PATCH v4 5/7] misc: Add versal-usb2-regs module

[Gerd Hoffmann]

On Sat, Aug 29, 2020 at 12:49:38AM +0530, Sai Pavan Boddu wrote:
> This is a dummy module to emulate control registers of versal usb2
> controller.

--verbose please.  xhci supports all usb speeds, including usb2.

So why this hardware is here, what does it on a real device and what is
the emulation doing?  "dummy" sounds like it does just enough to make
the guest driver happy, probably pretending nothing is connected?

thanks,
  Gerd

RE: [PATCH v4 5/7] misc: Add versal-usb2-regs module

[Sai Pavan Boddu]

Hi Gred,

> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Monday, August 31, 2020 12:33 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Markus Armbruster
> <armbru@redhat.com>; 'Marc-André Lureau'
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Edgar Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>; qemu-devel@nongnu.org; Alistair Francis
> <alistair.francis@wdc.com>; Eduardo Habkost <ehabkost@redhat.com>;
> Ying Fang <fangying1@huawei.com>; 'Philippe Mathieu-Daudé'
> <philmd@redhat.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 5/7] misc: Add versal-usb2-regs module
> 
> On Sat, Aug 29, 2020 at 12:49:38AM +0530, Sai Pavan Boddu wrote:
> > This is a dummy module to emulate control registers of versal usb2
> > controller.
> 
> --verbose please.  xhci supports all usb speeds, including usb2.
[Sai Pavan Boddu] This module is has soc specific control/status register to control the phy-reset, adjust frame length time  and coherency properties for the transactions.

> 
> So why this hardware is here, what does it on a real device and what is the
> emulation doing?  "dummy" sounds like it does just enough to make the
> guest driver happy, probably pretending nothing is connected?
Yes, this is added to make guest happy.

I will the commit message with more info

Regards,
Sai Pavan
> 
> thanks,
>   Gerd

[PATCH v4 6/7] usb: Add DWC3 model

[Sai Pavan Boddu]

From: Vikram Garhwal <fnu.vikram@xilinx.com>

This patch adds skeleton model of dwc3 usb controller attached to
xhci-sysbus device.

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/usb/Makefile.objs      |   1 +
 hw/usb/hcd-dwc3.c         | 606 ++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/usb/hcd-dwc3.h |  58 +++++
 3 files changed, 665 insertions(+)
 create mode 100644 hw/usb/hcd-dwc3.c
 create mode 100644 include/hw/usb/hcd-dwc3.h

diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index f16a3c3..af0487b 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -15,6 +15,7 @@ common-obj-$(CONFIG_USB_XHCI_PCI) += hcd-xhci-pci.o
 common-obj-$(CONFIG_USB_XHCI_SYSBUS) += hcd-xhci-sysbus.o
 common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
 common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
+common-obj-$(CONFIG_XLNX_VERSAL) += hcd-dwc3.o
 
 common-obj-$(CONFIG_TUSB6010) += tusb6010.o
 common-obj-$(CONFIG_IMX)      += chipidea.o
diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c
new file mode 100644
index 0000000..1c2a927
--- /dev/null
+++ b/hw/usb/hcd-dwc3.c
@@ -0,0 +1,606 @@
+/*
+ * QEMU model of the USB DWC3 host controller emulation.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written by Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/usb/hcd-dwc3.h"
+#include "qapi/error.h"
+
+#ifndef USB_DWC3_ERR_DEBUG
+#define USB_DWC3_ERR_DEBUG 0
+#endif
+
+#define HOST_MODE           1
+#define FIFO_LEN         0x1000
+
+REG32(GSBUSCFG0, 0x00)
+    FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4)
+    FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4)
+    FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4)
+    FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
+    FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4)
+    FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
+    FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
+    FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2)
+    FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
+    FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
+    FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1)
+    FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1)
+    FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1)
+    FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1)
+    FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1)
+    FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1)
+REG32(GSBUSCFG1, 0x04)
+    FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19)
+    FIELD(GSBUSCFG1, EN1KPAGE, 12, 1)
+    FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4)
+    FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8)
+REG32(GTXTHRCFG, 0x08)
+    FIELD(GTXTHRCFG, RESERVED_31, 31, 1)
+    FIELD(GTXTHRCFG, RESERVED_30, 30, 1)
+    FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1)
+    FIELD(GTXTHRCFG, RESERVED_28, 28, 1)
+    FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4)
+    FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8)
+    FIELD(GTXTHRCFG, RESERVED_15, 15, 1)
+    FIELD(GTXTHRCFG, RESERVED_14, 14, 1)
+    FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3)
+    FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11)
+REG32(GRXTHRCFG, 0x0c)
+    FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2)
+    FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1)
+    FIELD(GRXTHRCFG, RESERVED_28, 28, 1)
+    FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4)
+    FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5)
+    FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3)
+    FIELD(GRXTHRCFG, RESERVED_15, 15, 1)
+    FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2)
+    FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13)
+REG32(GCTL, 0x10)
+    FIELD(GCTL, PWRDNSCALE, 19, 13)
+    FIELD(GCTL, MASTERFILTBYPASS, 18, 1)
+    FIELD(GCTL, BYPSSETADDR, 17, 1)
+    FIELD(GCTL, U2RSTECN, 16, 1)
+    FIELD(GCTL, FRMSCLDWN, 14, 2)
+    FIELD(GCTL, PRTCAPDIR, 12, 2)
+    FIELD(GCTL, CORESOFTRESET, 11, 1)
+    FIELD(GCTL, U1U2TIMERSCALE, 9, 1)
+    FIELD(GCTL, DEBUGATTACH, 8, 1)
+    FIELD(GCTL, RAMCLKSEL, 6, 2)
+    FIELD(GCTL, SCALEDOWN, 4, 2)
+    FIELD(GCTL, DISSCRAMBLE, 3, 1)
+    FIELD(GCTL, U2EXIT_LFPS, 2, 1)
+    FIELD(GCTL, GBLHIBERNATIONEN, 1, 1)
+    FIELD(GCTL, DSBLCLKGTNG, 0, 1)
+REG32(GPMSTS, 0x14)
+REG32(GSTS, 0x18)
+    FIELD(GSTS, CBELT, 20, 12)
+    FIELD(GSTS, RESERVED_19_12, 12, 8)
+    FIELD(GSTS, SSIC_IP, 11, 1)
+    FIELD(GSTS, OTG_IP, 10, 1)
+    FIELD(GSTS, BC_IP, 9, 1)
+    FIELD(GSTS, ADP_IP, 8, 1)
+    FIELD(GSTS, HOST_IP, 7, 1)
+    FIELD(GSTS, DEVICE_IP, 6, 1)
+    FIELD(GSTS, CSRTIMEOUT, 5, 1)
+    FIELD(GSTS, BUSERRADDRVLD, 4, 1)
+    FIELD(GSTS, RESERVED_3_2, 2, 2)
+    FIELD(GSTS, CURMOD, 0, 2)
+REG32(GUCTL1, 0x1c)
+    FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1)
+REG32(GSNPSID, 0x20)
+REG32(GGPIO, 0x24)
+    FIELD(GGPIO, GPO, 16, 16)
+    FIELD(GGPIO, GPI, 0, 16)
+REG32(GUID, 0x28)
+REG32(GUCTL, 0x2c)
+    FIELD(GUCTL, REFCLKPER, 22, 10)
+    FIELD(GUCTL, NOEXTRDL, 21, 1)
+    FIELD(GUCTL, RESERVED_20_18, 18, 3)
+    FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1)
+    FIELD(GUCTL, RESBWHSEPS, 16, 1)
+    FIELD(GUCTL, RESERVED_15, 15, 1)
+    FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1)
+    FIELD(GUCTL, ENOVERLAPCHK, 13, 1)
+    FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1)
+    FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1)
+    FIELD(GUCTL, DTCT, 9, 2)
+    FIELD(GUCTL, DTFT, 0, 9)
+REG32(GBUSERRADDRLO, 0x30)
+REG32(GBUSERRADDRHI, 0x34)
+REG32(GHWPARAMS0, 0x40)
+    FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8)
+    FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8)
+    FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8)
+    FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2)
+    FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3)
+    FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3)
+REG32(GHWPARAMS1, 0x44)
+    FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2)
+    FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1)
+    FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2)
+    FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6)
+    FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3)
+    FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3)
+    FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3)
+    FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3)
+    FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3)
+REG32(GHWPARAMS2, 0x48)
+REG32(GHWPARAMS3, 0x4c)
+    FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1)
+    FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8)
+    FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5)
+    FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6)
+    FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1)
+    FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1)
+    FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2)
+    FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2)
+    FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2)
+    FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2)
+    FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2)
+REG32(GHWPARAMS4, 0x50)
+    FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4)
+    FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4)
+    FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1)
+    FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1)
+    FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1)
+    FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4)
+    FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4)
+    FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1)
+    FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1)
+    FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2)
+    FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2)
+    FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1)
+    FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6)
+REG32(GHWPARAMS5, 0x54)
+    FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4)
+    FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6)
+    FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6)
+    FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6)
+    FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6)
+    FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4)
+REG32(GHWPARAMS6, 0x58)
+    FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16)
+    FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1)
+    FIELD(GHWPARAMS6, BCSUPPORT, 14, 1)
+    FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1)
+    FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1)
+    FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1)
+    FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1)
+    FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2)
+    FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1)
+    FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1)
+    FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6)
+REG32(GHWPARAMS7, 0x5c)
+    FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16)
+    FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16)
+REG32(GDBGFIFOSPACE, 0x60)
+    FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16)
+    FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7)
+    FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9)
+REG32(GUCTL2, 0x9c)
+    FIELD(GUCTL2, RESERVED_31_26, 26, 6)
+    FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7)
+    FIELD(GUCTL2, NOLOWPWRDUR, 15, 4)
+    FIELD(GUCTL2, RST_ACTBITLATER, 14, 1)
+    FIELD(GUCTL2, RESERVED_13, 13, 1)
+    FIELD(GUCTL2, DISABLECFC, 11, 1)
+REG32(GUSB2PHYCFG, 0x100)
+    FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1)
+    FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1)
+    FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1)
+    FIELD(GUSB2PHYCFG, LSTRD, 22, 3)
+    FIELD(GUSB2PHYCFG, LSIPD, 19, 3)
+    FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1)
+    FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1)
+    FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1)
+    FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1)
+    FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1)
+    FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4)
+    FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1)
+    FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1)
+    FIELD(GUSB2PHYCFG, PHYSEL, 7, 1)
+    FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1)
+    FIELD(GUSB2PHYCFG, FSINTF, 5, 1)
+    FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1)
+    FIELD(GUSB2PHYCFG, PHYIF, 3, 1)
+    FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3)
+REG32(GUSB2I2CCTL, 0x140)
+REG32(GUSB2PHYACC_ULPI, 0x180)
+    FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5)
+    FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1)
+    FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1)
+    FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1)
+    FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1)
+    FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1)
+    FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6)
+    FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8)
+    FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8)
+REG32(GTXFIFOSIZ0, 0x200)
+    FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16)
+    FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ1, 0x204)
+    FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16)
+    FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ2, 0x208)
+    FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16)
+    FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ3, 0x20c)
+    FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16)
+    FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ4, 0x210)
+    FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16)
+    FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ5, 0x214)
+    FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16)
+    FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16)
+REG32(GRXFIFOSIZ0, 0x280)
+    FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16)
+    FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16)
+REG32(GRXFIFOSIZ1, 0x284)
+    FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16)
+    FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16)
+REG32(GRXFIFOSIZ2, 0x288)
+    FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16)
+    FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16)
+REG32(GEVNTADRLO_0, 0x300)
+REG32(GEVNTADRHI_0, 0x304)
+REG32(GEVNTSIZ_0, 0x308)
+    FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1)
+    FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_0, 0x30c)
+    FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1)
+    FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16)
+REG32(GEVNTADRLO_1, 0x310)
+REG32(GEVNTADRHI_1, 0x314)
+REG32(GEVNTSIZ_1, 0x318)
+    FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1)
+    FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_1, 0x31c)
+    FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1)
+    FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16)
+REG32(GEVNTADRLO_2, 0x320)
+REG32(GEVNTADRHI_2, 0x324)
+REG32(GEVNTSIZ_2, 0x328)
+    FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1)
+    FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_2, 0x32c)
+    FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1)
+    FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16)
+REG32(GEVNTADRLO_3, 0x330)
+REG32(GEVNTADRHI_3, 0x334)
+REG32(GEVNTSIZ_3, 0x338)
+    FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1)
+    FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_3, 0x33c)
+    FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1)
+    FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15)
+    FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16)
+REG32(GHWPARAMS8, 0x500)
+REG32(GTXFIFOPRIDEV, 0x510)
+    FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26)
+    FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6)
+REG32(GTXFIFOPRIHST, 0x518)
+    FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29)
+    FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3)
+REG32(GRXFIFOPRIHST, 0x51c)
+    FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29)
+    FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3)
+REG32(GDMAHLRATIO, 0x524)
+    FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19)
+    FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5)
+    FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3)
+    FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5)
+REG32(GFLADJ, 0x530)
+    FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1)
+    FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7)
+    FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1)
+    FIELD(GFLADJ, RESERVED_22, 22, 1)
+    FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14)
+    FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1)
+    FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6)
+
+static void reset_csr(USBDWC3 * s)
+{
+    int i = 0;
+    /*
+     * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID,
+     * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY
+     * register as we don't implement them.
+     */
+    for (i = 0; i < R_GCTL; i++) {
+        register_reset(&s->regs_info[i]);
+    }
+
+    for (i = R_GCTL; i < R_GBUSERRADDRLO; i++) {
+        if (i == R_GUCTL1 || i == R_GPMSTS) {
+            register_reset(&s->regs_info[i]);
+        } else {
+            continue;
+        }
+    }
+
+    for (i = R_GBUSERRADDRLO; i < USB_DWC3_R_MAX; i++) {
+        register_reset(&s->regs_info[i]);
+    }
+
+    xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
+}
+
+static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64)
+{
+    USBDWC3 *s = USB_DWC3(reg->opaque);
+
+    if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) {
+        reset_csr(s);
+    }
+}
+
+static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64)
+{
+    USBDWC3 *s = USB_DWC3(reg->opaque);
+
+    s->regs[R_GUID] = s->cfg.dwc_usb3_user;
+}
+
+static const RegisterAccessInfo usb_dwc3_regs_info[] = {
+    {   .name = "GSBUSCFG0",  .addr = A_GSBUSCFG0,
+        .ro = 0xf300,
+    },{ .name = "GSBUSCFG1",  .addr = A_GSBUSCFG1,
+        .reset = 0x300,
+        .ro = 0xffffe0ff,
+    },{ .name = "GTXTHRCFG",  .addr = A_GTXTHRCFG,
+        .ro = 0xd000ffff,
+    },{ .name = "GRXTHRCFG",  .addr = A_GRXTHRCFG,
+        .ro = 0xd007e000,
+    },{ .name = "GCTL",  .addr = A_GCTL,
+        .reset = 0x30c13004, .post_write = usb_dwc3_gctl_postw,
+    },{ .name = "GPMSTS",  .addr = A_GPMSTS,
+        .ro = 0xfffffff,
+    },{ .name = "GSTS",  .addr = A_GSTS,
+        .reset = 0x7e800000,
+        .ro = 0xffffffcf,
+        .w1c = 0x30,
+    },{ .name = "GUCTL1",  .addr = A_GUCTL1,
+        .reset = 0x198a,
+        .ro = 0x7800,
+    },{ .name = "GSNPSID",  .addr = A_GSNPSID,
+        .reset = 0x5533330a,
+        .ro = 0xffffffff,
+    },{ .name = "GGPIO",  .addr = A_GGPIO,
+        .ro = 0xffff,
+    },{ .name = "GUID",  .addr = A_GUID,
+        .reset = 0x12345678, .post_write = usb_dwc3_guid_postw,
+    },{ .name = "GUCTL",  .addr = A_GUCTL,
+        .reset = 0x0c808010,
+        .ro = 0x1c8000,
+    },{ .name = "GBUSERRADDRLO",  .addr = A_GBUSERRADDRLO,
+        .ro = 0xffffffff,
+    },{ .name = "GBUSERRADDRHI",  .addr = A_GBUSERRADDRHI,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS0",  .addr = A_GHWPARAMS0,
+        .reset = 0x4020404a,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS1",  .addr = A_GHWPARAMS1,
+        .reset = 0x222493b,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS2",  .addr = A_GHWPARAMS2,
+        .reset = 0x12345678,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS3",  .addr = A_GHWPARAMS3,
+        .reset = 0x618c088,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS4",  .addr = A_GHWPARAMS4,
+        .reset = 0x47822004,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS5",  .addr = A_GHWPARAMS5,
+        .reset = 0x4202088,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS6",  .addr = A_GHWPARAMS6,
+        .reset = 0x7850c20,
+        .ro = 0xffffffff,
+    },{ .name = "GHWPARAMS7",  .addr = A_GHWPARAMS7,
+        .ro = 0xffffffff,
+    },{ .name = "GDBGFIFOSPACE",  .addr = A_GDBGFIFOSPACE,
+        .reset = 0xa0000,
+        .ro = 0xfffffe00,
+    },{ .name = "GUCTL2",  .addr = A_GUCTL2,
+        .reset = 0x40d,
+        .ro = 0x2000,
+    },{ .name = "GUSB2PHYCFG",  .addr = A_GUSB2PHYCFG,
+        .reset = 0x40102410,
+        .ro = 0x1e014030,
+    },{ .name = "GUSB2I2CCTL",  .addr = A_GUSB2I2CCTL,
+        .ro = 0xffffffff,
+    },{ .name = "GUSB2PHYACC_ULPI",  .addr = A_GUSB2PHYACC_ULPI,
+        .ro = 0xfd000000,
+    },{ .name = "GTXFIFOSIZ0",  .addr = A_GTXFIFOSIZ0,
+        .reset = 0x2c7000a,
+    },{ .name = "GTXFIFOSIZ1",  .addr = A_GTXFIFOSIZ1,
+        .reset = 0x2d10103,
+    },{ .name = "GTXFIFOSIZ2",  .addr = A_GTXFIFOSIZ2,
+        .reset = 0x3d40103,
+    },{ .name = "GTXFIFOSIZ3",  .addr = A_GTXFIFOSIZ3,
+        .reset = 0x4d70083,
+    },{ .name = "GTXFIFOSIZ4",  .addr = A_GTXFIFOSIZ4,
+        .reset = 0x55a0083,
+    },{ .name = "GTXFIFOSIZ5",  .addr = A_GTXFIFOSIZ5,
+        .reset = 0x5dd0083,
+    },{ .name = "GRXFIFOSIZ0",  .addr = A_GRXFIFOSIZ0,
+        .reset = 0x1c20105,
+    },{ .name = "GRXFIFOSIZ1",  .addr = A_GRXFIFOSIZ1,
+        .reset = 0x2c70000,
+    },{ .name = "GRXFIFOSIZ2",  .addr = A_GRXFIFOSIZ2,
+        .reset = 0x2c70000,
+    },{ .name = "GEVNTADRLO_0",  .addr = A_GEVNTADRLO_0,
+    },{ .name = "GEVNTADRHI_0",  .addr = A_GEVNTADRHI_0,
+    },{ .name = "GEVNTSIZ_0",  .addr = A_GEVNTSIZ_0,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTCOUNT_0",  .addr = A_GEVNTCOUNT_0,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTADRLO_1",  .addr = A_GEVNTADRLO_1,
+    },{ .name = "GEVNTADRHI_1",  .addr = A_GEVNTADRHI_1,
+    },{ .name = "GEVNTSIZ_1",  .addr = A_GEVNTSIZ_1,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTCOUNT_1",  .addr = A_GEVNTCOUNT_1,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTADRLO_2",  .addr = A_GEVNTADRLO_2,
+    },{ .name = "GEVNTADRHI_2",  .addr = A_GEVNTADRHI_2,
+    },{ .name = "GEVNTSIZ_2",  .addr = A_GEVNTSIZ_2,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTCOUNT_2",  .addr = A_GEVNTCOUNT_2,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTADRLO_3",  .addr = A_GEVNTADRLO_3,
+    },{ .name = "GEVNTADRHI_3",  .addr = A_GEVNTADRHI_3,
+    },{ .name = "GEVNTSIZ_3",  .addr = A_GEVNTSIZ_3,
+        .ro = 0x7fff0000,
+    },{ .name = "GEVNTCOUNT_3",  .addr = A_GEVNTCOUNT_3,
+        .ro = 0x7fff0000,
+    },{ .name = "GHWPARAMS8",  .addr = A_GHWPARAMS8,
+        .reset = 0x478,
+        .ro = 0xffffffff,
+    },{ .name = "GTXFIFOPRIDEV",  .addr = A_GTXFIFOPRIDEV,
+        .ro = 0xffffffc0,
+    },{ .name = "GTXFIFOPRIHST",  .addr = A_GTXFIFOPRIHST,
+        .ro = 0xfffffff8,
+    },{ .name = "GRXFIFOPRIHST",  .addr = A_GRXFIFOPRIHST,
+        .ro = 0xfffffff8,
+    },{ .name = "GDMAHLRATIO",  .addr = A_GDMAHLRATIO,
+        .ro = 0xffffe0e0,
+    },{ .name = "GFLADJ",  .addr = A_GFLADJ,
+        .reset = 0xc83f020,
+        .rsvd = 0x40,
+        .ro = 0x400040,
+    }
+};
+
+static void usb_dwc3_reset(DeviceState *dev)
+{
+    USBDWC3 *s = USB_DWC3(dev);
+    unsigned int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+        register_reset(&s->regs_info[i]);
+    }
+    xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
+}
+
+static const MemoryRegionOps usb_dwc3_ops = {
+    .read = register_read_memory,
+    .write = register_write_memory,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static void usb_dwc3_realize(DeviceState *dev, Error **errp)
+{
+    USBDWC3 *s = USB_DWC3(dev);
+    Error *err = NULL;
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+}
+
+static void usb_dwc3_init(Object *obj)
+{
+    USBDWC3 *s = USB_DWC3(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    RegisterInfoArray *reg_array;
+
+    memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, USB_DWC3_R_MAX * 4);
+    reg_array =
+        register_init_block32(DEVICE(obj), usb_dwc3_regs_info,
+                              ARRAY_SIZE(usb_dwc3_regs_info),
+                              s->regs_info, s->regs,
+                              &usb_dwc3_ops,
+                              USB_DWC3_ERR_DEBUG,
+                              USB_DWC3_R_MAX * 4);
+    memory_region_add_subregion(&s->iomem,
+                                0x0,
+                                &reg_array->mem);
+    sysbus_init_mmio(sbd, &s->iomem);
+    object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci,
+                            TYPE_XHCI_SYSBUS);
+    qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj);
+
+    s->cfg.mode = HOST_MODE;
+}
+
+static Property usb_dwc3_properties[] = {
+    DEFINE_PROP_BOOL("usb2-mode", USBDWC3, cfg.usb2_mode, false),
+    DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user,
+                       0x12345678),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void usb_dwc3_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = usb_dwc3_reset;
+    dc->realize = usb_dwc3_realize;
+    device_class_set_props(dc, usb_dwc3_properties);
+}
+
+static const TypeInfo usb_dwc3_info = {
+    .name          = TYPE_USB_DWC3,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(USBDWC3),
+    .class_init    = usb_dwc3_class_init,
+    .instance_init = usb_dwc3_init,
+};
+
+static void usb_dwc3_register_types(void)
+{
+    type_register_static(&usb_dwc3_info);
+}
+
+type_init(usb_dwc3_register_types)
diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h
new file mode 100644
index 0000000..09708d0
--- /dev/null
+++ b/include/hw/usb/hcd-dwc3.h
@@ -0,0 +1,58 @@
+/*
+ * QEMU model of the USB DWC3 host controller emulation.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written by Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#ifndef HCD_DWC3_H
+#define HCD_DWC3_H
+
+#include "hw/usb/hcd-xhci.h"
+#include "hw/usb/hcd-xhci-sysbus.h"
+
+#define TYPE_USB_DWC3 "usb_dwc3"
+
+#define USB_DWC3(obj) \
+     OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3)
+
+#define USB_DWC3_R_MAX ((0x530 / 4) + 1)
+
+typedef struct USBDWC3 {
+    SysBusDevice parent_obj;
+    MemoryRegion iomem;
+    MemoryRegion fifos;
+    XHCISysbusState sysbus_xhci;
+
+    uint32_t regs[USB_DWC3_R_MAX];
+    RegisterInfo regs_info[USB_DWC3_R_MAX];
+
+    struct {
+        uint8_t     mode;
+        bool        usb2_mode;
+        uint32_t    dwc_usb3_user;
+        uint8_t     caplen;
+        uint16_t    hciver;
+    } cfg;
+
+} USBDWC3;
+
+#endif
-- 
2.7.4

Re: [PATCH v4 6/7] usb: Add DWC3 model

[Gerd Hoffmann]

On Sat, Aug 29, 2020 at 12:49:39AM +0530, Sai Pavan Boddu wrote:
> From: Vikram Garhwal <fnu.vikram@xilinx.com>
> 
> This patch adds skeleton model of dwc3 usb controller attached to
> xhci-sysbus device.

--verbose.

This looks like xhci with a bunch of extra registers?
What these registers are good for?

> +/*
> + * QEMU model of the USB DWC3 host controller emulation.

(answer should go to both this comment and the commit message).

thanks,
  Gerd

RE: [PATCH v4 6/7] usb: Add DWC3 model

[Sai Pavan Boddu]

HI Gred,

> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Monday, August 31, 2020 12:36 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Markus Armbruster
> <armbru@redhat.com>; 'Marc-André Lureau'
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Edgar Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>; qemu-devel@nongnu.org; Alistair Francis
> <alistair.francis@wdc.com>; Eduardo Habkost <ehabkost@redhat.com>;
> Ying Fang <fangying1@huawei.com>; 'Philippe Mathieu-Daudé'
> <philmd@redhat.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 6/7] usb: Add DWC3 model
> 
> On Sat, Aug 29, 2020 at 12:49:39AM +0530, Sai Pavan Boddu wrote:
> > From: Vikram Garhwal <fnu.vikram@xilinx.com>
> >
> > This patch adds skeleton model of dwc3 usb controller attached to
> > xhci-sysbus device.
> 
> --verbose.
> 
> This looks like xhci with a bunch of extra registers?
[Sai Pavan Boddu] 
> What these registers are good for?
These are also put to make the guest happy.
This module contain dwc3 global registers which deal with power management, phy config and ID registers.
And also has Device and OTG registers which are incomplete at present.

What I realized is, we could clean many of these registers and only emulate ID registers at present. As others are meaningless. I would just define a reserved space, to skip io access errors.

Thanks,
Sai Pavan
> 
> > +/*
> > + * QEMU model of the USB DWC3 host controller emulation.
> 
> (answer should go to both this comment and the commit message).
> 
> thanks,
>   Gerd

[PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal

[Sai Pavan Boddu]

From: Vikram Garhwal <fnu.vikram@xilinx.com>

Connect dwc3 controller and usb2-reg module to virt-versal.
Configure it as dual port host controller.

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/arm/xlnx-versal-virt.c    | 59 ++++++++++++++++++++++++++++++++++++++++++++
 hw/arm/xlnx-versal.c         | 38 ++++++++++++++++++++++++++++
 include/hw/arm/xlnx-versal.h | 14 +++++++++++
 3 files changed, 111 insertions(+)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 4b3152e..398693d 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -39,6 +39,8 @@ typedef struct VersalVirt {
         uint32_t ethernet_phy[2];
         uint32_t clk_125Mhz;
         uint32_t clk_25Mhz;
+        uint32_t usb;
+        uint32_t dwc;
     } phandle;
     struct arm_boot_info binfo;
 
@@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s)
     s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
     s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
 
+    s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);
+    s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);
     /* Create /chosen node for load_dtb.  */
     qemu_fdt_add_subnode(s->fdt, "/chosen");
 
@@ -148,6 +152,60 @@ static void fdt_add_timer_nodes(VersalVirt *s)
                      compat, sizeof(compat));
 }
 
+static void fdt_add_usb_xhci_nodes(VersalVirt *s)
+{
+    const char clocknames[] = "bus_clk\0ref_clk";
+    char *usb2name = g_strdup_printf("/usb@ff9d0000");
+    const char dwcCompat[] = "xlnx,versal-dwc3";
+    qemu_fdt_add_subnode(s->fdt, usb2name);
+    qemu_fdt_setprop(s->fdt, usb2name, "compatible",
+                         dwcCompat, sizeof(dwcCompat));
+    qemu_fdt_setprop_sized_cells(s->fdt, usb2name, "reg",
+                                     2, MM_USB2_REGS, 2, 0x100);
+    qemu_fdt_setprop(s->fdt, usb2name, "clock-names",
+                         clocknames, sizeof(clocknames));
+    qemu_fdt_setprop_cells(s->fdt, usb2name, "clocks",
+                               s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);
+    qemu_fdt_setprop(s->fdt, usb2name, "ranges", NULL, 0);
+    qemu_fdt_setprop_cell(s->fdt, usb2name, "#address-cells", 2);
+    qemu_fdt_setprop_cell(s->fdt, usb2name, "#size-cells", 2);
+    qemu_fdt_setprop_cell(s->fdt, usb2name, "phandle", s->phandle.usb);
+    g_free(usb2name);
+
+    {
+        uint64_t addr = MM_USB_XHCI_0;
+        unsigned int irq = VERSAL_USB0_IRQ_0;
+        const char compat[] = "snps,dwc3";
+        const char intName[] = "dwc_usb3";
+        uint32_t frameLen = 0x20;
+
+        char *name = g_strdup_printf("/usb@ff9d0000/dwc3@%" PRIx64, addr);
+        qemu_fdt_add_subnode(s->fdt, name);
+        qemu_fdt_setprop(s->fdt, name, "compatible",
+                         compat, sizeof(compat));
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, addr, 2, MM_USB_XHCI_SIZE_0);
+        qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+                         intName, sizeof(intName));
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                                   GIC_FDT_IRQ_TYPE_SPI, irq,
+                                   GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_cell(s->fdt, name,
+                              "snps,quirk-frame-length-adjustment",
+                               frameLen);
+        qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);
+        qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");
+        qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");
+        qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,usb3_lpm_capable", NULL, 0);
+        qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
+        qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
+        g_free(name);
+    }
+}
 static void fdt_add_uart_nodes(VersalVirt *s)
 {
     uint64_t addrs[] = { MM_UART1, MM_UART0 };
@@ -515,6 +573,7 @@ static void versal_virt_init(MachineState *machine)
     fdt_add_gic_nodes(s);
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
+    fdt_add_usb_xhci_nodes(s);
     fdt_add_sd_nodes(s);
     fdt_add_rtc_node(s);
     fdt_add_cpu_nodes(s, psci_conduit);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index e3aa4bd..5cb03a1 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -145,6 +145,43 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_usbs(Versal *s, qemu_irq *pic)
+{
+    char *name = g_strdup_printf("dwc3-0");
+    DeviceState *dev, *xhci_dev;
+    MemoryRegion *mr;
+
+    object_initialize_child(OBJECT(s), name, &s->fpd.iou.dwc3,
+                            TYPE_USB_DWC3);
+    dev = DEVICE(&s->fpd.iou.dwc3);
+    xhci_dev = DEVICE(&s->fpd.iou.dwc3.sysbus_xhci);
+
+    object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps),
+                             &error_abort);
+    qdev_prop_set_uint32(xhci_dev, "intrs", 4);
+    qdev_prop_set_uint32(xhci_dev, "slots", 2);
+
+    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0 + 0xC100 , mr);
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);
+    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);
+
+    sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]);
+    g_free(name);
+
+    name = g_strdup_printf("usb2reg-0");
+    object_initialize_child(OBJECT(s), name, &s->fpd.iou.Usb2Regs,
+                           "xlnx.usb2_regs");
+    dev = DEVICE(&s->fpd.iou.Usb2Regs);
+    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion(&s->mr_ps, MM_USB2_REGS, mr);
+    g_free(name);
+}
+
 static void versal_create_gems(Versal *s, qemu_irq *pic)
 {
     int i;
@@ -332,6 +369,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_apu_cpus(s);
     versal_create_apu_gic(s, pic);
     versal_create_uarts(s, pic);
+    versal_create_usbs(s, pic);
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
     versal_create_sds(s, pic);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 9c9f47b..e19cfd5 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -20,6 +20,8 @@
 #include "hw/dma/xlnx-zdma.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/rtc/xlnx-zynqmp-rtc.h"
+#include "hw/usb/hcd-dwc3.h"
+#include "hw/misc/xlnx-versal-usb2-regs.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
@@ -42,6 +44,11 @@ typedef struct Versal {
             ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
             GICv3State gic;
         } apu;
+
+        struct {
+            USBDWC3 dwc3;
+            XlnxUsb2Regs Usb2Regs;
+        } iou;
     } fpd;
 
     MemoryRegion mr_ps;
@@ -87,6 +94,7 @@ typedef struct Versal {
 
 #define VERSAL_UART0_IRQ_0         18
 #define VERSAL_UART1_IRQ_0         19
+#define VERSAL_USB0_IRQ_0          22
 #define VERSAL_GEM0_IRQ_0          56
 #define VERSAL_GEM0_WAKE_IRQ_0     57
 #define VERSAL_GEM1_IRQ_0          58
@@ -124,6 +132,12 @@ typedef struct Versal {
 #define MM_OCM                      0xfffc0000U
 #define MM_OCM_SIZE                 0x40000
 
+#define MM_USB2_REGS                0xFF9D0000
+#define MM_USB2_SIZE                0x10000
+
+#define MM_USB_XHCI_0               0xFE200000
+#define MM_USB_XHCI_SIZE_0          0x10000
+
 #define MM_TOP_DDR                  0x0
 #define MM_TOP_DDR_SIZE             0x80000000U
 #define MM_TOP_DDR_2                0x800000000ULL
-- 
2.7.4

Re: [PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal

[Gerd Hoffmann]

  Hi,

> +        unsigned int irq = VERSAL_USB0_IRQ_0;
> +        const char intName[] = "dwc_usb3";
> +        qemu_fdt_setprop(s->fdt, name, "interrupt-names",
> +                         intName, sizeof(intName));
> +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
> +                                   GIC_FDT_IRQ_TYPE_SPI, irq,
> +                                   GIC_FDT_IRQ_FLAGS_LEVEL_HI);

This seems to declare one IRQ in the FDT.

> +    qdev_prop_set_uint32(xhci_dev, "intrs", 4);

Here you configure 4 IRQs for xhci-sysbus.

> +    sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]);

Also a single IRQ only.

I'm wondering which is correct?  Probably one IRQ?  Do we need support
for multiple IRQs in xhci-sysbus in the first place?

take care,
  Gerd

RE: [PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal

[Sai Pavan Boddu]

Hi Gred,

> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Monday, August 31, 2020 12:43 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Markus Armbruster
> <armbru@redhat.com>; 'Marc-André Lureau'
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Edgar Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>; qemu-devel@nongnu.org; Alistair Francis
> <alistair.francis@wdc.com>; Eduardo Habkost <ehabkost@redhat.com>;
> Ying Fang <fangying1@huawei.com>; 'Philippe Mathieu-Daudé'
> <philmd@redhat.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal
> 
>   Hi,
> 
> > +        unsigned int irq = VERSAL_USB0_IRQ_0;
> > +        const char intName[] = "dwc_usb3";
> > +        qemu_fdt_setprop(s->fdt, name, "interrupt-names",
> > +                         intName, sizeof(intName));
> > +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
> > +                                   GIC_FDT_IRQ_TYPE_SPI, irq,
> > +                                   GIC_FDT_IRQ_FLAGS_LEVEL_HI);
> 
> This seems to declare one IRQ in the FDT.
> 
> > +    qdev_prop_set_uint32(xhci_dev, "intrs", 4);
> 
> Here you configure 4 IRQs for xhci-sysbus.
> 
> > +    sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0,
> > + pic[VERSAL_USB0_IRQ_0]);
> 
> Also a single IRQ only.
> 
> I'm wondering which is correct?  Probably one IRQ?  Do we need support for
> multiple IRQs in xhci-sysbus in the first place?
[Sai Pavan Boddu] It should be only one, as others seems to be define for device and OTG modes. I would fix this 

Thanks,
Sai Pavan
> 
> take care,
>   Gerd

Re: [PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal

[Gerd Hoffmann]

  Hi,

> > Also a single IRQ only.
> > 
> > I'm wondering which is correct?  Probably one IRQ?  Do we need support for
> > multiple IRQs in xhci-sysbus in the first place?
> [Sai Pavan Boddu] It should be only one, as others seems to be define for device and OTG modes.

Documenting the registers/irqs used for device & otg in comments would be nice.

thanks,
  Gerd

Re: [PATCH v4 0/7] Make hcd-xhci independent of pci hooks

[Gerd Hoffmann]

On Sat, Aug 29, 2020 at 12:49:33AM +0530, Sai Pavan Boddu wrote:
> This patch series attempts to make 'hcd-xhci' an independent model so
> it can be used by both pci and system-bus interface.

Doesn't apply to git master.
Seems the series needs a rebase and adaption to the meson build system.

take care,
  Gerd

RE: [PATCH v4 0/7] Make hcd-xhci independent of pci hooks

[Sai Pavan Boddu]

Hi Gred,

> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Monday, August 31, 2020 5:28 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Markus Armbruster
> <armbru@redhat.com>; 'Marc-André Lureau'
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Edgar Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> <figlesia@xilinx.com>; qemu-devel@nongnu.org; Alistair Francis
> <alistair.francis@wdc.com>; Eduardo Habkost <ehabkost@redhat.com>;
> Ying Fang <fangying1@huawei.com>; 'Philippe Mathieu-Daudé'
> <philmd@redhat.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v4 0/7] Make hcd-xhci independent of pci hooks
> 
> On Sat, Aug 29, 2020 at 12:49:33AM +0530, Sai Pavan Boddu wrote:
> > This patch series attempts to make 'hcd-xhci' an independent model so
> > it can be used by both pci and system-bus interface.
> 
> Doesn't apply to git master.
> Seems the series needs a rebase and adaption to the meson build system.
[Sai Pavan Boddu] Ok, I missed rebasing patches over master branch. I will update this in V5.

Thanks,
Sai Pavan
> 
> take care,
>   Gerd