From: Alexandre Ghiti <alexandre.ghiti@canonical.com> To: Samuel Holland <samuel@sholland.org> Cc: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>, Atish Patra <Atish.Patra@wdc.com>, Christoph Hellwig <hch@lst.de>, Andrey Ryabinin <ryabinin.a.a@gmail.com>, Alexander Potapenko <glider@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, Dmitry Vyukov <dvyukov@google.com>, Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Kees Cook <keescook@chromium.org>, Guo Ren <guoren@linux.alibaba.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, linux-doc@vger.kernel.org, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v2 04/10] riscv: Implement sv48 support Date: Mon, 4 Oct 2021 09:31:26 +0200 [thread overview] Message-ID: <CA+zEjCv-2ONyXykRLP2dabELimYbbCmREP5v6DfeV5zk5T+zRg@mail.gmail.com> (raw) In-Reply-To: <748a2c58-4d69-6457-0aa5-89797cb45a5c@sholland.org> On Mon, Oct 4, 2021 at 3:34 AM Samuel Holland <samuel@sholland.org> wrote: > > On 9/29/21 9:51 AM, Alexandre Ghiti wrote: > > By adding a new 4th level of page table, give the possibility to 64bit > > kernel to address 2^48 bytes of virtual address: in practice, that offers > > 128TB of virtual address space to userspace and allows up to 64TB of > > physical memory. > > > > If the underlying hardware does not support sv48, we will automatically > > fallback to a standard 3-level page table by folding the new PUD level into > > PGDIR level. In order to detect HW capabilities at runtime, we > > use SATP feature that ignores writes with an unsupported mode. > > > > Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> > > --- > > arch/riscv/Kconfig | 4 +- > > arch/riscv/include/asm/csr.h | 3 +- > > arch/riscv/include/asm/fixmap.h | 1 + > > arch/riscv/include/asm/kasan.h | 2 +- > > arch/riscv/include/asm/page.h | 10 + > > arch/riscv/include/asm/pgalloc.h | 40 ++++ > > arch/riscv/include/asm/pgtable-64.h | 108 ++++++++++- > > arch/riscv/include/asm/pgtable.h | 13 +- > > arch/riscv/kernel/head.S | 3 +- > > arch/riscv/mm/context.c | 4 +- > > arch/riscv/mm/init.c | 237 ++++++++++++++++++++---- > > arch/riscv/mm/kasan_init.c | 91 +++++++-- > > drivers/firmware/efi/libstub/efi-stub.c | 2 + > > 13 files changed, 453 insertions(+), 65 deletions(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 13e9c4298fbc..69c5533955ed 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -149,7 +149,7 @@ config PAGE_OFFSET > > hex > > default 0xC0000000 if 32BIT > > default 0x80000000 if 64BIT && !MMU > > - default 0xffffffe000000000 if 64BIT > > + default 0xffffc00000000000 if 64BIT > > > > config ARCH_FLATMEM_ENABLE > > def_bool !NUMA > > @@ -197,7 +197,7 @@ config FIX_EARLYCON_MEM > > > > config PGTABLE_LEVELS > > int > > - default 3 if 64BIT > > + default 4 if 64BIT > > default 2 > > > > config LOCKDEP_SUPPORT > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > > index 87ac65696871..3fdb971c7896 100644 > > --- a/arch/riscv/include/asm/csr.h > > +++ b/arch/riscv/include/asm/csr.h > > @@ -40,14 +40,13 @@ > > #ifndef CONFIG_64BIT > > #define SATP_PPN _AC(0x003FFFFF, UL) > > #define SATP_MODE_32 _AC(0x80000000, UL) > > -#define SATP_MODE SATP_MODE_32 > > #define SATP_ASID_BITS 9 > > #define SATP_ASID_SHIFT 22 > > #define SATP_ASID_MASK _AC(0x1FF, UL) > > #else > > #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) > > #define SATP_MODE_39 _AC(0x8000000000000000, UL) > > -#define SATP_MODE SATP_MODE_39 > > +#define SATP_MODE_48 _AC(0x9000000000000000, UL) > > #define SATP_ASID_BITS 16 > > #define SATP_ASID_SHIFT 44 > > #define SATP_ASID_MASK _AC(0xFFFF, UL) > > diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h > > index 54cbf07fb4e9..58a718573ad6 100644 > > --- a/arch/riscv/include/asm/fixmap.h > > +++ b/arch/riscv/include/asm/fixmap.h > > @@ -24,6 +24,7 @@ enum fixed_addresses { > > FIX_HOLE, > > FIX_PTE, > > FIX_PMD, > > + FIX_PUD, > > FIX_TEXT_POKE1, > > FIX_TEXT_POKE0, > > FIX_EARLYCON_MEM_BASE, > > diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h > > index a2b3d9cdbc86..1dcf5fa93aa0 100644 > > --- a/arch/riscv/include/asm/kasan.h > > +++ b/arch/riscv/include/asm/kasan.h > > @@ -27,7 +27,7 @@ > > */ > > #define KASAN_SHADOW_SCALE_SHIFT 3 > > > > -#define KASAN_SHADOW_SIZE (UL(1) << ((CONFIG_VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > +#define KASAN_SHADOW_SIZE (UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > Does this change belong in patch 1, where you remove CONFIG_VA_BITS? Indeed, I fixed KASAN in this version and wrongly rebased the changes. Thanks! Alex > > Regards, > Samuel
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Ghiti <alexandre.ghiti@canonical.com> To: Samuel Holland <samuel@sholland.org> Cc: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>, Atish Patra <Atish.Patra@wdc.com>, Christoph Hellwig <hch@lst.de>, Andrey Ryabinin <ryabinin.a.a@gmail.com>, Alexander Potapenko <glider@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, Dmitry Vyukov <dvyukov@google.com>, Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Kees Cook <keescook@chromium.org>, Guo Ren <guoren@linux.alibaba.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, linux-doc@vger.kernel.org, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v2 04/10] riscv: Implement sv48 support Date: Mon, 4 Oct 2021 09:31:26 +0200 [thread overview] Message-ID: <CA+zEjCv-2ONyXykRLP2dabELimYbbCmREP5v6DfeV5zk5T+zRg@mail.gmail.com> (raw) In-Reply-To: <748a2c58-4d69-6457-0aa5-89797cb45a5c@sholland.org> On Mon, Oct 4, 2021 at 3:34 AM Samuel Holland <samuel@sholland.org> wrote: > > On 9/29/21 9:51 AM, Alexandre Ghiti wrote: > > By adding a new 4th level of page table, give the possibility to 64bit > > kernel to address 2^48 bytes of virtual address: in practice, that offers > > 128TB of virtual address space to userspace and allows up to 64TB of > > physical memory. > > > > If the underlying hardware does not support sv48, we will automatically > > fallback to a standard 3-level page table by folding the new PUD level into > > PGDIR level. In order to detect HW capabilities at runtime, we > > use SATP feature that ignores writes with an unsupported mode. > > > > Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> > > --- > > arch/riscv/Kconfig | 4 +- > > arch/riscv/include/asm/csr.h | 3 +- > > arch/riscv/include/asm/fixmap.h | 1 + > > arch/riscv/include/asm/kasan.h | 2 +- > > arch/riscv/include/asm/page.h | 10 + > > arch/riscv/include/asm/pgalloc.h | 40 ++++ > > arch/riscv/include/asm/pgtable-64.h | 108 ++++++++++- > > arch/riscv/include/asm/pgtable.h | 13 +- > > arch/riscv/kernel/head.S | 3 +- > > arch/riscv/mm/context.c | 4 +- > > arch/riscv/mm/init.c | 237 ++++++++++++++++++++---- > > arch/riscv/mm/kasan_init.c | 91 +++++++-- > > drivers/firmware/efi/libstub/efi-stub.c | 2 + > > 13 files changed, 453 insertions(+), 65 deletions(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 13e9c4298fbc..69c5533955ed 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -149,7 +149,7 @@ config PAGE_OFFSET > > hex > > default 0xC0000000 if 32BIT > > default 0x80000000 if 64BIT && !MMU > > - default 0xffffffe000000000 if 64BIT > > + default 0xffffc00000000000 if 64BIT > > > > config ARCH_FLATMEM_ENABLE > > def_bool !NUMA > > @@ -197,7 +197,7 @@ config FIX_EARLYCON_MEM > > > > config PGTABLE_LEVELS > > int > > - default 3 if 64BIT > > + default 4 if 64BIT > > default 2 > > > > config LOCKDEP_SUPPORT > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > > index 87ac65696871..3fdb971c7896 100644 > > --- a/arch/riscv/include/asm/csr.h > > +++ b/arch/riscv/include/asm/csr.h > > @@ -40,14 +40,13 @@ > > #ifndef CONFIG_64BIT > > #define SATP_PPN _AC(0x003FFFFF, UL) > > #define SATP_MODE_32 _AC(0x80000000, UL) > > -#define SATP_MODE SATP_MODE_32 > > #define SATP_ASID_BITS 9 > > #define SATP_ASID_SHIFT 22 > > #define SATP_ASID_MASK _AC(0x1FF, UL) > > #else > > #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) > > #define SATP_MODE_39 _AC(0x8000000000000000, UL) > > -#define SATP_MODE SATP_MODE_39 > > +#define SATP_MODE_48 _AC(0x9000000000000000, UL) > > #define SATP_ASID_BITS 16 > > #define SATP_ASID_SHIFT 44 > > #define SATP_ASID_MASK _AC(0xFFFF, UL) > > diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h > > index 54cbf07fb4e9..58a718573ad6 100644 > > --- a/arch/riscv/include/asm/fixmap.h > > +++ b/arch/riscv/include/asm/fixmap.h > > @@ -24,6 +24,7 @@ enum fixed_addresses { > > FIX_HOLE, > > FIX_PTE, > > FIX_PMD, > > + FIX_PUD, > > FIX_TEXT_POKE1, > > FIX_TEXT_POKE0, > > FIX_EARLYCON_MEM_BASE, > > diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h > > index a2b3d9cdbc86..1dcf5fa93aa0 100644 > > --- a/arch/riscv/include/asm/kasan.h > > +++ b/arch/riscv/include/asm/kasan.h > > @@ -27,7 +27,7 @@ > > */ > > #define KASAN_SHADOW_SCALE_SHIFT 3 > > > > -#define KASAN_SHADOW_SIZE (UL(1) << ((CONFIG_VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > +#define KASAN_SHADOW_SIZE (UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > Does this change belong in patch 1, where you remove CONFIG_VA_BITS? Indeed, I fixed KASAN in this version and wrongly rebased the changes. Thanks! Alex > > Regards, > Samuel _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-10-04 7:31 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-29 14:51 [PATCH v2 00/10] Introduce sv48 support without relocatable kernel Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 01/10] riscv: Allow to dynamically define VA_BITS Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 02/10] riscv: Get rid of MAXPHYSMEM configs Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 03/10] asm-generic: Prepare for riscv use of pud_alloc_one and pud_free Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 04/10] riscv: Implement sv48 support Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-10-04 1:34 ` Samuel Holland 2021-10-04 1:34 ` Samuel Holland 2021-10-04 7:31 ` Alexandre Ghiti [this message] 2021-10-04 7:31 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 05/10] riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 06/10] riscv: Explicit comment about user virtual address space size Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 07/10] riscv: Improve virtual kernel memory layout dump Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 08/10] Documentation: riscv: Add sv48 description to VM layout Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 09/10] riscv: Initialize thread pointer before calling C functions Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-09-29 14:51 ` [PATCH v2 10/10] riscv: Allow user to downgrade to sv39 when hw supports sv48 Alexandre Ghiti 2021-09-29 14:51 ` Alexandre Ghiti 2021-11-24 23:29 ` [PATCH v2 00/10] Introduce sv48 support without relocatable kernel Heiko Stübner 2021-11-24 23:29 ` Heiko Stübner 2021-12-06 10:49 ` Alexandre ghiti 2021-12-06 10:49 ` Alexandre ghiti 2021-12-06 11:17 ` Heiko Stübner 2021-12-06 11:17 ` Heiko Stübner
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