From: Wendy Liang <sunnyliangjy@gmail.com> To: Sudeep Holla <sudeep.holla@arm.com> Cc: Wendy Liang <wendy.liang@xilinx.com>, Jassi Brar <jassisinghbrar@gmail.com>, Michal Simek <michal.simek@xilinx.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Devicetree List <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox Date: Wed, 10 Oct 2018 15:53:47 -0700 [thread overview] Message-ID: <CAA07jV_FWxMRq=4hmTdCXJG6e3=-8AejfpKxmh9KUi9KQDH7yQ@mail.gmail.com> (raw) In-Reply-To: <20181010095741.GA14472@e107155-lin> On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla <sudeep.holla@arm.com> wrote: > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > > in ZynqMP SoC used for the communication between various processor > > systems. > > > > Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> > > [...] > > > +Optional properties: > > +-------------------- > > +- method: The method of accessing the IPI agent registers. > > + Permitted values are: "smc" and "hvc". Default is > > + "smc". > > You are mixing the hardware messaging based mailbox and the software > "smc/hvc" based mailbox together here. Please keep them separated. > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > one direction and hardware based is used for "rx" or the other direction > for communication. > Hi Sudeep, Thanks for your comments. The IPI hardware block has both buffers and registers. The hardware block has dedicated buffers for each mailboxes, and thus, in the implementation, we directly access the buffers from IPI driver. However, the controller registers are shared between mailboxes in the hardware, as the ATF will also access the registers, we need to use SMC/HVC to access the registers (control or ISR). And the SMC/HVC here is for the register access. I am not clear on smc/hvc based mailbox is used for tx, and hardware based is used for "rx". As for both TX and RX, we need to write/read the registers (through SMC) and write/read the buffers provided by the IPI hardware block directly. Thanks, Wendy > You *should not* mix them as single unit. Also lots of other vendor need > SMC/HVC based mailbox. So make it generic and keep it separate. > > -- > Regards, > Sudeep
WARNING: multiple messages have this Message-ID (diff)
From: sunnyliangjy@gmail.com (Wendy Liang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox Date: Wed, 10 Oct 2018 15:53:47 -0700 [thread overview] Message-ID: <CAA07jV_FWxMRq=4hmTdCXJG6e3=-8AejfpKxmh9KUi9KQDH7yQ@mail.gmail.com> (raw) In-Reply-To: <20181010095741.GA14472@e107155-lin> On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla <sudeep.holla@arm.com> wrote: > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > > in ZynqMP SoC used for the communication between various processor > > systems. > > > > Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> > > [...] > > > +Optional properties: > > +-------------------- > > +- method: The method of accessing the IPI agent registers. > > + Permitted values are: "smc" and "hvc". Default is > > + "smc". > > You are mixing the hardware messaging based mailbox and the software > "smc/hvc" based mailbox together here. Please keep them separated. > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > one direction and hardware based is used for "rx" or the other direction > for communication. > Hi Sudeep, Thanks for your comments. The IPI hardware block has both buffers and registers. The hardware block has dedicated buffers for each mailboxes, and thus, in the implementation, we directly access the buffers from IPI driver. However, the controller registers are shared between mailboxes in the hardware, as the ATF will also access the registers, we need to use SMC/HVC to access the registers (control or ISR). And the SMC/HVC here is for the register access. I am not clear on smc/hvc based mailbox is used for tx, and hardware based is used for "rx". As for both TX and RX, we need to write/read the registers (through SMC) and write/read the buffers provided by the IPI hardware block directly. Thanks, Wendy > You *should not* mix them as single unit. Also lots of other vendor need > SMC/HVC based mailbox. So make it generic and keep it separate. > > -- > Regards, > Sudeep
next prev parent reply other threads:[~2018-10-10 22:54 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-10 7:18 [PATCH v4 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver Wendy Liang 2018-10-10 7:18 ` Wendy Liang 2018-10-10 7:18 ` Wendy Liang 2018-10-10 7:18 ` [PATCH v4 1/2] mailbox: ZynqMP IPI mailbox controller Wendy Liang 2018-10-10 7:18 ` Wendy Liang 2018-10-10 7:18 ` Wendy Liang 2018-10-10 7:18 ` [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox Wendy Liang 2018-10-10 7:18 ` Wendy Liang 2018-10-10 7:18 ` Wendy Liang 2018-10-10 9:57 ` Sudeep Holla 2018-10-10 9:57 ` Sudeep Holla 2018-10-10 22:53 ` Wendy Liang [this message] 2018-10-10 22:53 ` Wendy Liang 2018-10-29 18:01 ` Jiaying Liang 2018-10-29 18:01 ` Jiaying Liang
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