From: Alex Deucher <alexdeucher@gmail.com> To: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>, "Wentland, Harry" <harry.wentland@amd.com>, Daniel Vetter <daniel@ffwll.ch>, Marek Olsak <maraeo@gmail.com>, "Kazlauskas, Nicholas" <nicholas.kazlauskas@amd.com>, "Leo (Sunpeng) Li" <sunpeng.li@amd.com>, "for 3.8" <stable@vger.kernel.org> Subject: Re: [PATCH v3 03/11] drm/amd/display: Honor the offset for plane 0. Date: Thu, 22 Oct 2020 11:36:12 -0400 [thread overview] Message-ID: <CADnq5_OuXhN-2Raie9V452KrG4ChaguY1q6+Gk19mR86A=Fkog@mail.gmail.com> (raw) In-Reply-To: <20201021233130.874615-4-bas@basnieuwenhuizen.nl> On Wed, Oct 21, 2020 at 7:31 PM Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> wrote: > > With modifiers I'd like to support non-dedicated buffers for > images. > > Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> > Cc: stable@vger.kernel.org # 5.1.0 I think you need # 5.1.x- for it to be applied to all stable kernels since 5.1 otherwise it will just apply to 5.1.x Alex > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 73987fdb6a09..833887b9b0ad 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -3894,6 +3894,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, > struct dc *dc = adev->dm.dc; > struct dc_dcc_surface_param input; > struct dc_surface_dcc_cap output; > + uint64_t plane_address = afb->address + afb->base.offsets[0]; > uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); > uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; > uint64_t dcc_address; > @@ -3937,7 +3938,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, > AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; > dcc->independent_64b_blks = i64b; > > - dcc_address = get_dcc_address(afb->address, info); > + dcc_address = get_dcc_address(plane_address, info); > address->grph.meta_addr.low_part = lower_32_bits(dcc_address); > address->grph.meta_addr.high_part = upper_32_bits(dcc_address); > > @@ -3968,6 +3969,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, > address->tmz_surface = tmz_surface; > > if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { > + uint64_t addr = afb->address + fb->offsets[0]; > + > plane_size->surface_size.x = 0; > plane_size->surface_size.y = 0; > plane_size->surface_size.width = fb->width; > @@ -3976,9 +3979,10 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, > fb->pitches[0] / fb->format->cpp[0]; > > address->type = PLN_ADDR_TYPE_GRAPHICS; > - address->grph.addr.low_part = lower_32_bits(afb->address); > - address->grph.addr.high_part = upper_32_bits(afb->address); > + address->grph.addr.low_part = lower_32_bits(addr); > + address->grph.addr.high_part = upper_32_bits(addr); > } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { > + uint64_t luma_addr = afb->address + fb->offsets[0]; > uint64_t chroma_addr = afb->address + fb->offsets[1]; > > plane_size->surface_size.x = 0; > @@ -3999,9 +4003,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, > > address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; > address->video_progressive.luma_addr.low_part = > - lower_32_bits(afb->address); > + lower_32_bits(luma_addr); > address->video_progressive.luma_addr.high_part = > - upper_32_bits(afb->address); > + upper_32_bits(luma_addr); > address->video_progressive.chroma_addr.low_part = > lower_32_bits(chroma_addr); > address->video_progressive.chroma_addr.high_part = > -- > 2.28.0 >
WARNING: multiple messages have this Message-ID (diff)
From: Alex Deucher <alexdeucher@gmail.com> To: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Marek Olsak <maraeo@gmail.com>, "Leo \(Sunpeng\) Li" <sunpeng.li@amd.com>, amd-gfx list <amd-gfx@lists.freedesktop.org>, "for 3.8" <stable@vger.kernel.org>, Daniel Vetter <daniel@ffwll.ch>, "Wentland, Harry" <harry.wentland@amd.com>, "Kazlauskas, Nicholas" <nicholas.kazlauskas@amd.com> Subject: Re: [PATCH v3 03/11] drm/amd/display: Honor the offset for plane 0. Date: Thu, 22 Oct 2020 11:36:12 -0400 [thread overview] Message-ID: <CADnq5_OuXhN-2Raie9V452KrG4ChaguY1q6+Gk19mR86A=Fkog@mail.gmail.com> (raw) In-Reply-To: <20201021233130.874615-4-bas@basnieuwenhuizen.nl> On Wed, Oct 21, 2020 at 7:31 PM Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> wrote: > > With modifiers I'd like to support non-dedicated buffers for > images. > > Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> > Cc: stable@vger.kernel.org # 5.1.0 I think you need # 5.1.x- for it to be applied to all stable kernels since 5.1 otherwise it will just apply to 5.1.x Alex > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 73987fdb6a09..833887b9b0ad 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -3894,6 +3894,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, > struct dc *dc = adev->dm.dc; > struct dc_dcc_surface_param input; > struct dc_surface_dcc_cap output; > + uint64_t plane_address = afb->address + afb->base.offsets[0]; > uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); > uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; > uint64_t dcc_address; > @@ -3937,7 +3938,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, > AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; > dcc->independent_64b_blks = i64b; > > - dcc_address = get_dcc_address(afb->address, info); > + dcc_address = get_dcc_address(plane_address, info); > address->grph.meta_addr.low_part = lower_32_bits(dcc_address); > address->grph.meta_addr.high_part = upper_32_bits(dcc_address); > > @@ -3968,6 +3969,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, > address->tmz_surface = tmz_surface; > > if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { > + uint64_t addr = afb->address + fb->offsets[0]; > + > plane_size->surface_size.x = 0; > plane_size->surface_size.y = 0; > plane_size->surface_size.width = fb->width; > @@ -3976,9 +3979,10 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, > fb->pitches[0] / fb->format->cpp[0]; > > address->type = PLN_ADDR_TYPE_GRAPHICS; > - address->grph.addr.low_part = lower_32_bits(afb->address); > - address->grph.addr.high_part = upper_32_bits(afb->address); > + address->grph.addr.low_part = lower_32_bits(addr); > + address->grph.addr.high_part = upper_32_bits(addr); > } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { > + uint64_t luma_addr = afb->address + fb->offsets[0]; > uint64_t chroma_addr = afb->address + fb->offsets[1]; > > plane_size->surface_size.x = 0; > @@ -3999,9 +4003,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, > > address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; > address->video_progressive.luma_addr.low_part = > - lower_32_bits(afb->address); > + lower_32_bits(luma_addr); > address->video_progressive.luma_addr.high_part = > - upper_32_bits(afb->address); > + upper_32_bits(luma_addr); > address->video_progressive.chroma_addr.low_part = > lower_32_bits(chroma_addr); > address->video_progressive.chroma_addr.high_part = > -- > 2.28.0 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2020-10-22 15:36 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-21 23:31 [PATCH v3 00/11] amd/display: Add GFX9+ modifier support Bas Nieuwenhuizen 2020-10-21 23:31 ` [PATCH v3 01/11] drm/amd/display: Do not silently accept DCC for multiplane formats Bas Nieuwenhuizen 2020-10-26 13:50 ` Kazlauskas, Nicholas 2020-10-21 23:31 ` [PATCH v3 02/11] drm/amd: Init modifier field of helper fb Bas Nieuwenhuizen 2020-10-26 13:50 ` Kazlauskas, Nicholas 2020-10-21 23:31 ` [PATCH v3 03/11] drm/amd/display: Honor the offset for plane 0 Bas Nieuwenhuizen 2020-10-21 23:31 ` Bas Nieuwenhuizen 2020-10-22 15:36 ` Alex Deucher [this message] 2020-10-22 15:36 ` Alex Deucher 2020-10-22 16:10 ` Greg KH 2020-10-22 16:10 ` Greg KH 2020-10-26 13:51 ` Kazlauskas, Nicholas 2020-10-26 13:51 ` Kazlauskas, Nicholas 2020-10-21 23:31 ` [PATCH v3 04/11] drm/fourcc: Add AMD DRM modifiers Bas Nieuwenhuizen 2020-10-22 15:41 ` Alex Deucher 2020-10-22 16:39 ` Bas Nieuwenhuizen 2020-10-21 23:31 ` [PATCH v3 05/11] drm/amd/display: Store tiling_flags in the framebuffer Bas Nieuwenhuizen 2020-10-26 13:54 ` Kazlauskas, Nicholas 2020-10-21 23:31 ` [PATCH v3 06/11] drm/amd/display: Convert tiling_flags to modifiers Bas Nieuwenhuizen 2020-10-21 23:31 ` [PATCH v3 07/11] drm/amd/display: Refactor surface tiling setup Bas Nieuwenhuizen 2020-10-26 13:58 ` Kazlauskas, Nicholas 2020-10-21 23:31 ` [PATCH v3 08/11] drm/amd/display: Set DC options from modifiers Bas Nieuwenhuizen 2020-10-21 23:31 ` [PATCH v3 09/11] drm/amd/display: Add formats for DCC with 2/3 planes Bas Nieuwenhuizen 2020-10-21 23:31 ` [PATCH v3 10/11] drm/amd/display: Expose modifiers Bas Nieuwenhuizen 2020-10-22 5:50 ` Alex Deucher 2020-10-22 11:44 ` Bas Nieuwenhuizen 2020-10-21 23:31 ` [PATCH v3 11/11] drm/amd/display: Clean up GFX9 tiling_flags path Bas Nieuwenhuizen 2020-10-22 16:55 ` [PATCH v3 00/11] amd/display: Add GFX9+ modifier support Alex Deucher 2020-10-26 8:28 ` Pierre-Eric Pelloux-Prayer
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