From: Stephen Boyd <swboyd@chromium.org> To: Akhil P Oommen <quic_akhilpo@quicinc.com>, Doug Anderson <dianders@chromium.org>, Taniya Das <quic_tdas@quicinc.com>, quic_rjendra@quicinc.com Cc: devicetree@vger.kernel.org, Jonathan Marek <jonathan@marek.ca>, linux-arm-msm <linux-arm-msm@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>, dri-devel <dri-devel@lists.freedesktop.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Herring <robh+dt@kernel.org>, Andy Gross <agross@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Jordan Crouse <jordan@cosmicpenguin.net>, freedreno <freedreno@lists.freedesktop.org>, Matthias Kaehlcke <mka@chromium.org> Subject: Re: [Freedreno] [PATCH v2 5/7] arm64: dts: qcom: sc7280: Update gpu register list Date: Tue, 19 Jul 2022 03:19:48 -0400 [thread overview] Message-ID: <CAE-0n53J=dADDTrydVuNZzw38dW_-+Baf8cfn0Q6DSVX_6cLNg@mail.gmail.com> (raw) In-Reply-To: <0c050434-27ca-1099-d93d-8ad6ace3396e@quicinc.com> Quoting Akhil P Oommen (2022-07-18 23:37:16) > On 7/19/2022 11:19 AM, Stephen Boyd wrote: > > Quoting Akhil P Oommen (2022-07-18 21:07:05) > >> On 7/14/2022 11:10 AM, Akhil P Oommen wrote: > >>> IIUC, qcom gdsc driver doesn't ensure hardware is collapsed since they > >>> are vote-able switches. Ideally, we should ensure that the hw has > >>> collapsed for gpu recovery because there could be transient votes from > >>> other subsystems like hypervisor using their vote register. > >>> > >>> I am not sure how complex the plumbing to gpucc driver would be to allow > >>> gpu driver to check hw status. OTOH, with this patch, gpu driver does a > >>> read operation on a gpucc register which is in always-on domain. That > >>> means we don't need to vote any resource to access this register. Reading between the lines here, you're saying that you have to read the gdsc register to make sure that the gdsc is in some state? Can you clarify exactly what you're doing? And how do you know that something else in the kernel can't cause the register to change after it is read? It certainly seems like we can't be certain because there is voting involved. > >>> > >>> Stephen/Rajendra/Taniya, any suggestion? > > Why can't you assert a gpu reset signal with the reset APIs? This series > > seems to jump through a bunch of hoops to get the gdsc and power domain > > to "reset" when I don't know why any of that is necessary. Can't we > > simply assert a reset to the hardware after recovery completes so the > > device is back into a good known POR (power on reset) state? > That is because there is no register interface to reset GPU CX domain. > The recommended sequence from HW design folks is to collapse both cx and > gx gdsc to properly reset gpu/gmu. > Ok. One knee jerk reaction is to treat the gdsc as a reset then and possibly mux that request along with any power domain on/off so that if the reset is requested and the power domain is off nothing happens. Otherwise if the power domain is on then it manually sequences and controls the two gdscs so that the GPU is reset and then restores the enable state of the power domain.
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <swboyd@chromium.org> To: Akhil P Oommen <quic_akhilpo@quicinc.com>, Doug Anderson <dianders@chromium.org>, Taniya Das <quic_tdas@quicinc.com>, quic_rjendra@quicinc.com Cc: devicetree@vger.kernel.org, Jonathan Marek <jonathan@marek.ca>, linux-arm-msm <linux-arm-msm@vger.kernel.org>, Andy Gross <agross@kernel.org>, dri-devel <dri-devel@lists.freedesktop.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Herring <robh+dt@kernel.org>, Rob Clark <robdclark@gmail.com>, Matthias Kaehlcke <mka@chromium.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Jordan Crouse <jordan@cosmicpenguin.net>, freedreno <freedreno@lists.freedesktop.org>, LKML <linux-kernel@vger.kernel.org> Subject: Re: [Freedreno] [PATCH v2 5/7] arm64: dts: qcom: sc7280: Update gpu register list Date: Tue, 19 Jul 2022 03:19:48 -0400 [thread overview] Message-ID: <CAE-0n53J=dADDTrydVuNZzw38dW_-+Baf8cfn0Q6DSVX_6cLNg@mail.gmail.com> (raw) In-Reply-To: <0c050434-27ca-1099-d93d-8ad6ace3396e@quicinc.com> Quoting Akhil P Oommen (2022-07-18 23:37:16) > On 7/19/2022 11:19 AM, Stephen Boyd wrote: > > Quoting Akhil P Oommen (2022-07-18 21:07:05) > >> On 7/14/2022 11:10 AM, Akhil P Oommen wrote: > >>> IIUC, qcom gdsc driver doesn't ensure hardware is collapsed since they > >>> are vote-able switches. Ideally, we should ensure that the hw has > >>> collapsed for gpu recovery because there could be transient votes from > >>> other subsystems like hypervisor using their vote register. > >>> > >>> I am not sure how complex the plumbing to gpucc driver would be to allow > >>> gpu driver to check hw status. OTOH, with this patch, gpu driver does a > >>> read operation on a gpucc register which is in always-on domain. That > >>> means we don't need to vote any resource to access this register. Reading between the lines here, you're saying that you have to read the gdsc register to make sure that the gdsc is in some state? Can you clarify exactly what you're doing? And how do you know that something else in the kernel can't cause the register to change after it is read? It certainly seems like we can't be certain because there is voting involved. > >>> > >>> Stephen/Rajendra/Taniya, any suggestion? > > Why can't you assert a gpu reset signal with the reset APIs? This series > > seems to jump through a bunch of hoops to get the gdsc and power domain > > to "reset" when I don't know why any of that is necessary. Can't we > > simply assert a reset to the hardware after recovery completes so the > > device is back into a good known POR (power on reset) state? > That is because there is no register interface to reset GPU CX domain. > The recommended sequence from HW design folks is to collapse both cx and > gx gdsc to properly reset gpu/gmu. > Ok. One knee jerk reaction is to treat the gdsc as a reset then and possibly mux that request along with any power domain on/off so that if the reset is requested and the power domain is off nothing happens. Otherwise if the power domain is on then it manually sequences and controls the two gdscs so that the GPU is reset and then restores the enable state of the power domain.
next prev parent reply other threads:[~2022-07-19 7:19 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-09 5:59 [PATCH v2 0/7] Improve GPU Recovery Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-09 5:59 ` [PATCH v2 1/7] drm/msm: Remove unnecessary pm_runtime_get/put Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-09 5:59 ` [PATCH v2 2/7] drm/msm: Correct pm_runtime votes in recover worker Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-09 5:59 ` [PATCH v2 3/7] drm/msm: Fix cx collapse issue during recovery Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-11 23:22 ` Doug Anderson 2022-07-11 23:22 ` Doug Anderson 2022-07-12 5:04 ` [Freedreno] " Akhil P Oommen 2022-07-12 5:04 ` Akhil P Oommen 2022-07-12 16:44 ` Rob Clark 2022-07-12 16:44 ` Rob Clark 2022-07-12 19:15 ` Akhil P Oommen 2022-07-12 19:15 ` Akhil P Oommen 2022-07-20 18:06 ` Rob Clark 2022-07-20 18:06 ` Rob Clark 2022-07-20 20:38 ` Akhil P Oommen 2022-07-20 20:38 ` Akhil P Oommen 2022-07-22 17:25 ` Akhil P Oommen 2022-07-22 17:25 ` Akhil P Oommen 2022-07-09 5:59 ` [PATCH v2 4/7] drm/msm: Ensure cx gdsc collapse " Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-09 5:59 ` [PATCH v2 5/7] arm64: dts: qcom: sc7280: Update gpu register list Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-11 23:27 ` Doug Anderson 2022-07-11 23:27 ` Doug Anderson 2022-07-14 5:40 ` Akhil P Oommen 2022-07-14 5:40 ` Akhil P Oommen 2022-07-19 4:07 ` [Freedreno] " Akhil P Oommen 2022-07-19 4:07 ` Akhil P Oommen 2022-07-19 5:49 ` Stephen Boyd 2022-07-19 5:49 ` Stephen Boyd 2022-07-19 6:37 ` Akhil P Oommen 2022-07-19 6:37 ` Akhil P Oommen 2022-07-19 7:19 ` Stephen Boyd [this message] 2022-07-19 7:19 ` Stephen Boyd 2022-07-19 9:56 ` Rajendra Nayak 2022-07-19 9:56 ` Rajendra Nayak 2022-07-20 6:04 ` Akhil P Oommen 2022-07-20 6:04 ` Akhil P Oommen 2022-07-21 16:04 ` Akhil P Oommen 2022-07-21 16:04 ` Akhil P Oommen 2022-07-22 15:28 ` Rob Clark 2022-07-22 15:28 ` Rob Clark 2022-07-09 5:59 ` [PATCH v2 6/7] drm/msm/a6xx: Improve gpu recovery sequence Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen 2022-07-09 5:59 ` [PATCH v2 7/7] drm/msm/a6xx: Handle GMU prepare-slumber hfi failure Akhil P Oommen 2022-07-09 5:59 ` Akhil P Oommen
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