From: Bin Meng <bmeng.cn@gmail.com> To: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, "Bin Meng" <bin.meng@windriver.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "Alistair Francis" <alistair23@gmail.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, "Paolo Bonzini" <pbonzini@redhat.com> Subject: Re: [PATCH] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Date: Thu, 23 Sep 2021 13:16:26 +0800 [thread overview] Message-ID: <CAEUhbmX_PPdLPgGTtfJZg-Nd0pPxVC93ZYoeVpngnOvdLB0Tww@mail.gmail.com> (raw) In-Reply-To: <20210918180738.2506799-1-f4bug@amsat.org> Hi Philippe, On Sun, Sep 19, 2021 at 2:07 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it > - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART > - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() > - Keep mchp_pfsoc_mmuart_create() behavior Thanks for taking care of the updates! > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > include/hw/char/mchp_pfsoc_mmuart.h | 16 ++++-- > hw/char/mchp_pfsoc_mmuart.c | 77 +++++++++++++++++++++++------ > 2 files changed, 73 insertions(+), 20 deletions(-) > > diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h > index f61990215f0..b484b7ea5e4 100644 > --- a/include/hw/char/mchp_pfsoc_mmuart.h > +++ b/include/hw/char/mchp_pfsoc_mmuart.h > @@ -28,16 +28,22 @@ > #ifndef HW_MCHP_PFSOC_MMUART_H > #define HW_MCHP_PFSOC_MMUART_H > > +#include "hw/sysbus.h" > #include "hw/char/serial.h" > > #define MCHP_PFSOC_MMUART_REG_SIZE 52 > > -typedef struct MchpPfSoCMMUartState { > - MemoryRegion iomem; > - hwaddr base; > - qemu_irq irq; > +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart" > +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART) > > - SerialMM *serial; > +typedef struct MchpPfSoCMMUartState { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + MemoryRegion iomem; > + > + SerialMM serial_mm; > > uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)]; > } MchpPfSoCMMUartState; > diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c > index 2facf85c2d8..74404e047d4 100644 > --- a/hw/char/mchp_pfsoc_mmuart.c > +++ b/hw/char/mchp_pfsoc_mmuart.c > @@ -22,8 +22,9 @@ > > #include "qemu/osdep.h" > #include "qemu/log.h" > -#include "chardev/char.h" > +#include "qapi/error.h" > #include "hw/char/mchp_pfsoc_mmuart.h" > +#include "hw/qdev-properties.h" > > static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) > { > @@ -63,23 +64,69 @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { > }, > }; > > -MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, > - hwaddr base, qemu_irq irq, Chardev *chr) > +static void mchp_pfsoc_mmuart_init(Object *obj) > { > - MchpPfSoCMMUartState *s; > - > - s = g_new0(MchpPfSoCMMUartState, 1); > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj); > > memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, > "mchp.pfsoc.mmuart", 0x1000); > + sysbus_init_mmio(sbd, &s->iomem); > > - s->base = base; > - s->irq = irq; > - > - s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr, > - DEVICE_LITTLE_ENDIAN); > - > - memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); > - > - return s; > + object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM); > + object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev"); Do we have a common convention for what needs to be done in the instance_init() call and what in the realize() call? For example, I see some devices put memory_region_init_io() and sysbus_init_mmio() in their realize(). > +} > + > +static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp) > +{ > + MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev); > + > + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2); > + qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193); > + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness", > + DEVICE_LITTLE_ENDIAN); It looks like serial_mm_init() does one more thing: qdev_set_legacy_instance_id(DEVICE(smm), base, 2); I am not sure what that is. > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) { > + return; > + } > + sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm)); > + memory_region_add_subregion(&s->iomem, 0x20, > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0)); > +} > + > +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->realize = mchp_pfsoc_mmuart_realize; > +} > + > +static const TypeInfo mchp_pfsoc_mmuart_info = { > + .name = TYPE_MCHP_PFSOC_UART, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(MchpPfSoCMMUartState), > + .instance_init = mchp_pfsoc_mmuart_init, > + .class_init = mchp_pfsoc_mmuart_class_init, > +}; > + > +static void mchp_pfsoc_mmuart_register_types(void) > +{ > + type_register_static(&mchp_pfsoc_mmuart_info); > +} > + > +type_init(mchp_pfsoc_mmuart_register_types) > + > +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, > + hwaddr base, > + qemu_irq irq, Chardev *chr) > +{ > + DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART); > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > + > + qdev_prop_set_chr(dev, "chardev", chr); > + sysbus_realize(sbd, &error_fatal); > + > + memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0)); > + sysbus_connect_irq(sbd, 0, irq); > + > + return MCHP_PFSOC_UART(dev); > } This patch unfortunately breaks the polarfire machine that no serial output is seen. I did not take a further look yet. Regards, Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "Bin Meng" <bin.meng@windriver.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Alistair Francis" <alistair23@gmail.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com> Subject: Re: [PATCH] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Date: Thu, 23 Sep 2021 13:16:26 +0800 [thread overview] Message-ID: <CAEUhbmX_PPdLPgGTtfJZg-Nd0pPxVC93ZYoeVpngnOvdLB0Tww@mail.gmail.com> (raw) In-Reply-To: <20210918180738.2506799-1-f4bug@amsat.org> Hi Philippe, On Sun, Sep 19, 2021 at 2:07 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it > - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART > - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() > - Keep mchp_pfsoc_mmuart_create() behavior Thanks for taking care of the updates! > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > include/hw/char/mchp_pfsoc_mmuart.h | 16 ++++-- > hw/char/mchp_pfsoc_mmuart.c | 77 +++++++++++++++++++++++------ > 2 files changed, 73 insertions(+), 20 deletions(-) > > diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h > index f61990215f0..b484b7ea5e4 100644 > --- a/include/hw/char/mchp_pfsoc_mmuart.h > +++ b/include/hw/char/mchp_pfsoc_mmuart.h > @@ -28,16 +28,22 @@ > #ifndef HW_MCHP_PFSOC_MMUART_H > #define HW_MCHP_PFSOC_MMUART_H > > +#include "hw/sysbus.h" > #include "hw/char/serial.h" > > #define MCHP_PFSOC_MMUART_REG_SIZE 52 > > -typedef struct MchpPfSoCMMUartState { > - MemoryRegion iomem; > - hwaddr base; > - qemu_irq irq; > +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart" > +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART) > > - SerialMM *serial; > +typedef struct MchpPfSoCMMUartState { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + MemoryRegion iomem; > + > + SerialMM serial_mm; > > uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)]; > } MchpPfSoCMMUartState; > diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c > index 2facf85c2d8..74404e047d4 100644 > --- a/hw/char/mchp_pfsoc_mmuart.c > +++ b/hw/char/mchp_pfsoc_mmuart.c > @@ -22,8 +22,9 @@ > > #include "qemu/osdep.h" > #include "qemu/log.h" > -#include "chardev/char.h" > +#include "qapi/error.h" > #include "hw/char/mchp_pfsoc_mmuart.h" > +#include "hw/qdev-properties.h" > > static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) > { > @@ -63,23 +64,69 @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { > }, > }; > > -MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, > - hwaddr base, qemu_irq irq, Chardev *chr) > +static void mchp_pfsoc_mmuart_init(Object *obj) > { > - MchpPfSoCMMUartState *s; > - > - s = g_new0(MchpPfSoCMMUartState, 1); > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj); > > memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, > "mchp.pfsoc.mmuart", 0x1000); > + sysbus_init_mmio(sbd, &s->iomem); > > - s->base = base; > - s->irq = irq; > - > - s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr, > - DEVICE_LITTLE_ENDIAN); > - > - memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); > - > - return s; > + object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM); > + object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev"); Do we have a common convention for what needs to be done in the instance_init() call and what in the realize() call? For example, I see some devices put memory_region_init_io() and sysbus_init_mmio() in their realize(). > +} > + > +static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp) > +{ > + MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev); > + > + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2); > + qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193); > + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness", > + DEVICE_LITTLE_ENDIAN); It looks like serial_mm_init() does one more thing: qdev_set_legacy_instance_id(DEVICE(smm), base, 2); I am not sure what that is. > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) { > + return; > + } > + sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm)); > + memory_region_add_subregion(&s->iomem, 0x20, > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0)); > +} > + > +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->realize = mchp_pfsoc_mmuart_realize; > +} > + > +static const TypeInfo mchp_pfsoc_mmuart_info = { > + .name = TYPE_MCHP_PFSOC_UART, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(MchpPfSoCMMUartState), > + .instance_init = mchp_pfsoc_mmuart_init, > + .class_init = mchp_pfsoc_mmuart_class_init, > +}; > + > +static void mchp_pfsoc_mmuart_register_types(void) > +{ > + type_register_static(&mchp_pfsoc_mmuart_info); > +} > + > +type_init(mchp_pfsoc_mmuart_register_types) > + > +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, > + hwaddr base, > + qemu_irq irq, Chardev *chr) > +{ > + DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART); > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > + > + qdev_prop_set_chr(dev, "chardev", chr); > + sysbus_realize(sbd, &error_fatal); > + > + memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0)); > + sysbus_connect_irq(sbd, 0, irq); > + > + return MCHP_PFSOC_UART(dev); > } This patch unfortunately breaks the polarfire machine that no serial output is seen. I did not take a further look yet. Regards, Bin
next prev parent reply other threads:[~2021-09-23 5:17 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-18 18:07 [PATCH] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Philippe Mathieu-Daudé 2021-09-18 18:07 ` Philippe Mathieu-Daudé 2021-09-19 23:06 ` Alistair Francis 2021-09-19 23:06 ` Alistair Francis 2021-09-23 5:16 ` Bin Meng [this message] 2021-09-23 5:16 ` Bin Meng 2021-09-23 10:29 ` Philippe Mathieu-Daudé 2021-09-23 10:29 ` Philippe Mathieu-Daudé 2021-09-23 10:41 ` Peter Maydell 2021-09-23 10:41 ` Peter Maydell 2021-09-23 10:52 ` Philippe Mathieu-Daudé 2021-09-23 10:52 ` Philippe Mathieu-Daudé 2021-09-23 10:56 ` Philippe Mathieu-Daudé 2021-09-23 10:56 ` Philippe Mathieu-Daudé 2021-09-25 12:30 ` Philippe Mathieu-Daudé 2021-09-25 12:30 ` Philippe Mathieu-Daudé 2021-09-26 7:59 ` Bin Meng 2021-09-26 7:59 ` Bin Meng
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