[U-Boot] [PATCH 00/47] powerpc: Enable PCIe DM drvier for some platforms

[U-Boot] [PATCH 00/47] powerpc: Enable PCIe DM drvier for some platforms

[Hou Zhiqiang]

Enable PCIe DM driver for some PowerPC platforms which has supported
device tree.

Depends on the following 2 series:
http://patchwork.ozlabs.org/project/uboot/list/?series=120960
http://patchwork.ozlabs.org/project/uboot/list/?series=115008

Hou Zhiqiang (47):
  powerpc: T208xRDB: Compile legacy PCIe routines conditionally
  powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T2080RDB: Enable PCIe driver
  powerpc: T4RDB: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add T4240 PCIe support
  t4240: dts: Added PCIe DT nodes
  powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T4240RDB: Enable PCIe driver
  powerpc: T102xRDB: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add T102x PCIe support
  t102x: dts: Added PCIe DT nodes
  powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040
  powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T1024RDB: Enable PCIe driver
  powerpc: T104xRDB: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add T104x PCIe support
  t104x: dts: Added PCIe DT nodes
  powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: T1042D4RDB: Enable PCIe driver
  powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs
  P1020: dts: Added PCIe DT nodes
  powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled
  configs: P1020RDB: Enable PCIe driver
  P2020: dts: Added PCIe DT nodes
  configs: P2020RDB: Enable PCIe driver
  powerpc: p_corenet: Compile legacy PCIe routines conditionally
  dm: pcie_fsl: Add P2041 PCIe support
  P2041: dts: Added PCIe DT nodes
  powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled
  configs: P2041RDB: Enable PCIe driver
  dm: pcie_fsl: Add P3041 PCIe support
  P3041: dts: Added PCIe DT nodes
  powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled
  configs: P3041DS: Enable PCIe driver
  dm: pcie_fsl: Add P4080 PCIe support
  P4080: dts: Added PCIe DT nodes
  configs: P4080DS: Enable PCIe driver
  dm: pcie_fsl: Add P5040 PCIe support
  P5040: dts: Added PCIe DT nodes
  configs: P5040DS: Enable PCIe driver
  powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally
  powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected
  dm: pcie_fsl: Add MPC8548 PCIe support
  MPC8548: dts: Added PCIe DT node
  powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled
  configs: MPC8548CDS: Enable PCIe driver

 arch/powerpc/dts/mpc8548-post.dtsi           |  9 ++++
 arch/powerpc/dts/mpc8548cds.dts              |  6 +++
 arch/powerpc/dts/mpc8548cds_36b.dts          |  6 +++
 arch/powerpc/dts/p1020-post.dtsi             | 20 +++++++
 arch/powerpc/dts/p1020rdb-pc.dts             | 12 +++++
 arch/powerpc/dts/p1020rdb-pc_36b.dts         | 12 +++++
 arch/powerpc/dts/p1020rdb-pd.dts             | 12 +++++
 arch/powerpc/dts/p2020-post.dtsi             | 30 +++++++++++
 arch/powerpc/dts/p2020rdb-pc.dts             | 17 ++++++
 arch/powerpc/dts/p2020rdb-pc_36b.dts         | 17 ++++++
 arch/powerpc/dts/p2041.dtsi                  | 36 +++++++++++++
 arch/powerpc/dts/p3041.dtsi                  | 48 +++++++++++++++++
 arch/powerpc/dts/p4080.dtsi                  | 36 +++++++++++++
 arch/powerpc/dts/p5040.dtsi                  | 36 +++++++++++++
 arch/powerpc/dts/t102x.dtsi                  | 36 +++++++++++++
 arch/powerpc/dts/t104x.dtsi                  | 48 +++++++++++++++++
 arch/powerpc/dts/t4240.dtsi                  | 48 +++++++++++++++++
 board/freescale/common/cds_pci_ft.c          |  4 +-
 board/freescale/common/p_corenet/pci.c       |  2 +
 board/freescale/mpc8548cds/mpc8548cds.c      |  6 ++-
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c  |  4 +-
 board/freescale/t102xrdb/pci.c               |  2 +
 board/freescale/t104xrdb/pci.c               |  2 +
 board/freescale/t208xrdb/pci.c               |  2 +
 board/freescale/t4rdb/pci.c                  |  2 +
 configs/MPC8548CDS_36BIT_defconfig           |  4 ++
 configs/MPC8548CDS_defconfig                 |  4 ++
 configs/MPC8548CDS_legacy_defconfig          |  4 ++
 configs/P1020RDB-PC_36BIT_NAND_defconfig     |  4 ++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |  4 ++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |  4 ++
 configs/P1020RDB-PC_36BIT_defconfig          |  4 ++
 configs/P1020RDB-PC_NAND_defconfig           |  4 ++
 configs/P1020RDB-PC_SDCARD_defconfig         |  4 ++
 configs/P1020RDB-PC_SPIFLASH_defconfig       |  4 ++
 configs/P1020RDB-PC_defconfig                |  4 ++
 configs/P1020RDB-PD_NAND_defconfig           |  4 ++
 configs/P1020RDB-PD_SDCARD_defconfig         |  4 ++
 configs/P1020RDB-PD_SPIFLASH_defconfig       |  4 ++
 configs/P1020RDB-PD_defconfig                |  4 ++
 configs/P2020RDB-PC_36BIT_NAND_defconfig     |  4 ++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |  4 ++
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig |  4 ++
 configs/P2020RDB-PC_36BIT_defconfig          |  4 ++
 configs/P2020RDB-PC_NAND_defconfig           |  4 ++
 configs/P2020RDB-PC_SDCARD_defconfig         |  4 ++
 configs/P2020RDB-PC_SPIFLASH_defconfig       |  4 ++
 configs/P2020RDB-PC_defconfig                |  4 ++
 configs/P2041RDB_NAND_defconfig              |  4 ++
 configs/P2041RDB_SDCARD_defconfig            |  4 ++
 configs/P2041RDB_SPIFLASH_defconfig          |  4 ++
 configs/P2041RDB_defconfig                   |  4 ++
 configs/P3041DS_NAND_defconfig               |  4 ++
 configs/P3041DS_SDCARD_defconfig             |  4 ++
 configs/P3041DS_SPIFLASH_defconfig           |  4 ++
 configs/P3041DS_defconfig                    |  4 ++
 configs/P4080DS_SDCARD_defconfig             |  4 ++
 configs/P4080DS_SPIFLASH_defconfig           |  4 ++
 configs/P4080DS_defconfig                    |  4 ++
 configs/P5040DS_NAND_defconfig               |  4 ++
 configs/P5040DS_SDCARD_defconfig             |  4 ++
 configs/P5040DS_SPIFLASH_defconfig           |  4 ++
 configs/P5040DS_defconfig                    |  4 ++
 configs/T1024RDB_NAND_defconfig              |  4 ++
 configs/T1024RDB_SDCARD_defconfig            |  4 ++
 configs/T1024RDB_SPIFLASH_defconfig          |  4 ++
 configs/T1024RDB_defconfig                   |  4 ++
 configs/T1042D4RDB_NAND_defconfig            |  4 ++
 configs/T1042D4RDB_SDCARD_defconfig          |  4 ++
 configs/T1042D4RDB_SPIFLASH_defconfig        |  4 ++
 configs/T1042D4RDB_defconfig                 |  4 ++
 configs/T2080RDB_NAND_defconfig              |  4 ++
 configs/T2080RDB_SDCARD_defconfig            |  4 ++
 configs/T2080RDB_SPIFLASH_defconfig          |  4 ++
 configs/T2080RDB_defconfig                   |  4 ++
 configs/T4240RDB_SDCARD_defconfig            |  4 ++
 configs/T4240RDB_defconfig                   |  4 ++
 drivers/pci/pcie_fsl.c                       | 21 ++++++++
 include/configs/MPC8548CDS.h                 | 22 +++++---
 include/configs/P2041RDB.h                   | 55 ++++++--------------
 include/configs/T102xRDB.h                   | 78 ++++++----------------------
 include/configs/T104xRDB.h                   | 38 +++++++-------
 include/configs/T208xRDB.h                   | 36 +++++++------
 include/configs/T4240RDB.h                   | 35 +++++++------
 include/configs/corenet_ds.h                 | 63 +++++++---------------
 include/configs/p1_p2_rdb_pc.h               | 36 ++++++++-----
 86 files changed, 822 insertions(+), 223 deletions(-)

-- 
2.9.5

[U-Boot] [PATCH 01/47] powerpc: T208xRDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/t208xrdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t208xrdb/pci.c
+++ b/board/freescale/t208xrdb/pci.c
@@ -11,6 +11,7 @@
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

[U-Boot] [PATCH 02/47] powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/T208xRDB.h | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 1a5a93e..b1ae050 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -439,49 +439,51 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_PCIE4		/* PCIE controller 4 */
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
-- 
2.9.5

[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T2080RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/T2080RDB_NAND_defconfig     | 4 ++++
 configs/T2080RDB_SDCARD_defconfig   | 4 ++++
 configs/T2080RDB_SPIFLASH_defconfig | 4 ++++
 configs/T2080RDB_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 7eb7058..30ec72b 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 9ea6698..22c2e05 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -56,6 +56,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 988897b..e70fa0d 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 3f7e282..b620349 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -45,6 +45,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
-- 
2.9.5

[U-Boot] [PATCH 04/47] powerpc: T4RDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/t4rdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
index 4100370..7d670e1 100644
--- a/board/freescale/t4rdb/pci.c
+++ b/board/freescale/t4rdb/pci.c
@@ -11,6 +11,7 @@
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

[U-Boot] [PATCH 05/47] dm: pcie_fsl: Add T4240 PCIe support

[Hou Zhiqiang]

Add compatible string for T4240 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index e13e5a6..961d8e3 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -616,6 +616,7 @@ static struct fsl_pcie_data t2080_data = {
 
 static const struct udevice_id fsl_pcie_ids[] = {
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
+	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
 	{ }
 };
 
-- 
2.9.5

[U-Boot] [PATCH 06/47] t4240: dts: Added PCIe DT nodes

[Hou Zhiqiang]

T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/t4240.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 4d8fc71..fc34974 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -99,4 +99,52 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe240000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe250000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe260000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe270000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe270000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 07/47] powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/T4240RDB.h | 35 +++++++++++++++++++----------------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index a818f0c..8cdc17c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -63,7 +63,6 @@
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -178,44 +177,48 @@
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
-- 
2.9.5

[U-Boot] [PATCH 08/47] configs: T4240RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T4240RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/T4240RDB_SDCARD_defconfig | 4 ++++
 configs/T4240RDB_defconfig        | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index a70c237..cce4872 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -50,6 +50,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index d4ce176..bdadfa8 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -39,6 +39,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
-- 
2.9.5

[U-Boot] [PATCH 09/47] powerpc: T102xRDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/t102xrdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t102xrdb/pci.c
+++ b/board/freescale/t102xrdb/pci.c
@@ -11,6 +11,7 @@
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

[U-Boot] [PATCH 10/47] dm: pcie_fsl: Add T102x PCIe support

[Hou Zhiqiang]

Add compatible string for T102x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 961d8e3..25df84d 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -615,6 +615,7 @@ static struct fsl_pcie_data t2080_data = {
 };
 
 static const struct udevice_id fsl_pcie_ids[] = {
+	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
 	{ }
-- 
2.9.5

[U-Boot] [PATCH 11/47] t102x: dts: Added PCIe DT nodes

[Hou Zhiqiang]

T102x integrated 3 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/t102x.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index 2393e31..c49fd21 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -49,4 +49,40 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe240000 {
+		compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe250000 {
+		compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe260000 {
+		compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 12/47] powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040

[Hou Zhiqiang]

Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and
the PCIE4 related macros, as there are only 3 PCIe controllers
on T102x SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/T102xRDB.h | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index cce65f5..3715e25 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -500,9 +500,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
-#ifdef CONFIG_ARCH_T1040
-#define CONFIG_PCIE4		/* PCIE controller 4 */
-#endif
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 #define CONFIG_PCI_INDIRECT_BRIDGE
@@ -571,27 +568,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #endif
 
-/* controller 4, Base address 203000, to be removed */
-#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
-#else
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xb0000000
-#endif
-#define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#else
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xf8030000
-#endif
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000      /* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
-- 
2.9.5

[U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/T102xRDB.h | 54 +++++++++++++---------------------------------
 1 file changed, 15 insertions(+), 39 deletions(-)

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 3715e25..4fb1709 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
-#define CONFIG_PCI_INDIRECT_BRIDGE
 
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0x90000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
 #endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
 #endif
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-- 
2.9.5

[U-Boot] [PATCH 14/47] configs: T1024RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T1024RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/T1024RDB_NAND_defconfig     | 4 ++++
 configs/T1024RDB_SDCARD_defconfig   | 4 ++++
 configs/T1024RDB_SPIFLASH_defconfig | 4 ++++
 configs/T1024RDB_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 30acd0e..faea7d2 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 7569e4e..bce2fc3 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 470674b..55f80f8 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 146551d..f8b3227 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

[U-Boot] [PATCH 15/47] powerpc: T104xRDB: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/t104xrdb/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
index 9fd6659..6b666ba 100644
--- a/board/freescale/t104xrdb/pci.c
+++ b/board/freescale/t104xrdb/pci.c
@@ -11,6 +11,7 @@
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

[U-Boot] [PATCH 16/47] dm: pcie_fsl: Add T104x PCIe support

[Hou Zhiqiang]

Add compatible string for T104x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 25df84d..c4b4ace 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -616,6 +616,7 @@ static struct fsl_pcie_data t2080_data = {
 
 static const struct udevice_id fsl_pcie_ids[] = {
 	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
+	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
 	{ }
-- 
2.9.5

[U-Boot] [PATCH 17/47] t104x: dts: Added PCIe DT nodes

[Hou Zhiqiang]

T104x integrated 4 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/t104x.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index ff0da93..5998967 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -59,4 +59,52 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe240000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe250000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe260000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe270000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 18/47] powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/T104xRDB.h | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 470f60a..5d9dd10 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -151,13 +151,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_PCIE4			/* PCIE controller 4 */
 
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -530,51 +528,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #endif
 
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
 #define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #endif
 
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
-- 
2.9.5

[U-Boot] [PATCH 19/47] configs: T1042D4RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in T1042D4RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/T1042D4RDB_NAND_defconfig     | 4 ++++
 configs/T1042D4RDB_SDCARD_defconfig   | 4 ++++
 configs/T1042D4RDB_SPIFLASH_defconfig | 4 ++++
 configs/T1042D4RDB_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 2edd3b3..e51124b 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index f5a8613..fa9b3e3 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 945740a..fdec9a2 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 3be988c..86c0a7f 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

[U-Boot] [PATCH 20/47] powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines for P1020,
P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI
is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4b151e8..5982a91 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -277,7 +277,7 @@ int checkboard(void)
 	return 0;
 }
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -443,7 +443,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
+#if !defined(CONFIG_DM_PCI)
 	FT_FSL_PCI_SETUP;
+#endif
 
 #ifdef CONFIG_QE
 	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
-- 
2.9.5

[U-Boot] [PATCH 21/47] dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs

[Hou Zhiqiang]

Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index c4b4ace..c8b8e3b 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -608,6 +608,12 @@ static const struct dm_pci_ops fsl_pcie_ops = {
 	.write_config	= fsl_pcie_write_config,
 };
 
+static struct fsl_pcie_data p1_p2_data = {
+	.block_offset = 0xa000,
+	.block_offset_mask = 0xffff,
+	.stride = 0x1000,
+};
+
 static struct fsl_pcie_data t2080_data = {
 	.block_offset = 0x240000,
 	.block_offset_mask = 0x3fffff,
@@ -615,6 +621,7 @@ static struct fsl_pcie_data t2080_data = {
 };
 
 static const struct udevice_id fsl_pcie_ids[] = {
+	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
 	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p1020-post.dtsi     | 20 ++++++++++++++++++++
 arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
 arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
 arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
 4 files changed, 56 insertions(+)

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index e1a4f50..1e5e678 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -25,3 +25,23 @@
 		last-interrupt-source = <255>;
 	};
 };
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <1>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index fd68b8b..7ebaa61 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -18,6 +18,18 @@
 	soc: soc at ffe00000 {
 		ranges = <0x0 0x0 0xffe00000 0x100000>;
 	};
+
+	pci1: pcie at ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie at ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index a23d031..c0e5ef4 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -18,6 +18,18 @@
 	soc: soc at fffe00000 {
 		ranges = <0x0 0xf 0xffe00000 0x100000>;
 	};
+
+	pci1: pcie at fffe09000 {
+		reg = <0xf 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie at fffe0a000 {
+		reg = <0xf 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 81f25a3..21174a0 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -18,6 +18,18 @@
 	soc: soc at ffe00000 {
 		ranges = <0x0 0x0 0xffe00000 0x100000>;
 	};
+
+	pci1: pcie at ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie at ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "p1020-post.dtsi"
-- 
2.9.5

[U-Boot] [PATCH 23/47] powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1020, P1021, P1024, P1025 and P2020 RDB boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/p1_p2_rdb_pc.h | 36 +++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index b1367a9..d3fb3da 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -215,8 +215,6 @@
 
 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -580,44 +578,56 @@
  */
 
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif /* CONFIG_PCI */
-- 
2.9.5

[U-Boot] [PATCH 24/47] configs: P1020RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P1020RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/P1020RDB-PC_36BIT_NAND_defconfig     | 4 ++++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 4 ++++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++
 configs/P1020RDB-PC_36BIT_defconfig          | 4 ++++
 configs/P1020RDB-PC_NAND_defconfig           | 4 ++++
 configs/P1020RDB-PC_SDCARD_defconfig         | 4 ++++
 configs/P1020RDB-PC_SPIFLASH_defconfig       | 4 ++++
 configs/P1020RDB-PC_defconfig                | 4 ++++
 configs/P1020RDB-PD_NAND_defconfig           | 4 ++++
 configs/P1020RDB-PD_SDCARD_defconfig         | 4 ++++
 configs/P1020RDB-PD_SPIFLASH_defconfig       | 4 ++++
 configs/P1020RDB-PD_defconfig                | 4 ++++
 12 files changed, 48 insertions(+)

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 8fce49d..557fb49 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -55,6 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 80a4a0a..28ec227 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -52,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index ee565d4..84b88ae 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -53,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 7d7c55f..fea964d 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index b729089..62199b9 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -54,6 +54,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 4622efd..f10e4fa 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -51,6 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 9cd897f..bacae37 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -52,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 595ff5f..0a6f974 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index b45122d..2c41054 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index c559879..7f0c7d4 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -55,6 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 1de88fc..d664a09 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 0963553..db78cf4 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -45,6 +45,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
-- 
2.9.5

[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p2020-post.dtsi     | 30 ++++++++++++++++++++++++++++++
 arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
 arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index f20d1fa..f696f35 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -25,3 +25,33 @@
 		last-interrupt-source = <255>;
 	};
 };
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <0>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <1>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 4800b76..08befd4 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -18,6 +18,23 @@
 	soc: soc at ffe00000 {
 		ranges = <0x0 0x0 0xffe00000 0x100000>;
 	};
+
+	pci2: pcie at ffe08000 {
+		reg = <0x0 0xffe08000 0x0 0x1000>;	/* registers */
+		status = "disabled";
+	};
+
+	pci1: pcie at ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie at ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 8323b90..04b2519 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -18,6 +18,23 @@
 	soc: soc at fffe00000 {
 		ranges = <0x0 0xf 0xffe00000 0x100000>;
 	};
+
+	pci2: pcie at fffe08000 {
+		reg = <0xf 0xffe08000 0x0 0x1000>;	/* registers */
+		status = "disabled";
+	};
+
+	pci1: pcie at fffe09000 {
+		reg = <0xf 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie at fffe0a000 {
+		reg = <0xf 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "p2020-post.dtsi"
-- 
2.9.5

[U-Boot] [PATCH 26/47] configs: P2020RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P2020RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/P2020RDB-PC_36BIT_NAND_defconfig     | 4 ++++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 4 ++++
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++
 configs/P2020RDB-PC_36BIT_defconfig          | 4 ++++
 configs/P2020RDB-PC_NAND_defconfig           | 4 ++++
 configs/P2020RDB-PC_SDCARD_defconfig         | 4 ++++
 configs/P2020RDB-PC_SPIFLASH_defconfig       | 4 ++++
 configs/P2020RDB-PC_defconfig                | 4 ++++
 8 files changed, 32 insertions(+)

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index d8c04e2..a51a34c 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 7c45996..9c97b3d 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 5372d98..fee83e5 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 79f4f3c..bb5c6bd 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -47,6 +47,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 2f91691..610bd96 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index a5cee06..46d430c 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index a2f9d87..f3eb66e 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 4000459..b94c67e 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_SYS_NS16550=y
-- 
2.9.5

[U-Boot] [PATCH 27/47] powerpc: p_corenet: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines for P2041RDB,
P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
 not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/common/p_corenet/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c
index a2df928..a6abe66 100644
--- a/board/freescale/common/p_corenet/pci.c
+++ b/board/freescale/common/p_corenet/pci.c
@@ -11,6 +11,7 @@
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.9.5

[U-Boot] [PATCH 28/47] dm: pcie_fsl: Add P2041 PCIe support

[Hou Zhiqiang]

Add compatible string for P2041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index c8b8e3b..61f08e7 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -614,6 +614,12 @@ static struct fsl_pcie_data p1_p2_data = {
 	.stride = 0x1000,
 };
 
+static struct fsl_pcie_data p2041_data = {
+	.block_offset = 0x200000,
+	.block_offset_mask = 0x3fffff,
+	.stride = 0x1000,
+};
+
 static struct fsl_pcie_data t2080_data = {
 	.block_offset = 0x240000,
 	.block_offset_mask = 0x3fffff,
@@ -622,6 +628,7 @@ static struct fsl_pcie_data t2080_data = {
 
 static const struct udevice_id fsl_pcie_ids[] = {
 	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
+	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

[U-Boot] [PATCH 29/47] P2041: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p2041.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 9aa0422..55f7adc 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -60,4 +60,40 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe200000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe201000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe202000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/P2041RDB.h | 55 +++++++++++++---------------------------------
 1 file changed, 15 insertions(+), 40 deletions(-)

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b433308..ba670d7 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -37,7 +37,6 @@
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 #define CONFIG_SYS_SRIO
@@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
@@ -489,7 +449,22 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
-- 
2.9.5

[U-Boot] [PATCH 31/47] configs: P2041RDB: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P2041RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/P2041RDB_NAND_defconfig     | 4 ++++
 configs/P2041RDB_SDCARD_defconfig   | 4 ++++
 configs/P2041RDB_SPIFLASH_defconfig | 4 ++++
 configs/P2041RDB_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 73baf49..43434aa 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index d75f8b1..8d0efa4 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 925f0cd..eadb35b 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 1923b7a..8208907 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

[U-Boot] [PATCH 32/47] dm: pcie_fsl: Add P3041 PCIe support

[Hou Zhiqiang]

Add compatible string for P3041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 61f08e7..a4e0cd1 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -629,6 +629,7 @@ static struct fsl_pcie_data t2080_data = {
 static const struct udevice_id fsl_pcie_ids[] = {
 	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
 	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
+	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

[U-Boot] [PATCH 33/47] P3041: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p3041.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 7d5c713..197896d 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -60,4 +60,52 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe200000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe201000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe202000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe203000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe203000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/corenet_ds.h | 63 +++++++++++++-------------------------------
 1 file changed, 19 insertions(+), 44 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f974291..07844c1 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -54,7 +54,6 @@
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -362,68 +361,25 @@
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
@@ -505,7 +461,26 @@
 #endif
 
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
-- 
2.9.5

[U-Boot] [PATCH 35/47] configs: P3041DS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P3041DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/P3041DS_NAND_defconfig     | 4 ++++
 configs/P3041DS_SDCARD_defconfig   | 4 ++++
 configs/P3041DS_SPIFLASH_defconfig | 4 ++++
 configs/P3041DS_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index b315840..87958db 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 50dee40..90a0efe 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 984ff5f..7682877 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 5728cbb..ce9289f 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

[U-Boot] [PATCH 36/47] dm: pcie_fsl: Add P4080 PCIe support

[Hou Zhiqiang]

Add compatible string for P4080 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index a4e0cd1..f61e39e 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -630,6 +630,7 @@ static const struct udevice_id fsl_pcie_ids[] = {
 	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
 	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
+	{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

[U-Boot] [PATCH 37/47] P4080: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p4080.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 7c8dbae..ab76680 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -80,4 +80,40 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe200000 {
+		compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe201000 {
+		compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe202000 {
+		compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 38/47] configs: P4080DS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P4080DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/P4080DS_SDCARD_defconfig   | 4 ++++
 configs/P4080DS_SPIFLASH_defconfig | 4 ++++
 configs/P4080DS_defconfig          | 4 ++++
 3 files changed, 12 insertions(+)

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 0aaf09a..5e5b30c 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 3a91df2..29560f3 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index d89d69f..aa42a0b 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

[U-Boot] [PATCH 39/47] dm: pcie_fsl: Add P5040 PCIe support

[Hou Zhiqiang]

Add compatible string for P5040 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index f61e39e..1411b1f 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -631,6 +631,7 @@ static const struct udevice_id fsl_pcie_ids[] = {
 	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
+	{ .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
 	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
-- 
2.9.5

[U-Boot] [PATCH 40/47] P5040: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/p5040.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index b6f6c5d..8ab123d 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -59,4 +59,40 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe200000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe201000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe202000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5

[U-Boot] [PATCH 41/47] configs: P5040DS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in P5040DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/P5040DS_NAND_defconfig     | 4 ++++
 configs/P5040DS_SDCARD_defconfig   | 4 ++++
 configs/P5040DS_SPIFLASH_defconfig | 4 ++++
 configs/P5040DS_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index cbccb4c..bab7561 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index cdefb2d..517708a 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index c636b16..cb019f2 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 6572ff1..31a8fca 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.9.5

[U-Boot] [PATCH 42/47] powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally

[Hou Zhiqiang]

Compile the legacy PCIe initialization reoutines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/mpc8548cds/mpc8548cds.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 7d819d8..2799b5b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -164,7 +164,7 @@ void lbc_sdram_init(void)
 #endif	/* enable SDRAM init */
 }
 
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
 /* For some reason the Tundra PCI bridge shows up on itself as a
  * different device.  Work around that by refusing to configure it.
  */
@@ -189,6 +189,7 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 static struct pci_controller pci1_hose;
 #endif	/* CONFIG_PCI */
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -268,6 +269,7 @@ void pci_init_board(void)
 
 	fsl_pcie_init_board(first_free_busno);
 }
+#endif
 
 void configure_rgmii(void)
 {
@@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
-#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
 void ft_pci_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
-- 
2.9.5

[U-Boot] [PATCH 43/47] powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected

[Hou Zhiqiang]

Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 board/freescale/common/cds_pci_ft.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index 3ff2fa4..fb2e5c7 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -9,6 +9,7 @@
 #include "cadmus.h"
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 static void cds_pci_fixup(void *blob)
 {
 	int node;
@@ -61,11 +62,12 @@ static void cds_pci_fixup(void *blob)
 		}
 	}
 }
+#endif
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 	ft_pci_setup(blob, bd);
 	cds_pci_fixup(blob);
 #endif
-- 
2.9.5

[U-Boot] [PATCH 44/47] dm: pcie_fsl: Add MPC8548 PCIe support

[Hou Zhiqiang]

Add compatible string for MPC8548 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 drivers/pci/pcie_fsl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 1411b1f..112f3b9 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -627,6 +627,7 @@ static struct fsl_pcie_data t2080_data = {
 };
 
 static const struct udevice_id fsl_pcie_ids[] = {
+	{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
 	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
 	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
 	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
-- 
2.9.5

[U-Boot] [PATCH 45/47] MPC8548: dts: Added PCIe DT node

[Hou Zhiqiang]

MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/powerpc/dts/mpc8548-post.dtsi  | 9 +++++++++
 arch/powerpc/dts/mpc8548cds.dts     | 6 ++++++
 arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi
index 5533a4b..2206f2d 100644
--- a/arch/powerpc/dts/mpc8548-post.dtsi
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -25,3 +25,12 @@
 		last-interrupt-source = <255>;
 	};
 };
+
+&pcie {
+	compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
index cceea34..3b927bd 100644
--- a/arch/powerpc/dts/mpc8548cds.dts
+++ b/arch/powerpc/dts/mpc8548cds.dts
@@ -18,6 +18,12 @@
 	soc: soc8548 at e0000000 {
 		ranges = <0x0 0x0 0xe0000000 0x100000>;
 	};
+
+	pcie: pcie at e000a000 {
+		reg = <0x0 0xe000a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts
index faff35c..98d7c24 100644
--- a/arch/powerpc/dts/mpc8548cds_36b.dts
+++ b/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -18,6 +18,12 @@
 	soc: soc8548 at fe0000000 {
 		ranges = <0x0 0xf 0xe0000000 0x100000>;
 	};
+
+	pcie: pcie at fe000a000 {
+		reg = <0xf 0xe000a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
 
 /include/ "mpc8548-post.dtsi"
-- 
2.9.5

[U-Boot] [PATCH 46/47] powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled

[Hou Zhiqiang]

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 include/configs/MPC8548CDS.h | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4252fbe..4809bbd 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -18,8 +18,6 @@
 #define CONFIG_PCI1		/* PCI controller 1 */
 #define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
 #undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME		"Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
 /*
@@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT		1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	1
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#endif
+
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
 #endif	/* CONFIG_PCI */
-- 
2.9.5

[U-Boot] [PATCH 47/47] configs: MPC8548CDS: Enable PCIe driver

[Hou Zhiqiang]

Enable the DM PCIe driver in MPC8548CDS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 configs/MPC8548CDS_36BIT_defconfig  | 4 ++++
 configs/MPC8548CDS_defconfig        | 4 ++++
 configs/MPC8548CDS_legacy_defconfig | 4 ++++
 3 files changed, 12 insertions(+)

diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index f259f19..102716b 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -26,6 +26,10 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 72239da..9cccb60 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index f2420c3..782f827 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_CONS_INDEX=2
-- 
2.9.5

[U-Boot] [PATCH 01/47] powerpc: T208xRDB: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:21 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines only when
> DM_PCI is not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/t208xrdb/pci.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 02/47] powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:21 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/T208xRDB.h | 36 +++++++++++++++++++-----------------
>  1 file changed, 19 insertions(+), 17 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Bin Meng]

Hi Zhiqiang,

On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in T2080RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/T2080RDB_NAND_defconfig     | 4 ++++
>  configs/T2080RDB_SDCARD_defconfig   | 4 ++++
>  configs/T2080RDB_SPIFLASH_defconfig | 4 ++++
>  configs/T2080RDB_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>
> diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
> index 7eb7058..30ec72b 100644
> --- a/configs/T2080RDB_NAND_defconfig
> +++ b/configs/T2080RDB_NAND_defconfig
> @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y

Why do we need this option? I vaguely remember I commented in as
similar patch for some other board (maybe layerscape arm?)

> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
> index 9ea6698..22c2e05 100644
> --- a/configs/T2080RDB_SDCARD_defconfig
> +++ b/configs/T2080RDB_SDCARD_defconfig
> @@ -56,6 +56,10 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
> index 988897b..e70fa0d 100644
> --- a/configs/T2080RDB_SPIFLASH_defconfig
> +++ b/configs/T2080RDB_SPIFLASH_defconfig
> @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_STMICRO=y
>  CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
> +CONFIG_DM=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_MII=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
> diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
> index 3f7e282..b620349 100644
> --- a/configs/T2080RDB_defconfig
> +++ b/configs/T2080RDB_defconfig
> @@ -45,6 +45,10 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> --

Regards,
Bin

[U-Boot] [PATCH 04/47] powerpc: T4RDB: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:25 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines only when
> DM_PCI is not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/t4rdb/pci.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 05/47] dm: pcie_fsl: Add T4240 PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:32 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for T4240 PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 06/47] t4240: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> T4240 integrated 4 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 3.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/t4240.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 07/47] powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:23 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/T4240RDB.h | 35 +++++++++++++++++++----------------
>  1 file changed, 19 insertions(+), 16 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 08/47] configs: T4240RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:34 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in T4240RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/T4240RDB_SDCARD_defconfig | 4 ++++
>  configs/T4240RDB_defconfig        | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
> index a70c237..cce4872 100644
> --- a/configs/T4240RDB_SDCARD_defconfig
> +++ b/configs/T4240RDB_SDCARD_defconfig
> @@ -50,6 +50,10 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_GIGE=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y

Again, why is this option needed?

> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
> index d4ce176..bdadfa8 100644
> --- a/configs/T4240RDB_defconfig
> +++ b/configs/T4240RDB_defconfig
> @@ -39,6 +39,10 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_GIGE=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> --

Regards,
Bin

[U-Boot] [PATCH 09/47] powerpc: T102xRDB: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines only when
> DM_PCI is not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/t102xrdb/pci.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 10/47] dm: pcie_fsl: Add T102x PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:37 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for T102x PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 11/47] t102x: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:27 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> T102x integrated 3 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/t102x.dtsi | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 12/47] powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040

[Bin Meng]

On Tue, Jul 23, 2019 at 9:31 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and
> the PCIE4 related macros, as there are only 3 PCIe controllers
> on T102x SoCs.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/T102xRDB.h | 24 ------------------------
>  1 file changed, 24 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

Hi Zhiqiang,

On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/T102xRDB.h | 54 +++++++++++++---------------------------------
>  1 file changed, 15 insertions(+), 39 deletions(-)
>
> diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
> index 3715e25..4fb1709 100644
> --- a/include/configs/T102xRDB.h
> +++ b/include/configs/T102xRDB.h
> @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void);
>  #define CONFIG_PCIE1           /* PCIE controller 1 */
>  #define CONFIG_PCIE2           /* PCIE controller 2 */
>  #define CONFIG_PCIE3           /* PCIE controller 3 */
> -#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
>  #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
> -#define CONFIG_PCI_INDIRECT_BRIDGE
>
>  #ifdef CONFIG_PCI
>  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
>  #ifdef CONFIG_PCIE1
>  #define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define        CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
>  #define        CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
> -#else
> -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> -#endif
> -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
>  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> -#else
> -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> -#endif
> -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
>  #endif
>
>  /* controller 2, Slot 2, tgtid 2, Base address 201000 */
>  #ifdef CONFIG_PCIE2
>  #define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
> -#else
> -#define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS      0x90000000
> -#endif
> -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
>  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> -#else
> -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> -#endif
> -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
>  #endif
>
>  /* controller 3, Slot 1, tgtid 1, Base address 202000 */
>  #ifdef CONFIG_PCIE3
>  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
> -#else
> -#define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
> -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xa0000000
> -#endif
> -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /* 256M */
>  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> -#else
> -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
>  #endif
> +
> +#if !defined(CONFIG_DM_PCI)
> +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000

What about the #ifdef CONFIG_PHYS_64BIT part?

> +#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
> +#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000 /* 256M */
> +#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /* 256M */
> +#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
>  #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_PCI_INDIRECT_BRIDGE
>  #endif
>
>  #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
> --

Regards,
Bin

[U-Boot] [PATCH 15/47] powerpc: T104xRDB: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:37 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines only when
> DM_PCI is not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/t104xrdb/pci.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 16/47] dm: pcie_fsl: Add T104x PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:38 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for T104x PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 17/47] t104x: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> T104x integrated 4 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/t104x.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 18/47] powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:26 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/T104xRDB.h | 38 ++++++++++++++++++++------------------
>  1 file changed, 20 insertions(+), 18 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 20/47] powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:37 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines for P1020,
> P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI
> is not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 21/47] dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs

[Bin Meng]

On Tue, Jul 23, 2019 at 9:45 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for PCIe of P1020, P1021, P1024, P1025
> and P2020 SoCs.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 23/47] powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:37 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
> for P1020, P1021, P1024, P1025 and P2020 RDB boards.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/p1_p2_rdb_pc.h | 36 +++++++++++++++++++++++-------------
>  1 file changed, 23 insertions(+), 13 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Bin Meng]

Hi Zhiqiang,

On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P1020 integrated 2 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p1020-post.dtsi     | 20 ++++++++++++++++++++
>  arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
>  arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
>  arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
>  4 files changed, 56 insertions(+)
>
> diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
> index e1a4f50..1e5e678 100644
> --- a/arch/powerpc/dts/p1020-post.dtsi
> +++ b/arch/powerpc/dts/p1020-post.dtsi
> @@ -25,3 +25,23 @@
>                 last-interrupt-source = <255>;
>         };
>  };
> +
> +/* PCIe controller base address 0x9000 */
> +&pci1 {
> +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> +       law_trgt_if = <1>;
> +       #address-cells = <3>;
> +       #size-cells = <2>;
> +       device_type = "pci";
> +       bus-range = <0x0 0xff>;
> +};
> +
> +/* PCIe controller base address 0xa000 */
> +&pci0 {
> +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> +       law_trgt_if = <2>;
> +       #address-cells = <3>;
> +       #size-cells = <2>;
> +       device_type = "pci";
> +       bus-range = <0x0 0xff>;
> +};
> diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
> index fd68b8b..7ebaa61 100644
> --- a/arch/powerpc/dts/p1020rdb-pc.dts
> +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> @@ -18,6 +18,18 @@
>         soc: soc at ffe00000 {
>                 ranges = <0x0 0x0 0xffe00000 0x100000>;
>         };
> +
> +       pci1: pcie at ffe09000 {

Why this is named as pci1?

> +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers */

Shouldn't the <reg> property be put in the dtsi file?

> +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
> +
> +       pci0: pcie at ffe0a000 {

and this is pci0?

> +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
>  };
>
>  /include/ "p1020-post.dtsi"
> diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
> index a23d031..c0e5ef4 100644
> --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
> +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
> @@ -18,6 +18,18 @@
>         soc: soc at fffe00000 {
>                 ranges = <0x0 0xf 0xffe00000 0x100000>;
>         };
> +
> +       pci1: pcie at fffe09000 {
> +               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
> +
> +       pci0: pcie at fffe0a000 {
> +               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
>  };
>
>  /include/ "p1020-post.dtsi"
> diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
> index 81f25a3..21174a0 100644
> --- a/arch/powerpc/dts/p1020rdb-pd.dts
> +++ b/arch/powerpc/dts/p1020rdb-pd.dts
> @@ -18,6 +18,18 @@
>         soc: soc at ffe00000 {
>                 ranges = <0x0 0x0 0xffe00000 0x100000>;
>         };
> +
> +       pci1: pcie at ffe09000 {
> +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
> +
> +       pci0: pcie at ffe0a000 {
> +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
>  };
>
>  /include/ "p1020-post.dtsi"
> --

Regards,
Bin

[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P2020 integrated 3 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p2020-post.dtsi     | 30 ++++++++++++++++++++++++++++++
>  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
>  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
>  3 files changed, 64 insertions(+)
>
> diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
> index f20d1fa..f696f35 100644
> --- a/arch/powerpc/dts/p2020-post.dtsi
> +++ b/arch/powerpc/dts/p2020-post.dtsi
> @@ -25,3 +25,33 @@
>                 last-interrupt-source = <255>;
>         };
>  };
> +
> +/* PCIe controller base address 0x8000 */
> +&pci2 {

pci0?

> +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> +       law_trgt_if = <0>;
> +       #address-cells = <3>;
> +       #size-cells = <2>;
> +       device_type = "pci";
> +       bus-range = <0x0 0xff>;
> +};
> +
> +/* PCIe controller base address 0x9000 */
> +&pci1 {
> +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> +       law_trgt_if = <1>;
> +       #address-cells = <3>;
> +       #size-cells = <2>;
> +       device_type = "pci";
> +       bus-range = <0x0 0xff>;
> +};
> +
> +/* PCIe controller base address 0xa000 */
> +&pci0 {

pci2?

> +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> +       law_trgt_if = <2>;
> +       #address-cells = <3>;
> +       #size-cells = <2>;
> +       device_type = "pci";
> +       bus-range = <0x0 0xff>;
> +};
> diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
> index 4800b76..08befd4 100644
> --- a/arch/powerpc/dts/p2020rdb-pc.dts
> +++ b/arch/powerpc/dts/p2020rdb-pc.dts
> @@ -18,6 +18,23 @@
>         soc: soc at ffe00000 {
>                 ranges = <0x0 0x0 0xffe00000 0x100000>;
>         };
> +
> +       pci2: pcie at ffe08000 {
> +               reg = <0x0 0xffe08000 0x0 0x1000>;      /* registers */

put <reg> in dtsi?

> +               status = "disabled";
> +       };
> +
> +       pci1: pcie at ffe09000 {
> +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
> +
> +       pci0: pcie at ffe0a000 {
> +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
>  };
>
>  /include/ "p2020-post.dtsi"
> diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> index 8323b90..04b2519 100644
> --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> @@ -18,6 +18,23 @@
>         soc: soc at fffe00000 {
>                 ranges = <0x0 0xf 0xffe00000 0x100000>;
>         };
> +
> +       pci2: pcie at fffe08000 {
> +               reg = <0xf 0xffe08000 0x0 0x1000>;      /* registers */
> +               status = "disabled";
> +       };
> +
> +       pci1: pcie at fffe09000 {
> +               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
> +
> +       pci0: pcie at fffe0a000 {
> +               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers */
> +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
> +                         0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
> +       };
>  };
>
>  /include/ "p2020-post.dtsi"
> --

Regards,
Bin

[U-Boot] [PATCH 27/47] powerpc: p_corenet: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:27 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines for P2041RDB,
> P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
>  not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/common/p_corenet/pci.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 28/47] dm: pcie_fsl: Add P2041 PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:42 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for P2041 PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 29/47] P2041: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P2041 integrated 3 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p2041.dtsi | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:44 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/P2041RDB.h | 55 +++++++++++++---------------------------------
>  1 file changed, 15 insertions(+), 40 deletions(-)
>
> diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
> index b433308..ba670d7 100644
> --- a/include/configs/P2041RDB.h
> +++ b/include/configs/P2041RDB.h
> @@ -37,7 +37,6 @@
>  #define CONFIG_PCIE1                   /* PCIE controller 1 */
>  #define CONFIG_PCIE2                   /* PCIE controller 2 */
>  #define CONFIG_PCIE3                   /* PCIE controller 3 */
> -#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
>  #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
>
>  #define CONFIG_SYS_SRIO
> @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy);
>
>  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
>  #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
> -#else
> -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> -#endif
> -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
>  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> -#else
> -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> -#endif
> -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
>
>  /* controller 2, Slot 2, tgtid 2, Base address 201000 */
>  #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
> -#else
> -#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
> -#endif
> -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
>  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> -#else
> -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> -#endif
> -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
>
>  /* controller 3, Slot 1, tgtid 1, Base address 202000 */
>  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
> -#else
> -#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
> -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
> -#endif
> -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
>  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> -#else
> -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
> -#endif
> -#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
>
>  /* Qman/Bman */
>  #define CONFIG_SYS_BMAN_NUM_PORTALS    10
> @@ -489,7 +449,22 @@ unsigned long get_board_sys_clk(unsigned long dummy);
>  #endif
>
>  #ifdef CONFIG_PCI
> +#if !defined(CONFIG_DM_PCI)
> +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
>  #define CONFIG_PCI_INDIRECT_BRIDGE
> +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000

missing CONFIG_PHYS_64BIT?

> +#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> +#endif
>
>  #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
>  #endif /* CONFIG_PCI */
> --

Regards,
Bin

[U-Boot] [PATCH 32/47] dm: pcie_fsl: Add P3041 PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:30 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for P3041 PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 33/47] P3041: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P3041 integrated 4 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p3041.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/corenet_ds.h | 63 +++++++++++++-------------------------------
>  1 file changed, 19 insertions(+), 44 deletions(-)
>
> diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
> index f974291..07844c1 100644
> --- a/include/configs/corenet_ds.h
> +++ b/include/configs/corenet_ds.h
> @@ -54,7 +54,6 @@
>  #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
>  #define CONFIG_PCIE1                   /* PCIE controller 1 */
>  #define CONFIG_PCIE2                   /* PCIE controller 2 */
> -#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
>  #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
>
>  #define CONFIG_ENV_OVERWRITE
> @@ -362,68 +361,25 @@
>
>  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
>  #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
> -#else
> -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> -#endif
> -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
>  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> -#else
> -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> -#endif
> -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
>
>  /* controller 2, Slot 2, tgtid 2, Base address 201000 */
>  #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
> -#else
> -#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
> -#endif
> -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
>  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> -#else
> -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> -#endif
> -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
>
>  /* controller 3, Slot 1, tgtid 1, Base address 202000 */
>  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
> -#else
> -#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
> -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
> -#endif
> -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
>  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> -#ifdef CONFIG_PHYS_64BIT
>  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> -#else
> -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
> -#endif
> -#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
>
>  /* controller 4, Base address 203000 */
> -#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
>  #define CONFIG_SYS_PCIE4_MEM_PHYS      0xc60000000ull
> -#define CONFIG_SYS_PCIE4_MEM_SIZE      0x20000000      /* 512M */
> -#define CONFIG_SYS_PCIE4_IO_BUS                0x00000000
>  #define CONFIG_SYS_PCIE4_IO_PHYS       0xff8030000ull
> -#define CONFIG_SYS_PCIE4_IO_SIZE       0x00010000      /* 64k */
>
>  /* Qman/Bman */
>  #define CONFIG_SYS_BMAN_NUM_PORTALS    10
> @@ -505,7 +461,26 @@
>  #endif
>
>  #ifdef CONFIG_PCI
> +#if !defined(CONFIG_DM_PCI)
> +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
>  #define CONFIG_PCI_INDIRECT_BRIDGE
> +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000

CONFIG_PHYS_64BIT?

> +#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> +#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
> +#define CONFIG_SYS_PCIE4_MEM_SIZE      0x20000000      /* 512M */
> +#define CONFIG_SYS_PCIE4_IO_BUS                0x00000000
> +#define CONFIG_SYS_PCIE4_IO_SIZE       0x00010000      /* 64k */
> +#endif
>
>  #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
>  #endif /* CONFIG_PCI */
> --

Regards,
Bin

[U-Boot] [PATCH 36/47] dm: pcie_fsl: Add P4080 PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:35 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for P4080 PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 37/47] P4080: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:41 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P4080 integrated 3 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p4080.dtsi | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 39/47] dm: pcie_fsl: Add P5040 PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:43 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for P5040 PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 40/47] P5040: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:30 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P5040 integrated 3 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 2.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p5040.dtsi | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 42/47] powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally

[Bin Meng]

On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Compile the legacy PCIe initialization reoutines only when
> DM_PCI is not enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/mpc8548cds/mpc8548cds.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 43/47] powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected

[Bin Meng]

On Tue, Jul 23, 2019 at 9:43 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  board/freescale/common/cds_pci_ft.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 44/47] dm: pcie_fsl: Add MPC8548 PCIe support

[Bin Meng]

On Tue, Jul 23, 2019 at 9:44 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Add compatible string for MPC8548 PCIe.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/pcie_fsl.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 45/47] MPC8548: dts: Added PCIe DT node

[Bin Meng]

On Tue, Jul 23, 2019 at 9:30 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> MPC8548 integrated a PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
> patch is to add DT node for the PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/mpc8548-post.dtsi  | 9 +++++++++
>  arch/powerpc/dts/mpc8548cds.dts     | 6 ++++++
>  arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++++++
>  3 files changed, 21 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 46/47] powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/MPC8548CDS.h | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月26日 22:48
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
> 
> Hi Zhiqiang,
> 
> On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > Enable the DM PCIe driver in T2080RDB defconfig.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  configs/T2080RDB_NAND_defconfig     | 4 ++++
> >  configs/T2080RDB_SDCARD_defconfig   | 4 ++++
> >  configs/T2080RDB_SPIFLASH_defconfig | 4 ++++
> >  configs/T2080RDB_defconfig          | 4 ++++
> >  4 files changed, 16 insertions(+)
> >
> > diff --git a/configs/T2080RDB_NAND_defconfig
> > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b 100644
> > --- a/configs/T2080RDB_NAND_defconfig
> > +++ b/configs/T2080RDB_NAND_defconfig
> > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> 
> Why do we need this option? I vaguely remember I commented in as similar
> patch for some other board (maybe layerscape arm?)

We discussed this during adding PCIe DM driver on T2080QDS, so it's the same
reason.

Thanks,
Zhiqiang

> 
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > diff --git a/configs/T2080RDB_SDCARD_defconfig
> > b/configs/T2080RDB_SDCARD_defconfig
> > index 9ea6698..22c2e05 100644
> > --- a/configs/T2080RDB_SDCARD_defconfig
> > +++ b/configs/T2080RDB_SDCARD_defconfig
> > @@ -56,6 +56,10 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > diff --git a/configs/T2080RDB_SPIFLASH_defconfig
> > b/configs/T2080RDB_SPIFLASH_defconfig
> > index 988897b..e70fa0d 100644
> > --- a/configs/T2080RDB_SPIFLASH_defconfig
> > +++ b/configs/T2080RDB_SPIFLASH_defconfig
> > @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_STMICRO=y
> CONFIG_PHYLIB=y
> > CONFIG_PHY_AQUANTIA=y  CONFIG_E1000=y
> > +CONFIG_DM=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_MII=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> > diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
> > index 3f7e282..b620349 100644
> > --- a/configs/T2080RDB_defconfig
> > +++ b/configs/T2080RDB_defconfig
> > @@ -45,6 +45,10 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > --
> 
> Regards,
> Bin

[U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月26日 22:49
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy
> PCIe driver when DM_PCI is enabled
> 
> Hi Zhiqiang,
> 
> On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  include/configs/T102xRDB.h | 54
> > +++++++++++++---------------------------------
> >  1 file changed, 15 insertions(+), 39 deletions(-)
> >
> > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
> > index 3715e25..4fb1709 100644
> > --- a/include/configs/T102xRDB.h
> > +++ b/include/configs/T102xRDB.h
> > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void);
> >  #define CONFIG_PCIE1           /* PCIE controller 1 */
> >  #define CONFIG_PCIE2           /* PCIE controller 2 */
> >  #define CONFIG_PCIE3           /* PCIE controller 3 */
> > -#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> >  #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
> > -#define CONFIG_PCI_INDIRECT_BRIDGE
> >
> >  #ifdef CONFIG_PCI
> >  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
> > #ifdef CONFIG_PCIE1
> >  #define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define        CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
> >  #define        CONFIG_SYS_PCIE1_MEM_PHYS
> 0xc00000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> > -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> > -#endif
> > -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /*
> 256M */
> >  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> > -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> > -#endif
> > -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> >  #endif
> >
> >  /* controller 2, Slot 2, tgtid 2, Base address 201000 */  #ifdef
> > CONFIG_PCIE2
> >  #define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
> > -#define CONFIG_SYS_PCIE2_MEM_PHYS      0x90000000
> > -#endif
> > -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /*
> 256M */
> >  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> > -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> > -#else
> > -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> > -#endif
> > -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> >  #endif
> >
> >  /* controller 3, Slot 1, tgtid 1, Base address 202000 */  #ifdef
> > CONFIG_PCIE3
> >  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
> > -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xa0000000
> > -#endif
> > -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /*
> 256M */
> >  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> > -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> > -#else
> > -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
> >  #endif
> > +
> > +#if !defined(CONFIG_DM_PCI)
> > +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> > +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
> 
> What about the #ifdef CONFIG_PHYS_64BIT part?

In the arch/powerpc/cpu/mpc85xx/Kconfig, all the T102x boards selected
the CONFIG_PHYS_64BIT, so removed the #else...#endif part.

Thanks,
Zhiqiang
> 
> > +#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /*
> 256M */
> > +#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000 /* 256M */
> > +#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /*
> 256M */
> > +#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> >  #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k
> */
> > +#define CONFIG_PCI_INDIRECT_BRIDGE
> >  #endif
> >
> >  #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on
> startup */
> > --
> 
> Regards,
> Bin

[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> 
> Hi Zhiqiang,
> 
> On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > P1020 integrated 2 PCIe controllers, which is compatible with the PCI
> > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > DT node for each PCIe controller.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  arch/powerpc/dts/p1020-post.dtsi     | 20 ++++++++++++++++++++
> >  arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
> >  arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
> >  arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
> >  4 files changed, 56 insertions(+)
> >
> > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > b/arch/powerpc/dts/p1020-post.dtsi
> > index e1a4f50..1e5e678 100644
> > --- a/arch/powerpc/dts/p1020-post.dtsi
> > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > @@ -25,3 +25,23 @@
> >                 last-interrupt-source = <255>;
> >         };
> >  };
> > +
> > +/* PCIe controller base address 0x9000 */
> > +&pci1 {
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <1>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0xa000 */
> > +&pci0 {
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <2>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > b/arch/powerpc/dts/p1020rdb-pc.dts
> > index fd68b8b..7ebaa61 100644
> > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > @@ -18,6 +18,18 @@
> >         soc: soc at ffe00000 {
> >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci1: pcie at ffe09000 {
> 
> Why this is named as pci1?

The P1020 reference manual said the first controller registers offset begin at 0xa000
and the second begin at 0x9000.

> 
> > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers
> */
> 
> Shouldn't the <reg> property be put in the dtsi file?

The registers starting addresses are different between 32bit and 36bit dts.

Thanks,
Zhiqiang

> 
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xa0000000 0x0
> 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at ffe0a000 {
> 
> and this is pci0?
> 
> > +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0x0
> 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p1020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > b/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > index a23d031..c0e5ef4 100644
> > --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > @@ -18,6 +18,18 @@
> >         soc: soc at fffe00000 {
> >                 ranges = <0x0 0xf 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci1: pcie at fffe09000 {
> > +               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xc0000000 0xc
> 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at fffe0a000 {
> > +               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0xc
> 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p1020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p1020rdb-pd.dts
> > b/arch/powerpc/dts/p1020rdb-pd.dts
> > index 81f25a3..21174a0 100644
> > --- a/arch/powerpc/dts/p1020rdb-pd.dts
> > +++ b/arch/powerpc/dts/p1020rdb-pd.dts
> > @@ -18,6 +18,18 @@
> >         soc: soc at ffe00000 {
> >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci1: pcie at ffe09000 {
> > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xa0000000 0x0
> 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at ffe0a000 {
> > +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0x0
> 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p1020-post.dtsi"
> > --
> 
> Regards,
> Bin

[U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

Hi Zhiqiang,

On Tue, Aug 27, 2019 at 10:33 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年8月26日 22:49
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> > Subject: Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy
> > PCIe driver when DM_PCI is enabled
> >
> > Hi Zhiqiang,
> >
> > On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > wrote:
> > >
> > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > >  include/configs/T102xRDB.h | 54
> > > +++++++++++++---------------------------------
> > >  1 file changed, 15 insertions(+), 39 deletions(-)
> > >
> > > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
> > > index 3715e25..4fb1709 100644
> > > --- a/include/configs/T102xRDB.h
> > > +++ b/include/configs/T102xRDB.h
> > > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void);
> > >  #define CONFIG_PCIE1           /* PCIE controller 1 */
> > >  #define CONFIG_PCIE2           /* PCIE controller 2 */
> > >  #define CONFIG_PCIE3           /* PCIE controller 3 */
> > > -#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> > >  #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
> > > -#define CONFIG_PCI_INDIRECT_BRIDGE
> > >
> > >  #ifdef CONFIG_PCI
> > >  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
> > > #ifdef CONFIG_PCIE1
> > >  #define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
> > > -#ifdef CONFIG_PHYS_64BIT
> > > -#define        CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
> > >  #define        CONFIG_SYS_PCIE1_MEM_PHYS
> > 0xc00000000ull
> > > -#else
> > > -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> > > -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> > > -#endif
> > > -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /*
> > 256M */
> > >  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> > > -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > > -#ifdef CONFIG_PHYS_64BIT
> > >  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> > > -#else
> > > -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> > > -#endif
> > > -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> > >  #endif
> > >
> > >  /* controller 2, Slot 2, tgtid 2, Base address 201000 */  #ifdef
> > > CONFIG_PCIE2
> > >  #define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
> > > -#ifdef CONFIG_PHYS_64BIT
> > > -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> > >  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
> > > -#else
> > > -#define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
> > > -#define CONFIG_SYS_PCIE2_MEM_PHYS      0x90000000
> > > -#endif
> > > -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /*
> > 256M */
> > >  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> > > -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > > -#ifdef CONFIG_PHYS_64BIT
> > >  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> > > -#else
> > > -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> > > -#endif
> > > -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> > >  #endif
> > >
> > >  /* controller 3, Slot 1, tgtid 1, Base address 202000 */  #ifdef
> > > CONFIG_PCIE3
> > >  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
> > > -#ifdef CONFIG_PHYS_64BIT
> > > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> > >  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
> > > -#else
> > > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
> > > -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xa0000000
> > > -#endif
> > > -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /*
> > 256M */
> > >  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> > > -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> > > -#ifdef CONFIG_PHYS_64BIT
> > >  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> > > -#else
> > > -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
> > >  #endif
> > > +
> > > +#if !defined(CONFIG_DM_PCI)
> > > +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> > > +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
> >
> > What about the #ifdef CONFIG_PHYS_64BIT part?
>
> In the arch/powerpc/cpu/mpc85xx/Kconfig, all the T102x boards selected
> the CONFIG_PHYS_64BIT, so removed the #else...#endif part.
>

Thanks for the clarification. With that info,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin

[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Bin Meng]

Hi Zhiqiang,

On Tue, Aug 27, 2019 at 10:05 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年8月26日 22:48
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
> >
> > Hi Zhiqiang,
> >
> > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > wrote:
> > >
> > > Enable the DM PCIe driver in T2080RDB defconfig.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > >  configs/T2080RDB_NAND_defconfig     | 4 ++++
> > >  configs/T2080RDB_SDCARD_defconfig   | 4 ++++
> > >  configs/T2080RDB_SPIFLASH_defconfig | 4 ++++
> > >  configs/T2080RDB_defconfig          | 4 ++++
> > >  4 files changed, 16 insertions(+)
> > >
> > > diff --git a/configs/T2080RDB_NAND_defconfig
> > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b 100644
> > > --- a/configs/T2080RDB_NAND_defconfig
> > > +++ b/configs/T2080RDB_NAND_defconfig
> > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
> > >  CONFIG_PHY_AQUANTIA=y
> > >  CONFIG_E1000=y
> > >  CONFIG_MII=y
> > > +CONFIG_DM=y
> > > +CONFIG_DM_PCI=y
> > > +CONFIG_DM_PCI_COMPAT=y
> >
> > Why do we need this option? I vaguely remember I commented in as similar
> > patch for some other board (maybe layerscape arm?)
>
> We discussed this during adding PCIe DM driver on T2080QDS, so it's the same
> reason.

I dug into the mailing list archive, and I see:
https://lists.denx.de/pipermail/u-boot/2019-May/370756.html

In that thread, you wrote:

"I will submit a patch to remove the DM_PCI_COMPAT when all driver has
been converted."

So I believe you guys have not converted all PowerPC drivers to DM,
hence it's still left there?

Regards,
Bin

[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> 
> On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > P2020 integrated 3 PCIe controllers, which is compatible with the PCI
> > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > DT node for each PCIe controller.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  arch/powerpc/dts/p2020-post.dtsi     | 30
> ++++++++++++++++++++++++++++++
> >  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
> >  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
> >  3 files changed, 64 insertions(+)
> >
> > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > b/arch/powerpc/dts/p2020-post.dtsi
> > index f20d1fa..f696f35 100644
> > --- a/arch/powerpc/dts/p2020-post.dtsi
> > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > @@ -25,3 +25,33 @@
> >                 last-interrupt-source = <255>;
> >         };
> >  };
> > +
> > +/* PCIe controller base address 0x8000 */
> > +&pci2 {
> 
> pci0?

Describe the controller index and starting address according to P2020 RM.

> 
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <0>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0x9000 */
> > +&pci1 {
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <1>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0xa000 */
> > +&pci0 {
> 
> pci2?
> 
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <2>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > diff --git a/arch/powerpc/dts/p2020rdb-pc.dts
> > b/arch/powerpc/dts/p2020rdb-pc.dts
> > index 4800b76..08befd4 100644
> > --- a/arch/powerpc/dts/p2020rdb-pc.dts
> > +++ b/arch/powerpc/dts/p2020rdb-pc.dts
> > @@ -18,6 +18,23 @@
> >         soc: soc at ffe00000 {
> >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci2: pcie at ffe08000 {
> > +               reg = <0x0 0xffe08000 0x0 0x1000>;      /* registers
> */
> 
> put <reg> in dtsi?

The same reason as P1020, see #22 of this series.

Thanks,
Zhiqiang

> 
> > +               status = "disabled";
> > +       };
> > +
> > +       pci1: pcie at ffe09000 {
> > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xa0000000 0x0
> 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at ffe0a000 {
> > +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0x0
> 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p2020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > index 8323b90..04b2519 100644
> > --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > @@ -18,6 +18,23 @@
> >         soc: soc at fffe00000 {
> >                 ranges = <0x0 0xf 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci2: pcie at fffe08000 {
> > +               reg = <0xf 0xffe08000 0x0 0x1000>;      /* registers
> */
> > +               status = "disabled";
> > +       };
> > +
> > +       pci1: pcie at fffe09000 {
> > +               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xc0000000 0xc
> 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at fffe0a000 {
> > +               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0xc
> 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p2020-post.dtsi"
> > --
> 
> Regards,
> Bin

[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Bin Meng]

Hi Zhiqiang,

On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年8月26日 22:50
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> >
> > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > wrote:
> > >
> > > P2020 integrated 3 PCIe controllers, which is compatible with the PCI
> > > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > > DT node for each PCIe controller.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > >  arch/powerpc/dts/p2020-post.dtsi     | 30
> > ++++++++++++++++++++++++++++++
> > >  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
> > >  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
> > >  3 files changed, 64 insertions(+)
> > >
> > > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > > b/arch/powerpc/dts/p2020-post.dtsi
> > > index f20d1fa..f696f35 100644
> > > --- a/arch/powerpc/dts/p2020-post.dtsi
> > > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > > @@ -25,3 +25,33 @@
> > >                 last-interrupt-source = <255>;
> > >         };
> > >  };
> > > +
> > > +/* PCIe controller base address 0x8000 */
> > > +&pci2 {
> >
> > pci0?
>
> Describe the controller index and starting address according to P2020 RM.

OK, so will this weird index number (2, 1, 0) break the index
calculation log in the following patch?
http://patchwork.ozlabs.org/patch/1152811/

Regards,
Bin

[U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy
> PCIe driver when DM_PCI is enabled
> 
> On Tue, Jul 23, 2019 at 9:44 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  include/configs/P2041RDB.h | 55
> > +++++++++++++---------------------------------
> >  1 file changed, 15 insertions(+), 40 deletions(-)
> >
> > diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
> > index b433308..ba670d7 100644
> > --- a/include/configs/P2041RDB.h
> > +++ b/include/configs/P2041RDB.h
> > @@ -37,7 +37,6 @@
> >  #define CONFIG_PCIE1                   /* PCIE controller 1 */
> >  #define CONFIG_PCIE2                   /* PCIE controller 2 */
> >  #define CONFIG_PCIE3                   /* PCIE controller 3 */
> > -#define CONFIG_FSL_PCI_INIT            /* Use common FSL init
> code */
> >  #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI
> resources */
> >
> >  #define CONFIG_SYS_SRIO
> > @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long
> > dummy);
> >
> >  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
> >  #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> > -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> > -#endif
> > -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /*
> 512M */
> >  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> > -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> > -#endif
> > -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* controller 2, Slot 2, tgtid 2, Base address 201000 */
> >  #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
> > -#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
> > -#endif
> > -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /*
> 512M */
> >  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> > -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> > -#else
> > -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> > -#endif
> > -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* controller 3, Slot 1, tgtid 1, Base address 202000 */
> >  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
> > -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
> > -#endif
> > -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /*
> 512M */
> >  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> > -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> > -#else
> > -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
> > -#endif
> > -#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* Qman/Bman */
> >  #define CONFIG_SYS_BMAN_NUM_PORTALS    10
> > @@ -489,7 +449,22 @@ unsigned long get_board_sys_clk(unsigned long
> > dummy);  #endif
> >
> >  #ifdef CONFIG_PCI
> > +#if !defined(CONFIG_DM_PCI)
> > +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> >  #define CONFIG_PCI_INDIRECT_BRIDGE
> > +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
> 
> missing CONFIG_PHYS_64BIT?

The P2041RDB board selected CONFIG_PHYS_64BIT, so removed these unused macros.

Thanks,
Zhiqiang

> 
> > +#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> > +#endif
> >
> >  #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on
> startup */
> >  #endif /* CONFIG_PCI */
> > --
> 
> Regards,
> Bin

[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Bin Meng]

Hi Zhiqiang,

On Tue, Aug 27, 2019 at 10:46 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年8月26日 22:50
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> > Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> >
> > Hi Zhiqiang,
> >
> > On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > wrote:
> > >
> > > P1020 integrated 2 PCIe controllers, which is compatible with the PCI
> > > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > > DT node for each PCIe controller.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > >  arch/powerpc/dts/p1020-post.dtsi     | 20 ++++++++++++++++++++
> > >  arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
> > >  arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
> > >  arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
> > >  4 files changed, 56 insertions(+)
> > >
> > > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > > b/arch/powerpc/dts/p1020-post.dtsi
> > > index e1a4f50..1e5e678 100644
> > > --- a/arch/powerpc/dts/p1020-post.dtsi
> > > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > > @@ -25,3 +25,23 @@
> > >                 last-interrupt-source = <255>;
> > >         };
> > >  };
> > > +
> > > +/* PCIe controller base address 0x9000 */
> > > +&pci1 {
> > > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > +       law_trgt_if = <1>;
> > > +       #address-cells = <3>;
> > > +       #size-cells = <2>;
> > > +       device_type = "pci";
> > > +       bus-range = <0x0 0xff>;
> > > +};
> > > +
> > > +/* PCIe controller base address 0xa000 */
> > > +&pci0 {
> > > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > +       law_trgt_if = <2>;
> > > +       #address-cells = <3>;
> > > +       #size-cells = <2>;
> > > +       device_type = "pci";
> > > +       bus-range = <0x0 0xff>;
> > > +};
> > > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > > b/arch/powerpc/dts/p1020rdb-pc.dts
> > > index fd68b8b..7ebaa61 100644
> > > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > > @@ -18,6 +18,18 @@
> > >         soc: soc at ffe00000 {
> > >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> > >         };
> > > +
> > > +       pci1: pcie at ffe09000 {
> >
> > Why this is named as pci1?
>
> The P1020 reference manual said the first controller registers offset begin at 0xa000
> and the second begin at 0x9000.
>
> >
> > > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers
> > */
> >
> > Shouldn't the <reg> property be put in the dtsi file?
>
> The registers starting addresses are different between 32bit and 36bit dts.
>

I see. But looks they are inconsistent. Some of the platforms put the
reg in the dtsi, and some do not. I believe it's because some
platforms force to select CONFIG_PHYS_64BIT hence no need to have two
version of <reg> in DT?

Regards,
Bin

[U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy
> PCIe driver when DM_PCI is enabled
> 
> On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> wrote:
> >
> > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  include/configs/corenet_ds.h | 63
> > +++++++++++++-------------------------------
> >  1 file changed, 19 insertions(+), 44 deletions(-)
> >
> > diff --git a/include/configs/corenet_ds.h
> > b/include/configs/corenet_ds.h index f974291..07844c1 100644
> > --- a/include/configs/corenet_ds.h
> > +++ b/include/configs/corenet_ds.h
> > @@ -54,7 +54,6 @@
> >  #define CONFIG_SYS_NUM_CPC
> CONFIG_SYS_NUM_DDR_CTLRS
> >  #define CONFIG_PCIE1                   /* PCIE controller 1 */
> >  #define CONFIG_PCIE2                   /* PCIE controller 2 */
> > -#define CONFIG_FSL_PCI_INIT            /* Use common FSL init
> code */
> >  #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI
> resources */
> >
> >  #define CONFIG_ENV_OVERWRITE
> > @@ -362,68 +361,25 @@
> >
> >  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
> >  #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
> > -#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
> > -#endif
> > -#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /*
> 512M */
> >  #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
> > -#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
> > -#endif
> > -#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* controller 2, Slot 2, tgtid 2, Base address 201000 */
> >  #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
> > -#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
> > -#endif
> > -#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /*
> 512M */
> >  #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
> > -#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
> > -#else
> > -#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
> > -#endif
> > -#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* controller 3, Slot 1, tgtid 1, Base address 202000 */
> >  #define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
> > -#ifdef CONFIG_PHYS_64BIT
> > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
> > -#else
> > -#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
> > -#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
> > -#endif
> > -#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /*
> 512M */
> >  #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
> > -#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> > -#ifdef CONFIG_PHYS_64BIT
> >  #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
> > -#else
> > -#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
> > -#endif
> > -#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* controller 4, Base address 203000 */
> > -#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
> >  #define CONFIG_SYS_PCIE4_MEM_PHYS      0xc60000000ull
> > -#define CONFIG_SYS_PCIE4_MEM_SIZE      0x20000000      /*
> 512M */
> > -#define CONFIG_SYS_PCIE4_IO_BUS                0x00000000
> >  #define CONFIG_SYS_PCIE4_IO_PHYS       0xff8030000ull
> > -#define CONFIG_SYS_PCIE4_IO_SIZE       0x00010000      /* 64k */
> >
> >  /* Qman/Bman */
> >  #define CONFIG_SYS_BMAN_NUM_PORTALS    10
> > @@ -505,7 +461,26 @@
> >  #endif
> >
> >  #ifdef CONFIG_PCI
> > +#if !defined(CONFIG_DM_PCI)
> > +#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
> >  #define CONFIG_PCI_INDIRECT_BRIDGE
> > +#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
> 
> CONFIG_PHYS_64BIT?

All CORENET DS boards selected PHYS_64BIT, so removed these unused macros.

Thanks,
Zhiqiang

> 
> > +#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
> > +#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
> > +#define CONFIG_SYS_PCIE4_MEM_SIZE      0x20000000      /*
> 512M */
> > +#define CONFIG_SYS_PCIE4_IO_BUS                0x00000000
> > +#define CONFIG_SYS_PCIE4_IO_SIZE       0x00010000      /* 64k */
> > +#endif
> >
> >  #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on
> startup */
> >  #endif /* CONFIG_PCI */
> > --
> 
> Regards,
> Bin

[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Z.q. Hou]

Hi Bin,

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月27日 10:51
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
> 
> Hi Zhiqiang,
> 
> On Tue, Aug 27, 2019 at 10:05 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 2019年8月26日 22:48
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>;
> Priyanka
> > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu
> <shengzhou.liu@nxp.com>
> > > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe
> > > driver
> > >
> > > Hi Zhiqiang,
> > >
> > > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > wrote:
> > > >
> > > > Enable the DM PCIe driver in T2080RDB defconfig.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > >  configs/T2080RDB_NAND_defconfig     | 4 ++++
> > > >  configs/T2080RDB_SDCARD_defconfig   | 4 ++++
> > > >  configs/T2080RDB_SPIFLASH_defconfig | 4 ++++
> > > >  configs/T2080RDB_defconfig          | 4 ++++
> > > >  4 files changed, 16 insertions(+)
> > > >
> > > > diff --git a/configs/T2080RDB_NAND_defconfig
> > > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b
> 100644
> > > > --- a/configs/T2080RDB_NAND_defconfig
> > > > +++ b/configs/T2080RDB_NAND_defconfig
> > > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
> CONFIG_PHY_AQUANTIA=y
> > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > +CONFIG_DM=y
> > > > +CONFIG_DM_PCI=y
> > > > +CONFIG_DM_PCI_COMPAT=y
> > >
> > > Why do we need this option? I vaguely remember I commented in as
> > > similar patch for some other board (maybe layerscape arm?)
> >
> > We discussed this during adding PCIe DM driver on T2080QDS, so it's
> > the same reason.
> 
> I dug into the mailing list archive, and I see:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d
> enx.de%2Fpipermail%2Fu-boot%2F2019-May%2F370756.html&amp;data=0
> 2%7C01%7Czhiqiang.hou%40nxp.com%7C7e2ca21c87dd4d497e4008d72a99
> 626b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702471058
> 1230533&amp;sdata=Ams8RKheHQcU9pgTAuTugXcLCrzbRFk5xOm6ubu84R
> Y%3D&amp;reserved=0
> 
> In that thread, you wrote:
> 
> "I will submit a patch to remove the DM_PCI_COMPAT when all driver has
> been converted."
> 
> So I believe you guys have not converted all PowerPC drivers to DM, hence
> it's still left there?

Yes, I will remove it when DM_ETH is added, otherwise there will be build errors.

Thanks,
Zhiqiang

> 
> Regards,
> Bin

[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Z.q. Hou]

Hi Bin,

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月27日 10:56
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> 
> Hi Zhiqiang,
> 
> On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 2019年8月26日 22:50
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>;
> Priyanka
> > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu
> <shengzhou.liu@nxp.com>
> > > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> > >
> > > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > wrote:
> > > >
> > > > P2020 integrated 3 PCIe controllers, which is compatible with the
> > > > PCI Express™ Base Specification, Revision 1.0a, and this patch is
> > > > to add DT node for each PCIe controller.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > >  arch/powerpc/dts/p2020-post.dtsi     | 30
> > > ++++++++++++++++++++++++++++++
> > > >  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
> > > >  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
> > > >  3 files changed, 64 insertions(+)
> > > >
> > > > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > > > b/arch/powerpc/dts/p2020-post.dtsi
> > > > index f20d1fa..f696f35 100644
> > > > --- a/arch/powerpc/dts/p2020-post.dtsi
> > > > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > > > @@ -25,3 +25,33 @@
> > > >                 last-interrupt-source = <255>;
> > > >         };
> > > >  };
> > > > +
> > > > +/* PCIe controller base address 0x8000 */
> > > > +&pci2 {
> > >
> > > pci0?
> >
> > Describe the controller index and starting address according to P2020 RM.
> 
> OK, so will this weird index number (2, 1, 0) break the index calculation log in
> the following patch?

No, the code handled this.

Thanks,
Zhiqiang

> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F1152811%2F&amp;data=02%7C01%7Czhiqian
> g.hou%40nxp.com%7Cb20f64bf19f445e50ce108d72a9a160a%7C686ea1d3b
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C637024713598549064&amp;sdat
> a=WG5PXoeY0zriaxdITqzOJ%2BnT65uzrQ%2FUtwi4JuykXnA%3D&amp;reser
> ved=0
> 
> Regards,
> Bin

[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Z.q. Hou]

Hi Bin,

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年8月27日 10:59
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> 
> Hi Zhiqiang,
> 
> On Tue, Aug 27, 2019 at 10:46 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 2019年8月26日 22:50
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>;
> Priyanka
> > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu
> <shengzhou.liu@nxp.com>
> > > Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> > >
> > > Hi Zhiqiang,
> > >
> > > On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > wrote:
> > > >
> > > > P1020 integrated 2 PCIe controllers, which is compatible with the
> > > > PCI Express™ Base Specification, Revision 1.0a, and this patch is
> > > > to add DT node for each PCIe controller.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > >  arch/powerpc/dts/p1020-post.dtsi     | 20
> ++++++++++++++++++++
> > > >  arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
> > > >  arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
> > > >  arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
> > > >  4 files changed, 56 insertions(+)
> > > >
> > > > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > > > b/arch/powerpc/dts/p1020-post.dtsi
> > > > index e1a4f50..1e5e678 100644
> > > > --- a/arch/powerpc/dts/p1020-post.dtsi
> > > > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > > > @@ -25,3 +25,23 @@
> > > >                 last-interrupt-source = <255>;
> > > >         };
> > > >  };
> > > > +
> > > > +/* PCIe controller base address 0x9000 */
> > > > +&pci1 {
> > > > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > > +       law_trgt_if = <1>;
> > > > +       #address-cells = <3>;
> > > > +       #size-cells = <2>;
> > > > +       device_type = "pci";
> > > > +       bus-range = <0x0 0xff>;
> > > > +};
> > > > +
> > > > +/* PCIe controller base address 0xa000 */
> > > > +&pci0 {
> > > > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > > +       law_trgt_if = <2>;
> > > > +       #address-cells = <3>;
> > > > +       #size-cells = <2>;
> > > > +       device_type = "pci";
> > > > +       bus-range = <0x0 0xff>;
> > > > +};
> > > > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > > > b/arch/powerpc/dts/p1020rdb-pc.dts
> > > > index fd68b8b..7ebaa61 100644
> > > > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > > > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > > > @@ -18,6 +18,18 @@
> > > >         soc: soc at ffe00000 {
> > > >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> > > >         };
> > > > +
> > > > +       pci1: pcie at ffe09000 {
> > >
> > > Why this is named as pci1?
> >
> > The P1020 reference manual said the first controller registers offset
> > begin at 0xa000 and the second begin at 0x9000.
> >
> > >
> > > > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /*
> registers
> > > */
> > >
> > > Shouldn't the <reg> property be put in the dtsi file?
> >
> > The registers starting addresses are different between 32bit and 36bit dts.
> >
> 
> I see. But looks they are inconsistent. Some of the platforms put the reg in
> the dtsi, and some do not. I believe it's because some platforms force to
> select CONFIG_PHYS_64BIT hence no need to have two version of <reg> in
> DT?

Yes, you're right.

Thanks,
Zhiqiang

> 
> Regards,
> Bin

[U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver

[Bin Meng]

Hi Zhiqiang,

On Tue, Aug 27, 2019 at 11:09 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年8月27日 10:51
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>; Priyanka
> > Jain <priyanka.jain@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>
> > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
> >
> > Hi Zhiqiang,
> >
> > On Tue, Aug 27, 2019 at 10:05 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > Hi Bin,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -----Original Message-----
> > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > Sent: 2019年8月26日 22:48
> > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Prabhakar Kushwaha
> > > > <prabhakar.kushwaha@nxp.com>; Wolfgang Denk <wd@denx.de>;
> > Priyanka
> > > > Jain <priyanka.jain@nxp.com>; Shengzhou Liu
> > <shengzhou.liu@nxp.com>
> > > > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe
> > > > driver
> > > >
> > > > Hi Zhiqiang,
> > > >
> > > > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > wrote:
> > > > >
> > > > > Enable the DM PCIe driver in T2080RDB defconfig.
> > > > >
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > ---
> > > > >  configs/T2080RDB_NAND_defconfig     | 4 ++++
> > > > >  configs/T2080RDB_SDCARD_defconfig   | 4 ++++
> > > > >  configs/T2080RDB_SPIFLASH_defconfig | 4 ++++
> > > > >  configs/T2080RDB_defconfig          | 4 ++++
> > > > >  4 files changed, 16 insertions(+)
> > > > >
> > > > > diff --git a/configs/T2080RDB_NAND_defconfig
> > > > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b
> > 100644
> > > > > --- a/configs/T2080RDB_NAND_defconfig
> > > > > +++ b/configs/T2080RDB_NAND_defconfig
> > > > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y
> > CONFIG_PHY_AQUANTIA=y
> > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > +CONFIG_DM=y
> > > > > +CONFIG_DM_PCI=y
> > > > > +CONFIG_DM_PCI_COMPAT=y
> > > >
> > > > Why do we need this option? I vaguely remember I commented in as
> > > > similar patch for some other board (maybe layerscape arm?)
> > >
> > > We discussed this during adding PCIe DM driver on T2080QDS, so it's
> > > the same reason.
> >
> > I dug into the mailing list archive, and I see:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d
> > enx.de%2Fpipermail%2Fu-boot%2F2019-May%2F370756.html&amp;data=0
> > 2%7C01%7Czhiqiang.hou%40nxp.com%7C7e2ca21c87dd4d497e4008d72a99
> > 626b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702471058
> > 1230533&amp;sdata=Ams8RKheHQcU9pgTAuTugXcLCrzbRFk5xOm6ubu84R
> > Y%3D&amp;reserved=0
> >
> > In that thread, you wrote:
> >
> > "I will submit a patch to remove the DM_PCI_COMPAT when all driver has
> > been converted."
> >
> > So I believe you guys have not converted all PowerPC drivers to DM, hence
> > it's still left there?
>
> Yes, I will remove it when DM_ETH is added, otherwise there will be build errors.
>

Great!, so,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin

[U-Boot] [PATCH 08/47] configs: T4240RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:34 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in T4240RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/T4240RDB_SDCARD_defconfig | 4 ++++
>  configs/T4240RDB_defconfig        | 4 ++++
>  2 files changed, 8 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 14/47] configs: T1024RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in T1024RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/T1024RDB_NAND_defconfig     | 4 ++++
>  configs/T1024RDB_SDCARD_defconfig   | 4 ++++
>  configs/T1024RDB_SPIFLASH_defconfig | 4 ++++
>  configs/T1024RDB_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 19/47] configs: T1042D4RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in T1042D4RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/T1042D4RDB_NAND_defconfig     | 4 ++++
>  configs/T1042D4RDB_SDCARD_defconfig   | 4 ++++
>  configs/T1042D4RDB_SPIFLASH_defconfig | 4 ++++
>  configs/T1042D4RDB_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P1020 integrated 2 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p1020-post.dtsi     | 20 ++++++++++++++++++++
>  arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
>  arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
>  arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
>  4 files changed, 56 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 24/47] configs: P1020RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:41 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in P1020RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/P1020RDB-PC_36BIT_NAND_defconfig     | 4 ++++
>  configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 4 ++++
>  configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++
>  configs/P1020RDB-PC_36BIT_defconfig          | 4 ++++
>  configs/P1020RDB-PC_NAND_defconfig           | 4 ++++
>  configs/P1020RDB-PC_SDCARD_defconfig         | 4 ++++
>  configs/P1020RDB-PC_SPIFLASH_defconfig       | 4 ++++
>  configs/P1020RDB-PC_defconfig                | 4 ++++
>  configs/P1020RDB-PD_NAND_defconfig           | 4 ++++
>  configs/P1020RDB-PD_SDCARD_defconfig         | 4 ++++
>  configs/P1020RDB-PD_SPIFLASH_defconfig       | 4 ++++
>  configs/P1020RDB-PD_defconfig                | 4 ++++
>  12 files changed, 48 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Bin Meng]

On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> P2020 integrated 3 PCIe controllers, which is compatible with
> the PCI Expressâ„¢ Base Specification, Revision 1.0a, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  arch/powerpc/dts/p2020-post.dtsi     | 30 ++++++++++++++++++++++++++++++
>  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
>  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
>  3 files changed, 64 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 26/47] configs: P2020RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:40 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in P2020RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/P2020RDB-PC_36BIT_NAND_defconfig     | 4 ++++
>  configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 4 ++++
>  configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++
>  configs/P2020RDB-PC_36BIT_defconfig          | 4 ++++
>  configs/P2020RDB-PC_NAND_defconfig           | 4 ++++
>  configs/P2020RDB-PC_SDCARD_defconfig         | 4 ++++
>  configs/P2020RDB-PC_SPIFLASH_defconfig       | 4 ++++
>  configs/P2020RDB-PC_defconfig                | 4 ++++
>  8 files changed, 32 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:44 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/P2041RDB.h | 55 +++++++++++++---------------------------------
>  1 file changed, 15 insertions(+), 40 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 31/47] configs: P2041RDB: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:43 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in P2041RDB defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/P2041RDB_NAND_defconfig     | 4 ++++
>  configs/P2041RDB_SDCARD_defconfig   | 4 ++++
>  configs/P2041RDB_SPIFLASH_defconfig | 4 ++++
>  configs/P2041RDB_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

[Bin Meng]

On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  include/configs/corenet_ds.h | 63 +++++++++++++-------------------------------
>  1 file changed, 19 insertions(+), 44 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 35/47] configs: P3041DS: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:32 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in P3041DS defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/P3041DS_NAND_defconfig     | 4 ++++
>  configs/P3041DS_SDCARD_defconfig   | 4 ++++
>  configs/P3041DS_SPIFLASH_defconfig | 4 ++++
>  configs/P3041DS_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 38/47] configs: P4080DS: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:31 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in P4080DS defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/P4080DS_SDCARD_defconfig   | 4 ++++
>  configs/P4080DS_SPIFLASH_defconfig | 4 ++++
>  configs/P4080DS_defconfig          | 4 ++++
>  3 files changed, 12 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 41/47] configs: P5040DS: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:31 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in P5040DS defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/P5040DS_NAND_defconfig     | 4 ++++
>  configs/P5040DS_SDCARD_defconfig   | 4 ++++
>  configs/P5040DS_SPIFLASH_defconfig | 4 ++++
>  configs/P5040DS_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 47/47] configs: MPC8548CDS: Enable PCIe driver

[Bin Meng]

On Tue, Jul 23, 2019 at 9:26 PM Hou Zhiqiang <Zhiqiang.Hou@nxp.com> wrote:
>
> Enable the DM PCIe driver in MPC8548CDS defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  configs/MPC8548CDS_36BIT_defconfig  | 4 ++++
>  configs/MPC8548CDS_defconfig        | 4 ++++
>  configs/MPC8548CDS_legacy_defconfig | 4 ++++
>  3 files changed, 12 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>