From: Mario Kleiner <mario.kleiner.de@gmail.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: mario.kleiner.de@gmail.de,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915/dp: Add current maximum eDP link rate to sink_rate array.
Date: Thu, 9 Jan 2020 17:30:05 +0100 [thread overview]
Message-ID: <CAEsyxyj6xbHrkKk5=bG5APrD5VW_PP-Cs+nT0vqCjW_LBSG29A@mail.gmail.com> (raw)
In-Reply-To: <20200109153815.GQ1208@intel.com>
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On Thu, Jan 9, 2020 at 4:38 PM Ville Syrjälä <ville.syrjala@linux.intel.com>
wrote:
> On Thu, Jan 09, 2020 at 05:26:57PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 09, 2020 at 04:07:52PM +0100, Mario Kleiner wrote:
> > > The panel reports 10 bpc color depth in its EDID, and the UEFI
> > > firmware chooses link settings at boot which support enough
> > > bandwidth for 10 bpc (324000 kbit/sec to be precise), but the
> > > DP_MAX_LINK_RATE dpcd register only reports 2.7 Gbps as possible,
>
> Does it actually or do we just ignore the fact that it reports 3.24Gbps?
>
> If it really reports 3.24 then we should be able to just add that to
> dp_rates[] in intel_dp_set_sink_rates() and be done with it.
>
> Although we'd likely want to skip 3.24 unless it really is reported
> as the max so as to not use that non-standard rate on other displays.
> So would require a bit fancier logic for that.
>
>
Was also my initial thought, but the DP_MAX_LINK_RATE reg reports 2.7 Gbps
as maximum.
-mario
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WARNING: multiple messages have this Message-ID (diff)
From: Mario Kleiner <mario.kleiner.de@gmail.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: mario.kleiner.de@gmail.de,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Add current maximum eDP link rate to sink_rate array.
Date: Thu, 9 Jan 2020 17:30:05 +0100 [thread overview]
Message-ID: <CAEsyxyj6xbHrkKk5=bG5APrD5VW_PP-Cs+nT0vqCjW_LBSG29A@mail.gmail.com> (raw)
In-Reply-To: <20200109153815.GQ1208@intel.com>
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On Thu, Jan 9, 2020 at 4:38 PM Ville Syrjälä <ville.syrjala@linux.intel.com>
wrote:
> On Thu, Jan 09, 2020 at 05:26:57PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 09, 2020 at 04:07:52PM +0100, Mario Kleiner wrote:
> > > The panel reports 10 bpc color depth in its EDID, and the UEFI
> > > firmware chooses link settings at boot which support enough
> > > bandwidth for 10 bpc (324000 kbit/sec to be precise), but the
> > > DP_MAX_LINK_RATE dpcd register only reports 2.7 Gbps as possible,
>
> Does it actually or do we just ignore the fact that it reports 3.24Gbps?
>
> If it really reports 3.24 then we should be able to just add that to
> dp_rates[] in intel_dp_set_sink_rates() and be done with it.
>
> Although we'd likely want to skip 3.24 unless it really is reported
> as the max so as to not use that non-standard rate on other displays.
> So would require a bit fancier logic for that.
>
>
Was also my initial thought, but the DP_MAX_LINK_RATE reg reports 2.7 Gbps
as maximum.
-mario
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-01-09 16:30 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-09 15:07 [PATCH] drm/i915/dp: Add current maximum eDP link rate to sink_rate array Mario Kleiner
2020-01-09 15:07 ` [Intel-gfx] " Mario Kleiner
2020-01-09 15:26 ` Ville Syrjälä
2020-01-09 15:26 ` [Intel-gfx] " Ville Syrjälä
2020-01-09 15:38 ` Ville Syrjälä
2020-01-09 15:38 ` [Intel-gfx] " Ville Syrjälä
2020-01-09 16:30 ` Mario Kleiner [this message]
2020-01-09 16:30 ` Mario Kleiner
2020-01-09 16:47 ` Ville Syrjälä
2020-01-09 16:47 ` [Intel-gfx] " Ville Syrjälä
2020-01-09 17:57 ` Mario Kleiner
2020-01-09 17:57 ` [Intel-gfx] " Mario Kleiner
2020-01-09 18:24 ` Ville Syrjälä
2020-01-09 18:24 ` [Intel-gfx] " Ville Syrjälä
2020-01-09 20:19 ` Mario Kleiner
2020-01-09 20:19 ` [Intel-gfx] " Mario Kleiner
2020-01-10 13:32 ` Ville Syrjälä
2020-01-10 13:32 ` [Intel-gfx] " Ville Syrjälä
2020-01-10 15:50 ` Mario Kleiner
2020-01-10 15:50 ` [Intel-gfx] " Mario Kleiner
2020-01-09 16:31 ` Ville Syrjälä
2020-01-09 16:31 ` [Intel-gfx] " Ville Syrjälä
2020-01-09 16:27 ` Mario Kleiner
2020-01-09 16:27 ` [Intel-gfx] " Mario Kleiner
2020-01-09 15:39 ` Alex Deucher
2020-01-09 15:39 ` [Intel-gfx] " Alex Deucher
2020-01-09 16:46 ` Mario Kleiner
2020-01-09 16:46 ` [Intel-gfx] " Mario Kleiner
2020-01-09 19:49 ` Alex Deucher
2020-01-09 19:49 ` [Intel-gfx] " Alex Deucher
2020-01-09 21:04 ` Mario Kleiner
2020-01-09 21:04 ` [Intel-gfx] " Mario Kleiner
2020-01-09 21:26 ` Harry Wentland
2020-01-09 21:26 ` [Intel-gfx] " Harry Wentland
2020-01-10 16:02 ` Mario Kleiner
2020-01-10 16:02 ` [Intel-gfx] " Mario Kleiner
2020-01-10 18:09 ` Ville Syrjälä
2020-01-10 18:09 ` Ville Syrjälä
2020-01-15 12:34 ` Jani Nikula
2020-01-15 12:34 ` Jani Nikula
2020-01-15 14:17 ` Ville Syrjälä
2020-01-15 14:17 ` Ville Syrjälä
2020-01-09 23:52 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: Add current maximum eDP link rate to sink_rate array. (rev2) Patchwork
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