Re: [PATCH 02/11] target/arm: Add ARM Cortex-R52 cpu

[Peter Maydell <peter.maydell@linaro.org>]

On Thu, 14 Jul 2022 at 15:54, Tobias Roehmel <quic_trohmel@quicinc.com> wrote:
>
> From: Tobias Röhmel <quic_trohmel@quicinc.com>
>
> All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3

This should be the last patch in the patchset, so that we only
add the new CPU when all the code changes necessary to make it work
are present.

> Signed-off-by: Tobias Röhmel <quic_trohmel@quicinc.com>
> ---
>  target/arm/cpu_tcg.c | 54 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
>
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index b751a19c8a..49fb03c09a 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -843,6 +843,59 @@ static void cortex_r5_initfn(Object *obj)
>      define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
>  }
>
> +static const ARMCPRegInfo cortexr52_cp_reginfo[] = {
> +    /* Dummy the TCM region regs for the moment */
> +    { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
> +      .access = PL1_RW, .type = ARM_CP_CONST },
> +    { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
> +      .access = PL1_RW, .type = ARM_CP_CONST },
> +    { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
> +      .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
> +};

This is just a copy of the Cortex-R5 impdef register set.
The R52 doesn't have the DCACHE_INVAL. Although it does have
registers in the ATCM and BTCM encodings, it also has a
third CTCM, because it has three TCM regions.

You should implement the IMPDEF registers that the CPU
actually has, assuming that guest software cares about them.

> +static void cortex_r52_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    set_feature(&cpu->env, ARM_FEATURE_V8);
> +    set_feature(&cpu->env, ARM_FEATURE_V8_R);
> +    set_feature(&cpu->env, ARM_FEATURE_EL2);
> +    set_feature(&cpu->env, ARM_FEATURE_PMSA);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> +    cpu->midr = 0x411fd133; /* r1p3 */
> +    cpu->revidr = 0x00000000;
> +    cpu->reset_fpsid = 0x41034023;
> +    cpu->isar.mvfr0 = 0x10110222;
> +    cpu->isar.mvfr1 = 0x12111111;
> +    cpu->isar.mvfr2 = 0x00000043;
> +    cpu->ctr = 0x8144c004;
> +    cpu->reset_sctlr = 0x30c50838;
> +    cpu->isar.id_pfr0 = 0x00000131;
> +    cpu->isar.id_pfr1 = 0x10111001;
> +    cpu->isar.id_dfr0 = 0x03010006;
> +    cpu->id_afr0 = 0x00000000;
> +    cpu->isar.id_mmfr0 = 0x00211040;
> +    cpu->isar.id_mmfr1 = 0x40000000;
> +    cpu->isar.id_mmfr2 = 0x01200000;
> +    cpu->isar.id_mmfr3 = 0xf0102211;
> +    cpu->isar.id_mmfr4 = 0x00000010;
> +    cpu->isar.id_isar0 = 0x02101110;
> +    cpu->isar.id_isar1 = 0x13112111;
> +    cpu->isar.id_isar2 = 0x21232142;
> +    cpu->isar.id_isar3 = 0x01112131;
> +    cpu->isar.id_isar4 = 0x00010142;
> +    cpu->isar.id_isar5 = 0x00010001;
> +    cpu->isar.dbgdidr = 0x77168000;
> +    cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
> +    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> +    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
> +
> +    cpu->pmsav7_dregion = 16;
> +
> +    define_arm_cp_regs(cpu, cortexr52_cp_reginfo);
> +}
> +
>  static void cortex_r5f_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -1148,6 +1201,7 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
>                               .class_init = arm_v7m_class_init },
>      { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
> +    { .name = "cortex-r52",   .initfn = cortex_r52_initfn },
>      { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },

List it below cortex-r5f, so that the two different flavours of R5
stay together.

>      { .name = "ti925t",      .initfn = ti925t_initfn },
>      { .name = "sa1100",      .initfn = sa1100_initfn },
> --
> 2.25.1
>

thanks
-- PMM