From: Peter Maydell <peter.maydell@linaro.org>
To: Nathan Chancellor <natechancellor@gmail.com>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
qemu-ppc <qemu-ppc@nongnu.org>,
"Guenter Roeck" <linux@roeck-us.net>,
"Greg Kurz" <groug@kaod.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 4/5] hw/ppc/ppc4xx_pci: Replace pointless warning by assert()
Date: Mon, 11 Jan 2021 17:41:54 +0000 [thread overview]
Message-ID: <CAFEAcA_uz3XryHh3t4DvVR38jHGCm47YFL6KMJJX4-boMih2og@mail.gmail.com> (raw)
In-Reply-To: <20210111011117.GA215408@ubuntu-m3-large-x86>
On Mon, 11 Jan 2021 at 01:11, Nathan Chancellor
<natechancellor@gmail.com> wrote:
>
> On Tue, Sep 01, 2020 at 12:40:42PM +0200, Philippe Mathieu-Daudé wrote:
> > We call pci_register_root_bus() to register 4 IRQs with the
> > ppc4xx_pci_set_irq() handler. As it can only be called with
> > values in the [0-4[ range, replace the pointless warning by
> > an assert().
> >
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Hopefully reporting this here is okay, I find Launchpad hard to use but
> I can file it there if need be.
>
> The assertion added by this patch triggers while trying to boot a
> ppc44x_defconfig Linux kernel:
This is the same issue reported here by Guenter:
https://lore.kernel.org/qemu-devel/3f0f8fc6-6148-a76e-1088-b7882b0bbcaf@roeck-us.net/
It's still there in master (you can see it if you apply my fix
https://patchew.org/QEMU/20210111171623.18871-1-peter.maydell@linaro.org/
to get past the earlier kernel panic).
The QEMU code as it stands for the Bamboo PCI interrupts is clearly
wrong. The problem is that I don't know what the hardware's
actual behaviour is, so it's hard to fix the model...
A comment in hw/ppc/ppc4xx_pci.c claims
"On Bamboo, all pins from each slot are tied to a single board IRQ."
Code in hw/ppc/ppc440_bamboo.c wires four irq lines from the
PCI controller up to UIC lines 25, 26, 27, 28.
Does anybody have documentation for this board ? What is Linux
expecting the PCI IRQ wiring to be (not necessarily an indication
that that's what the h/w does, but a useful clue :-)) ?
thanks
-- PMM
next prev parent reply other threads:[~2021-01-11 17:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 10:40 [PATCH 0/5] hw: Replace some impossible checks by assertions Philippe Mathieu-Daudé
2020-09-01 10:40 ` [PATCH 1/5] hw/gpio/max7310: Remove impossible check Philippe Mathieu-Daudé
2020-09-01 10:42 ` Peter Maydell
2020-09-01 10:40 ` [PATCH 2/5] hw/mips/fuloong2e: Convert pointless error message to an assert() Philippe Mathieu-Daudé
2020-09-01 11:36 ` chen huacai
2020-09-01 17:49 ` Richard Henderson
2020-09-09 13:23 ` Laurent Vivier
2020-09-01 10:40 ` [PATCH 3/5] hw/ppc/ppc4xx_pci: Use ARRAY_SIZE() instead of magic value Philippe Mathieu-Daudé
2020-09-01 17:50 ` Richard Henderson
2020-09-02 1:16 ` David Gibson
2020-09-02 6:53 ` Cédric Le Goater
2020-09-02 8:12 ` Philippe Mathieu-Daudé
2020-09-01 10:40 ` [PATCH 4/5] hw/ppc/ppc4xx_pci: Replace pointless warning by assert() Philippe Mathieu-Daudé
2020-09-01 17:50 ` Richard Henderson
2020-09-02 1:17 ` David Gibson
2021-01-11 1:11 ` Nathan Chancellor
2021-01-11 10:04 ` Philippe Mathieu-Daudé
2021-01-11 16:46 ` Nathan Chancellor
2021-01-11 17:41 ` Peter Maydell [this message]
2020-09-01 10:40 ` [PATCH 5/5] hw/isa/isa-bus: Replace hw_error() " Philippe Mathieu-Daudé
2020-09-01 17:50 ` Richard Henderson
2020-09-09 13:25 ` Laurent Vivier
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