ARM cortex A9 feature

ARM cortex A9 feature

[naveen yadav]

Hi All,

I am reading ARM cortex a9 manual and got few question in mind.

1. Where I need strong order type memory ? any sample example is very helpfull.

2. L2 cache, Cortex a9 support exclusive L2 cache feature, where we need it ?

ARM cortex A9 feature

[naveen yadav]

Hi All,

I am reading ARM cortex a9 manual and got few question in mind.

1. Where I need strong order type memory ? any sample example is very helpfull.

2. L2 cache, Cortex a9 support exclusive L2 cache feature, where we need it ?

Re: ARM cortex A9 feature

[Dave Hylands]

Hi Naveen,

On Wed, Jul 13, 2011 at 11:26 PM, naveen yadav <yad.naveen@gmail.com> wrote:
> Hi All,
>
> I am reading ARM cortex a9 manual and got few question in mind.
>
> 1. Where I need strong order type memory ? any sample example is very helpfull.

Often when dealing with hardware, you need to ensure that when your code does:

reg1 = val1;
reg2 = val2;

that these writes actually occur in the order that the code issues
them. Using volatile pointers will get the compiler to not reorder the
instructions, but you still need the writes to hit the hardware in the
same order that they were issued. Using strongly ordered memory is one
way to achieve that.

> 2. L2 cache, Cortex a9 support exclusive L2 cache feature, where we need it ?

L2 cache can improve your performance.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

ARM cortex A9 feature

[Dave Hylands]

Hi Naveen,

On Wed, Jul 13, 2011 at 11:26 PM, naveen yadav <yad.naveen@gmail.com> wrote:
> Hi All,
>
> I am reading ARM cortex a9 manual and got few question in mind.
>
> 1. Where I need strong order type memory ? any sample example is very helpfull.

Often when dealing with hardware, you need to ensure that when your code does:

reg1 = val1;
reg2 = val2;

that these writes actually occur in the order that the code issues
them. Using volatile pointers will get the compiler to not reorder the
instructions, but you still need the writes to hit the hardware in the
same order that they were issued. Using strongly ordered memory is one
way to achieve that.

> 2. L2 cache, Cortex a9 support exclusive L2 cache feature, where we need it ?

L2 cache can improve your performance.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

Re: ARM cortex A9 feature

[Russell King - ARM Linux]

On Thu, Jul 14, 2011 at 09:56:34AM -0700, Dave Hylands wrote:
> Hi Naveen,
> 
> On Wed, Jul 13, 2011 at 11:26 PM, naveen yadav <yad.naveen@gmail.com> wrote:
> > Hi All,
> >
> > I am reading ARM cortex a9 manual and got few question in mind.
> >
> > 1. Where I need strong order type memory ? any sample example is very helpfull.
> 
> Often when dealing with hardware, you need to ensure that when your code does:
> 
> reg1 = val1;
> reg2 = val2;
> 
> that these writes actually occur in the order that the code issues
> them. Using volatile pointers will get the compiler to not reorder the
> instructions, but you still need the writes to hit the hardware in the
> same order that they were issued. Using strongly ordered memory is one
> way to achieve that.

Note that device memory also gives that an ordering guarantee too.

ARM cortex A9 feature

[Russell King - ARM Linux]

On Thu, Jul 14, 2011 at 09:56:34AM -0700, Dave Hylands wrote:
> Hi Naveen,
> 
> On Wed, Jul 13, 2011 at 11:26 PM, naveen yadav <yad.naveen@gmail.com> wrote:
> > Hi All,
> >
> > I am reading ARM cortex a9 manual and got few question in mind.
> >
> > 1. Where I need strong order type memory ? any sample example is very helpfull.
> 
> Often when dealing with hardware, you need to ensure that when your code does:
> 
> reg1 = val1;
> reg2 = val2;
> 
> that these writes actually occur in the order that the code issues
> them. Using volatile pointers will get the compiler to not reorder the
> instructions, but you still need the writes to hit the hardware in the
> same order that they were issued. Using strongly ordered memory is one
> way to achieve that.

Note that device memory also gives that an ordering guarantee too.

Re: ARM cortex A9 feature

[naveen yadav]

Hi dave,

Thanks for answering, but I think question 2, answer  is still not clear to me .

my question is why exclusive L2.

8.1.4 Exclusive L2 cache
The Cortex-A9 processor can be connected to an L2 cache that supports
an exclusive cache
mode. This mode must be activated both in the Cortex-A9 processor and
in the L2 cache
controller.
In this mode, the data cache of the Cortex-A9 processor and the L2
cache are exclusive. At any
time, a given address is cached in either L1 data caches or in the L2
cache, but not in both. This
has the effect of greatly increasing the usable space and efficiency
of an L2 cache connected to
the Cortex-A9 processor. When exclusive cache configuration is selected:
• Data cache line replacement policy is modified so that the victim
line always gets evicted
to L2 memory, even if it is clean.
• If a line is dirty in the L2 cache controller, a read request to this address


what is usecase for this . This is my question .

Thanks


On Thu, Jul 14, 2011 at 10:26 PM, Dave Hylands <dhylands@gmail.com> wrote:
> Hi Naveen,
>
> On Wed, Jul 13, 2011 at 11:26 PM, naveen yadav <yad.naveen@gmail.com> wrote:
>> Hi All,
>>
>> I am reading ARM cortex a9 manual and got few question in mind.
>>
>> 1. Where I need strong order type memory ? any sample example is very helpfull.
>
> Often when dealing with hardware, you need to ensure that when your code does:
>
> reg1 = val1;
> reg2 = val2;
>
> that these writes actually occur in the order that the code issues
> them. Using volatile pointers will get the compiler to not reorder the
> instructions, but you still need the writes to hit the hardware in the
> same order that they were issued. Using strongly ordered memory is one
> way to achieve that.
>
>> 2. L2 cache, Cortex a9 support exclusive L2 cache feature, where we need it ?
>
> L2 cache can improve your performance.
>
> --
> Dave Hylands
> Shuswap, BC, Canada
> http://www.davehylands.com
>

ARM cortex A9 feature

[naveen yadav]

Hi dave,

Thanks for answering, but I think question 2, answer  is still not clear to me .

my question is why exclusive L2.

8.1.4 Exclusive L2 cache
The Cortex-A9 processor can be connected to an L2 cache that supports
an exclusive cache
mode. This mode must be activated both in the Cortex-A9 processor and
in the L2 cache
controller.
In this mode, the data cache of the Cortex-A9 processor and the L2
cache are exclusive. At any
time, a given address is cached in either L1 data caches or in the L2
cache, but not in both. This
has the effect of greatly increasing the usable space and efficiency
of an L2 cache connected to
the Cortex-A9 processor. When exclusive cache configuration is selected:
? Data cache line replacement policy is modified so that the victim
line always gets evicted
to L2 memory, even if it is clean.
? If a line is dirty in the L2 cache controller, a read request to this address


what is usecase for this . This is my question .

Thanks


On Thu, Jul 14, 2011 at 10:26 PM, Dave Hylands <dhylands@gmail.com> wrote:
> Hi Naveen,
>
> On Wed, Jul 13, 2011 at 11:26 PM, naveen yadav <yad.naveen@gmail.com> wrote:
>> Hi All,
>>
>> I am reading ARM cortex a9 manual and got few question in mind.
>>
>> 1. Where I need strong order type memory ? any sample example is very helpfull.
>
> Often when dealing with hardware, you need to ensure that when your code does:
>
> reg1 = val1;
> reg2 = val2;
>
> that these writes actually occur in the order that the code issues
> them. Using volatile pointers will get the compiler to not reorder the
> instructions, but you still need the writes to hit the hardware in the
> same order that they were issued. Using strongly ordered memory is one
> way to achieve that.
>
>> 2. L2 cache, Cortex a9 support exclusive L2 cache feature, where we need it ?
>
> L2 cache can improve your performance.
>
> --
> Dave Hylands
> Shuswap, BC, Canada
> http://www.davehylands.com
>

Re: ARM cortex A9 feature

[Dave Hylands]

Hi naveen,

On Thu, Jul 14, 2011 at 10:15 PM, naveen yadav <yad.naveen@gmail.com> wrote:
> Hi dave,
>
> Thanks for answering, but I think question 2, answer  is still not clear to me .
>
> my question is why exclusive L2.
>
> 8.1.4 Exclusive L2 cache
> The Cortex-A9 processor can be connected to an L2 cache that supports
> an exclusive cache
> mode. This mode must be activated both in the Cortex-A9 processor and
> in the L2 cache
> controller.
> In this mode, the data cache of the Cortex-A9 processor and the L2
> cache are exclusive. At any
> time, a given address is cached in either L1 data caches or in the L2
> cache, but not in both. This
> has the effect of greatly increasing the usable space and efficiency
> of an L2 cache connected to
> the Cortex-A9 processor. When exclusive cache configuration is selected:
> • Data cache line replacement policy is modified so that the victim
> line always gets evicted
> to L2 memory, even if it is clean.
> • If a line is dirty in the L2 cache controller, a read request to this address
>
>
> what is usecase for this . This is my question .

Since I've never used one, I'm not sure. Maybe somebody else knows.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

ARM cortex A9 feature

[Dave Hylands]

Hi naveen,

On Thu, Jul 14, 2011 at 10:15 PM, naveen yadav <yad.naveen@gmail.com> wrote:
> Hi dave,
>
> Thanks for answering, but I think question 2, answer ?is still not clear to me .
>
> my question is why exclusive L2.
>
> 8.1.4 Exclusive L2 cache
> The Cortex-A9 processor can be connected to an L2 cache that supports
> an exclusive cache
> mode. This mode must be activated both in the Cortex-A9 processor and
> in the L2 cache
> controller.
> In this mode, the data cache of the Cortex-A9 processor and the L2
> cache are exclusive. At any
> time, a given address is cached in either L1 data caches or in the L2
> cache, but not in both. This
> has the effect of greatly increasing the usable space and efficiency
> of an L2 cache connected to
> the Cortex-A9 processor. When exclusive cache configuration is selected:
> ? Data cache line replacement policy is modified so that the victim
> line always gets evicted
> to L2 memory, even if it is clean.
> ? If a line is dirty in the L2 cache controller, a read request to this address
>
>
> what is usecase for this . This is my question .

Since I've never used one, I'm not sure. Maybe somebody else knows.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

RE: ARM cortex A9 feature

[Woodruff, Richard]

> From: linux-arm-kernel-bounces@lists.infradead.org [mailto:linux-arm-
> kernel-bounces@lists.infradead.org] On Behalf Of Dave Hylands
> Sent: Friday, July 15, 2011 1:03 AM
> To: naveen yadav

> > what is usecase for this . This is my question .
> 
> Since I've never used one, I'm not sure. Maybe somebody else knows.

The exclusive L2 feature is not the default option.

If you choose a small L2 size when configuring your CortexA hardware it might be useful.

A friend who did early x86/amd design indicated this feature was used when L1 & L2 caches were near the same size back in 90's. Going exclusive can have the effect of near doubling cache size.  As L2 got much bigger most folks stopped using it...presumably benchmarks fell off and it wasn't worth validation effort of carrying an option not commonly used.

The CortexA8 r1px rev's was exclusive only (like in omap3430).  Later A8 rev's (like omap3630) and A9 (omap4430) added and defaulted to non-exclusive.  Early L2's were 64K,128K,256K so adding 32K to a 64K probably did make sense.  Today in A9's (omap4460) and A15's (omap5430) with 1M and 2M L2 sizes +32K is not so impacting.

The A8's L2 was pretty quick (like 8 cycles) to registers on an A9 with external L2 you only can configure like 22 cycles.  Mixing with speed differences might create some other issues.

If you care about correlating benchmark results back to hardware actuals for things like lmbench, you find the exclusive configuration muddies several test results.

Regards,
Richard W.

ARM cortex A9 feature

[Woodruff, Richard]

> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Dave Hylands
> Sent: Friday, July 15, 2011 1:03 AM
> To: naveen yadav

> > what is usecase for this . This is my question .
> 
> Since I've never used one, I'm not sure. Maybe somebody else knows.

The exclusive L2 feature is not the default option.

If you choose a small L2 size when configuring your CortexA hardware it might be useful.

A friend who did early x86/amd design indicated this feature was used when L1 & L2 caches were near the same size back in 90's. Going exclusive can have the effect of near doubling cache size.  As L2 got much bigger most folks stopped using it...presumably benchmarks fell off and it wasn't worth validation effort of carrying an option not commonly used.

The CortexA8 r1px rev's was exclusive only (like in omap3430).  Later A8 rev's (like omap3630) and A9 (omap4430) added and defaulted to non-exclusive.  Early L2's were 64K,128K,256K so adding 32K to a 64K probably did make sense.  Today in A9's (omap4460) and A15's (omap5430) with 1M and 2M L2 sizes +32K is not so impacting.

The A8's L2 was pretty quick (like 8 cycles) to registers on an A9 with external L2 you only can configure like 22 cycles.  Mixing with speed differences might create some other issues.

If you care about correlating benchmark results back to hardware actuals for things like lmbench, you find the exclusive configuration muddies several test results.

Regards,
Richard W.