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From: Guo Ren <guoren@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Wei Fu <wefu@redhat.com>, liush <liush@allwinnertech.com>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Drew Fustini <drew@beagleboard.org>,
	Christoph Hellwig <hch@lst.de>, Arnd Bergmann <arnd@arndb.de>,
	Chen-Yu Tsai <wens@csie.org>, Maxime Ripard <maxime@cerno.tech>,
	Greg Favor <gfavor@ventanamicro.com>,
	Andrea Mondelli <andrea.mondelli@huawei.com>,
	Jonathan Behrens <behrensj@mit.edu>,
	"Xinhaoqu (Freddie)" <xinhaoqu@huawei.com>,
	Nick Kossifidis <mick@ics.forth.gr>,
	Allen Baum <allen.baum@esperantotech.com>,
	Josh Scheid <jscheid@ventanamicro.com>,
	Richard Trauben <rtrauben@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Christoph Muellner <cmuellner@linux.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: Re: [PATCH 02/12] riscv: allow different stages with alternatives
Date: Mon, 16 May 2022 14:51:24 +0800	[thread overview]
Message-ID: <CAJF2gTQKsJ00MAyXGnBXR-tK1pAnHeuEr6Se79OYN4_kvPjjFQ@mail.gmail.com> (raw)
In-Reply-To: <20220511192921.2223629-3-heiko@sntech.de>

Reviewed-by: Guo Ren <guoren@kernel.org>

On Thu, May 12, 2022 at 3:29 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Future features may need to be applied at a different
> time during boot, so allow defining stages for alternatives
> and handling them differently depending on the stage.
>
> Also make the alternatives-location more flexible so that
> future stages may provide their own location.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>  arch/riscv/errata/sifive/errata.c    |  3 ++-
>  arch/riscv/include/asm/alternative.h |  5 ++++-
>  arch/riscv/kernel/alternative.c      | 26 +++++++++++++++++---------
>  3 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
> index f5e5ae70e829..4fe03ac41fd7 100644
> --- a/arch/riscv/errata/sifive/errata.c
> +++ b/arch/riscv/errata/sifive/errata.c
> @@ -80,7 +80,8 @@ static void __init warn_miss_errata(u32 miss_errata)
>  }
>
>  void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> -                                    unsigned long archid, unsigned long impid)
> +                                    unsigned long archid, unsigned long impid,
> +                                    unsigned int stage)
>  {
>         struct alt_entry *alt;
>         u32 cpu_req_errata = sifive_errata_probe(archid, impid);
> diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
> index 7b42bcef0ecf..0ff550667e94 100644
> --- a/arch/riscv/include/asm/alternative.h
> +++ b/arch/riscv/include/asm/alternative.h
> @@ -19,6 +19,8 @@
>  #include <linux/stddef.h>
>  #include <asm/hwcap.h>
>
> +#define RISCV_ALTERNATIVES_BOOT                0 /* alternatives applied during regular boot */
> +
>  void __init apply_boot_alternatives(void);
>
>  struct alt_entry {
> @@ -35,7 +37,8 @@ struct errata_checkfunc_id {
>  };
>
>  void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> -                             unsigned long archid, unsigned long impid);
> +                             unsigned long archid, unsigned long impid,
> +                             unsigned int stage);
>
>  #else /* CONFIG_RISCV_ALTERNATIVE */
>
> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> index e8b4a0fe488c..02db62f55bac 100644
> --- a/arch/riscv/kernel/alternative.c
> +++ b/arch/riscv/kernel/alternative.c
> @@ -22,8 +22,8 @@ static struct cpu_manufacturer_info_t {
>  } cpu_mfr_info;
>
>  static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
> -                                unsigned long archid,
> -                                unsigned long impid) __initdata;
> +                                unsigned long archid, unsigned long impid,
> +                                unsigned int stage) __initdata;
>
>  static inline void __init riscv_fill_cpu_mfr_info(void)
>  {
> @@ -58,6 +58,18 @@ static void __init init_alternative(void)
>   * a feature detect on the boot CPU). No need to worry about other CPUs
>   * here.
>   */
> +static void __init _apply_alternatives(struct alt_entry *begin,
> +                                      struct alt_entry *end,
> +                                      unsigned int stage)
> +{
> +       if (!vendor_patch_func)
> +               return;
> +
> +       vendor_patch_func(begin, end,
> +                         cpu_mfr_info.arch_id, cpu_mfr_info.imp_id,
> +                         stage);
> +}
> +
>  void __init apply_boot_alternatives(void)
>  {
>         /* If called on non-boot cpu things could go wrong */
> @@ -65,11 +77,7 @@ void __init apply_boot_alternatives(void)
>
>         init_alternative();
>
> -       if (!vendor_patch_func)
> -               return;
> -
> -       vendor_patch_func((struct alt_entry *)__alt_start,
> -                         (struct alt_entry *)__alt_end,
> -                         cpu_mfr_info.arch_id, cpu_mfr_info.imp_id);
> +       _apply_alternatives((struct alt_entry *)__alt_start,
> +                           (struct alt_entry *)__alt_end,
> +                           RISCV_ALTERNATIVES_BOOT);
>  }
> -
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	 Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Wei Fu <wefu@redhat.com>,  liush <liush@allwinnertech.com>,
	Atish Patra <atishp@atishpatra.org>,
	 Anup Patel <anup@brainfault.org>,
	Drew Fustini <drew@beagleboard.org>,
	 Christoph Hellwig <hch@lst.de>, Arnd Bergmann <arnd@arndb.de>,
	Chen-Yu Tsai <wens@csie.org>,  Maxime Ripard <maxime@cerno.tech>,
	Greg Favor <gfavor@ventanamicro.com>,
	 Andrea Mondelli <andrea.mondelli@huawei.com>,
	Jonathan Behrens <behrensj@mit.edu>,
	 "Xinhaoqu (Freddie)" <xinhaoqu@huawei.com>,
	Nick Kossifidis <mick@ics.forth.gr>,
	Allen Baum <allen.baum@esperantotech.com>,
	Josh Scheid <jscheid@ventanamicro.com>,
	 Richard Trauben <rtrauben@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	 Christoph Muellner <cmuellner@linux.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: Re: [PATCH 02/12] riscv: allow different stages with alternatives
Date: Mon, 16 May 2022 14:51:24 +0800	[thread overview]
Message-ID: <CAJF2gTQKsJ00MAyXGnBXR-tK1pAnHeuEr6Se79OYN4_kvPjjFQ@mail.gmail.com> (raw)
In-Reply-To: <20220511192921.2223629-3-heiko@sntech.de>

Reviewed-by: Guo Ren <guoren@kernel.org>

On Thu, May 12, 2022 at 3:29 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Future features may need to be applied at a different
> time during boot, so allow defining stages for alternatives
> and handling them differently depending on the stage.
>
> Also make the alternatives-location more flexible so that
> future stages may provide their own location.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>  arch/riscv/errata/sifive/errata.c    |  3 ++-
>  arch/riscv/include/asm/alternative.h |  5 ++++-
>  arch/riscv/kernel/alternative.c      | 26 +++++++++++++++++---------
>  3 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
> index f5e5ae70e829..4fe03ac41fd7 100644
> --- a/arch/riscv/errata/sifive/errata.c
> +++ b/arch/riscv/errata/sifive/errata.c
> @@ -80,7 +80,8 @@ static void __init warn_miss_errata(u32 miss_errata)
>  }
>
>  void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> -                                    unsigned long archid, unsigned long impid)
> +                                    unsigned long archid, unsigned long impid,
> +                                    unsigned int stage)
>  {
>         struct alt_entry *alt;
>         u32 cpu_req_errata = sifive_errata_probe(archid, impid);
> diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
> index 7b42bcef0ecf..0ff550667e94 100644
> --- a/arch/riscv/include/asm/alternative.h
> +++ b/arch/riscv/include/asm/alternative.h
> @@ -19,6 +19,8 @@
>  #include <linux/stddef.h>
>  #include <asm/hwcap.h>
>
> +#define RISCV_ALTERNATIVES_BOOT                0 /* alternatives applied during regular boot */
> +
>  void __init apply_boot_alternatives(void);
>
>  struct alt_entry {
> @@ -35,7 +37,8 @@ struct errata_checkfunc_id {
>  };
>
>  void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> -                             unsigned long archid, unsigned long impid);
> +                             unsigned long archid, unsigned long impid,
> +                             unsigned int stage);
>
>  #else /* CONFIG_RISCV_ALTERNATIVE */
>
> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> index e8b4a0fe488c..02db62f55bac 100644
> --- a/arch/riscv/kernel/alternative.c
> +++ b/arch/riscv/kernel/alternative.c
> @@ -22,8 +22,8 @@ static struct cpu_manufacturer_info_t {
>  } cpu_mfr_info;
>
>  static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
> -                                unsigned long archid,
> -                                unsigned long impid) __initdata;
> +                                unsigned long archid, unsigned long impid,
> +                                unsigned int stage) __initdata;
>
>  static inline void __init riscv_fill_cpu_mfr_info(void)
>  {
> @@ -58,6 +58,18 @@ static void __init init_alternative(void)
>   * a feature detect on the boot CPU). No need to worry about other CPUs
>   * here.
>   */
> +static void __init _apply_alternatives(struct alt_entry *begin,
> +                                      struct alt_entry *end,
> +                                      unsigned int stage)
> +{
> +       if (!vendor_patch_func)
> +               return;
> +
> +       vendor_patch_func(begin, end,
> +                         cpu_mfr_info.arch_id, cpu_mfr_info.imp_id,
> +                         stage);
> +}
> +
>  void __init apply_boot_alternatives(void)
>  {
>         /* If called on non-boot cpu things could go wrong */
> @@ -65,11 +77,7 @@ void __init apply_boot_alternatives(void)
>
>         init_alternative();
>
> -       if (!vendor_patch_func)
> -               return;
> -
> -       vendor_patch_func((struct alt_entry *)__alt_start,
> -                         (struct alt_entry *)__alt_end,
> -                         cpu_mfr_info.arch_id, cpu_mfr_info.imp_id);
> +       _apply_alternatives((struct alt_entry *)__alt_start,
> +                           (struct alt_entry *)__alt_end,
> +                           RISCV_ALTERNATIVES_BOOT);
>  }
> -
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2022-05-16  6:51 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11 19:29 [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-05-11 19:29 ` Heiko Stuebner
2022-05-11 19:29 ` [PATCH 01/12] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:01   ` Christoph Hellwig
2022-05-16  6:01     ` Christoph Hellwig
2022-05-16  6:45   ` Guo Ren
2022-05-16  6:45     ` Guo Ren
2022-05-11 19:29 ` [PATCH 02/12] riscv: allow different stages with alternatives Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:01   ` Christoph Hellwig
2022-05-16  6:01     ` Christoph Hellwig
2022-05-16  6:51   ` Guo Ren [this message]
2022-05-16  6:51     ` Guo Ren
2022-05-11 19:29 ` [PATCH 03/12] riscv: implement module alternatives Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:02   ` Christoph Hellwig
2022-05-16  6:02     ` Christoph Hellwig
2022-05-16  6:54   ` Guo Ren
2022-05-16  6:54     ` Guo Ren
2022-05-11 19:29 ` [PATCH 04/12] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:03   ` Christoph Hellwig
2022-05-16  6:03     ` Christoph Hellwig
2022-05-16  6:54   ` Guo Ren
2022-05-16  6:54     ` Guo Ren
2022-05-11 19:29 ` [PATCH 05/12] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:03   ` Christoph Hellwig
2022-05-16  6:03     ` Christoph Hellwig
2022-05-16  6:55   ` Guo Ren
2022-05-16  6:55     ` Guo Ren
2022-05-11 19:29 ` [PATCH 06/12] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:04   ` Christoph Hellwig
2022-05-16  6:04     ` Christoph Hellwig
2022-05-16  6:55   ` Guo Ren
2022-05-16  6:55     ` Guo Ren
2022-05-11 19:29 ` [PATCH 07/12] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-11 19:29 ` [PATCH 08/12] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:04   ` Christoph Hellwig
2022-05-16  6:04     ` Christoph Hellwig
2022-05-16  6:55   ` Guo Ren
2022-05-16  6:55     ` Guo Ren
2022-05-23 14:03   ` Alexandre Ghiti
2022-05-23 14:03     ` Alexandre Ghiti
2022-05-25 15:22     ` Heiko Stübner
2022-05-25 15:22       ` Heiko Stübner
2022-05-28  8:15       ` Alexandre Ghiti
2022-05-28  8:15         ` Alexandre Ghiti
2022-05-11 19:29 ` [PATCH 09/12] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:10   ` Christoph Hellwig
2022-05-16  6:10     ` Christoph Hellwig
2022-05-16  9:09     ` Philipp Tomsich
2022-05-16  9:09       ` Philipp Tomsich
2022-05-16 10:30       ` Heiko Stübner
2022-05-16 10:30         ` Heiko Stübner
2022-05-11 19:29 ` [PATCH 10/12] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-11 19:29 ` [PATCH 11/12] riscv: don't use global static vars to store alternative data Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-16  6:15   ` Christoph Hellwig
2022-05-16  6:15     ` Christoph Hellwig
2022-05-11 19:29 ` [PATCH 12/12] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-05-11 19:29   ` Heiko Stuebner
2022-05-13 13:37   ` Guo Ren
2022-05-13 13:37     ` Guo Ren
2022-05-13  3:32 ` [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt
2022-05-13  3:32   ` Palmer Dabbelt
2022-05-13 21:41   ` Heiko Stuebner
2022-05-13 21:41     ` Heiko Stuebner

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