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* [PATCH 1/2] drm/i915: Specify bsd rings through exec flag
@ 2015-01-13  0:48 Zhipeng Gong
  2015-01-13  0:48 ` [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Zhipeng Gong
  2015-01-14  0:36 ` [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Daniel Vetter
  0 siblings, 2 replies; 7+ messages in thread
From: Zhipeng Gong @ 2015-01-13  0:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: rodrigo.vivi

On Skylake GT3 we have 2 Video Command Streamers (VCS), which is asymmetrical.
For example, HEVC GPU commands can be only dispatched to VCS1 ring.
But userspace has no control when using VCS1 or VCS2. This patch introduces
a mechanism to avoid the default ping-pong mode and use one specific ring
through execution flag. This mechanism is usable for all the platforms
with 2 VCS rings.

The open source usage is from these two commits in vaapi/intel:
	commit 702050f04131a44ef8ac16651708ce8a8d98e4b8
	Author: Zhao, Yakui <yakui.zhao@intel.com>
	Date:   Mon Nov 17 12:44:19 2014 +0800

	    Allow the batchbuffer to be submitted with override flag

	commit a56efcdf27d11ad9b21664b4a2cda72d7f90f5a8
	Author: Zhao Yakui <yakui.zhao@intel.com>
	Date:   Mon Nov 17 12:44:22 2014 +0800

	    Add the override flag to assure that HEVC video command
		always uses BSD ring0 for SKL GT3 machine

v2: fix whitespace (Rodrigo)
v3: remove incorrect chunk that came on -collector rebase. (Rodrigo)
v4: change the comment (Zhipeng)
v5: address Daniel's comment (Zhipeng)

Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v4)
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 26 ++++++++++++++++++++++++--
 include/uapi/drm/i915_drm.h                |  8 +++++++-
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e3ef177..b773368 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1380,13 +1380,35 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
+	if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
+	    ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
+		DRM_DEBUG("execbuf with non bsd ring but with invalid "
+			"bsd dispatch flags: %d\n", (int)(args->flags));
+		return -EINVAL;
+	} 
+
 	if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
 		ring = &dev_priv->ring[RCS];
 	else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
 		if (HAS_BSD2(dev)) {
 			int ring_id;
-			ring_id = gen8_dispatch_bsd_ring(dev, file);
-			ring = &dev_priv->ring[ring_id];
+
+			switch (args->flags & I915_EXEC_BSD_MASK) {
+			case I915_EXEC_BSD_DEFAULT:
+				ring_id = gen8_dispatch_bsd_ring(dev, file);
+				ring = &dev_priv->ring[ring_id];
+				break;
+			case I915_EXEC_BSD_RING1:
+				ring = &dev_priv->ring[VCS];
+				break;
+			case I915_EXEC_BSD_RING2:
+				ring = &dev_priv->ring[VCS2];
+				break;
+			default:
+				DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
+					  (int)(args->flags & I915_EXEC_BSD_MASK));
+				return -EINVAL;
+			}
 		} else
 			ring = &dev_priv->ring[VCS];
 	} else
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2e559f6e..dc84561 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -750,7 +750,13 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_HANDLE_LUT		(1<<12)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
+/** Used for switching BSD rings on the platforms with two BSD rings */
+#define I915_EXEC_BSD_MASK		(3<<13)
+#define I915_EXEC_BSD_DEFAULT		(0<<13) /* default ping-pong mode */
+#define I915_EXEC_BSD_RING1		(1<<13)
+#define I915_EXEC_BSD_RING2		(2<<13)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
1.8.3.1

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam
  2015-01-13  0:48 [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Zhipeng Gong
@ 2015-01-13  0:48 ` Zhipeng Gong
  2015-01-13  6:30   ` shuang.he
  2015-01-20 21:50   ` Rodrigo Vivi
  2015-01-14  0:36 ` [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Daniel Vetter
  1 sibling, 2 replies; 7+ messages in thread
From: Zhipeng Gong @ 2015-01-13  0:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: rodrigo.vivi

This will let userland only try to use the new ring
when the appropriate kernel is present

v2: change the number to be consistent with upstream (Zhipeng)

Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
Reviewed--by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v1)
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 include/uapi/drm/i915_drm.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 8cbff30..f0786d6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -92,6 +92,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_HAS_VEBOX:
 		value = intel_ring_initialized(&dev_priv->ring[VECS]);
 		break;
+	case I915_PARAM_HAS_BSD2:
+		value = intel_ring_initialized(&dev_priv->ring[VCS2]);
+		break;
 	case I915_PARAM_HAS_RELAXED_FENCING:
 		value = 1;
 		break;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index dc84561..6eed16b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -346,6 +346,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_CMD_PARSER_VERSION	 28
 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
 #define I915_PARAM_MMAP_VERSION          30
+#define I915_PARAM_HAS_BSD2		 31
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam
  2015-01-13  0:48 ` [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Zhipeng Gong
@ 2015-01-13  6:30   ` shuang.he
  2015-01-20 21:50   ` Rodrigo Vivi
  1 sibling, 0 replies; 7+ messages in thread
From: shuang.he @ 2015-01-13  6:30 UTC (permalink / raw)
  To: shuang.he, ethan.gao, intel-gfx, zhipeng.gong

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  354/354              354/354
ILK                                  354/354              354/354
SNB              +1-1              401/424              401/424
IVB                                  488/488              488/488
BYT                                  278/278              278/278
HSW                 -42              529/529              487/529
BDW                 -1              405/405              404/405
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 SNB  igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible      NSPT(1, M35)PASS(7, M35M22)      PASS(1, M35)
*SNB  igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible      PASS(8, M35M22)      DMESG_WARN(1, M35)
 HSW  igt_kms_cursor_crc_cursor-size-change      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_kms_fence_pin_leak      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_kms_flip_event_leak      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_lpsp_non-edp      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_cursor      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_cursor-dpms      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_dpms-non-lpsp      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_drm-resources-equal      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_fences      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_fences-dpms      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_gem-execbuf      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_gem-mmap-cpu      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_gem-mmap-gtt      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_gem-pread      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_i2c      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_modeset-non-lpsp      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_pci-d3-state      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_pm_rpm_rte      NSPT(4, M40M19)PASS(1, M20)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-bcs-early-read-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-bcs-early-read-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-bcs-overwrite-source-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-bcs-overwrite-source-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-rcs-early-read-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-rcs-overwrite-source-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gtt-rcs-overwrite-source-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-bcs-early-read-interruptible      DMESG_WARN(3, M40)PASS(2, M20M19)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-bcs-overwrite-source-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-bcs-overwrite-source-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-rcs-early-read-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write-interruptible      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-rcs-overwrite-source-forked      DMESG_WARN(4, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
 HSW  igt_gem_concurrent_blit_gttX-rcs-overwrite-source-interruptible      DMESG_WARN(2, M40M19)PASS(1, M20)      DMESG_WARN(1, M40)
*BDW  igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible      PASS(7, M30M28)      DMESG_WARN(1, M30)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] drm/i915: Specify bsd rings through exec flag
  2015-01-13  0:48 [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Zhipeng Gong
  2015-01-13  0:48 ` [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Zhipeng Gong
@ 2015-01-14  0:36 ` Daniel Vetter
  2015-01-20 21:53   ` Rodrigo Vivi
  1 sibling, 1 reply; 7+ messages in thread
From: Daniel Vetter @ 2015-01-14  0:36 UTC (permalink / raw)
  To: Zhipeng Gong; +Cc: intel-gfx, Rodrigo Vivi

On Tue, Jan 13, 2015 at 08:48:24AM +0800, Zhipeng Gong wrote:
> On Skylake GT3 we have 2 Video Command Streamers (VCS), which is asymmetrical.
> For example, HEVC GPU commands can be only dispatched to VCS1 ring.
> But userspace has no control when using VCS1 or VCS2. This patch introduces
> a mechanism to avoid the default ping-pong mode and use one specific ring
> through execution flag. This mechanism is usable for all the platforms
> with 2 VCS rings.
>
> The open source usage is from these two commits in vaapi/intel:
> commit 702050f04131a44ef8ac16651708ce8a8d98e4b8
> Author: Zhao, Yakui <yakui.zhao@intel.com>
> Date:   Mon Nov 17 12:44:19 2014 +0800
>
>    Allow the batchbuffer to be submitted with override flag
>
> commit a56efcdf27d11ad9b21664b4a2cda72d7f90f5a8
> Author: Zhao Yakui <yakui.zhao@intel.com>
> Date:   Mon Nov 17 12:44:22 2014 +0800
>
>    Add the override flag to assure that HEVC video command
> always uses BSD ring0 for SKL GT3 machine
>
> v2: fix whitespace (Rodrigo)
> v3: remove incorrect chunk that came on -collector rebase. (Rodrigo)
> v4: change the comment (Zhipeng)
> v5: address Daniel's comment (Zhipeng)

Can you please be more specific here for the in-patch changelog? The idea
is that people understand the changes with just this, as-is you need to
dig out the old review thread (which is pretty much impossible).

I'll add that to the commit message when merging, so no need to
resend. I'll merge as soon as Rodrigo has doublechecked the revised
patches.
-Daniel

>
> Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v4)
> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 26 ++++++++++++++++++++++++--
>  include/uapi/drm/i915_drm.h                |  8 +++++++-
>  2 files changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index e3ef177..b773368 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1380,13 +1380,35 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>   return -EINVAL;
>   }
>
> + if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
> +    ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
> + DRM_DEBUG("execbuf with non bsd ring but with invalid "
> + "bsd dispatch flags: %d\n", (int)(args->flags));
> + return -EINVAL;
> + }
> +
>   if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
>   ring = &dev_priv->ring[RCS];
>   else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
>   if (HAS_BSD2(dev)) {
>   int ring_id;
> - ring_id = gen8_dispatch_bsd_ring(dev, file);
> - ring = &dev_priv->ring[ring_id];
> +
> + switch (args->flags & I915_EXEC_BSD_MASK) {
> + case I915_EXEC_BSD_DEFAULT:
> + ring_id = gen8_dispatch_bsd_ring(dev, file);
> + ring = &dev_priv->ring[ring_id];
> + break;
> + case I915_EXEC_BSD_RING1:
> + ring = &dev_priv->ring[VCS];
> + break;
> + case I915_EXEC_BSD_RING2:
> + ring = &dev_priv->ring[VCS2];
> + break;
> + default:
> + DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
> +  (int)(args->flags & I915_EXEC_BSD_MASK));
> + return -EINVAL;
> + }
>   } else
>   ring = &dev_priv->ring[VCS];
>   } else
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 2e559f6e..dc84561 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -750,7 +750,13 @@ struct drm_i915_gem_execbuffer2 {
>   */
>  #define I915_EXEC_HANDLE_LUT (1<<12)
>
> -#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
> +/** Used for switching BSD rings on the platforms with two BSD rings */
> +#define I915_EXEC_BSD_MASK (3<<13)
> +#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
> +#define I915_EXEC_BSD_RING1 (1<<13)
> +#define I915_EXEC_BSD_RING2 (2<<13)
> +
> +#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
>
>  #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
>  #define i915_execbuffer2_set_context_id(eb2, context) \
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam
  2015-01-13  0:48 ` [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Zhipeng Gong
  2015-01-13  6:30   ` shuang.he
@ 2015-01-20 21:50   ` Rodrigo Vivi
  1 sibling, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2015-01-20 21:50 UTC (permalink / raw)
  To: Zhipeng Gong; +Cc: intel-gfx, Vivi, Rodrigo

for v2 as well:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Jan 12, 2015 at 4:48 PM, Zhipeng Gong <zhipeng.gong@intel.com> wrote:
> This will let userland only try to use the new ring
> when the appropriate kernel is present
>
> v2: change the number to be consistent with upstream (Zhipeng)
>
> Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
> Reviewed--by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v1)
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 3 +++
>  include/uapi/drm/i915_drm.h     | 1 +
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 8cbff30..f0786d6 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -92,6 +92,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>         case I915_PARAM_HAS_VEBOX:
>                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
>                 break;
> +       case I915_PARAM_HAS_BSD2:
> +               value = intel_ring_initialized(&dev_priv->ring[VCS2]);
> +               break;
>         case I915_PARAM_HAS_RELAXED_FENCING:
>                 value = 1;
>                 break;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index dc84561..6eed16b 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -346,6 +346,7 @@ typedef struct drm_i915_irq_wait {
>  #define I915_PARAM_CMD_PARSER_VERSION   28
>  #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
>  #define I915_PARAM_MMAP_VERSION          30
> +#define I915_PARAM_HAS_BSD2             31
>
>  typedef struct drm_i915_getparam {
>         int param;
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] drm/i915: Specify bsd rings through exec flag
  2015-01-14  0:36 ` [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Daniel Vetter
@ 2015-01-20 21:53   ` Rodrigo Vivi
  0 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2015-01-20 21:53 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx, Rodrigo Vivi

Sorry for the delay.

Also for v5:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Tue, Jan 13, 2015 at 4:36 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Jan 13, 2015 at 08:48:24AM +0800, Zhipeng Gong wrote:
>> On Skylake GT3 we have 2 Video Command Streamers (VCS), which is asymmetrical.
>> For example, HEVC GPU commands can be only dispatched to VCS1 ring.
>> But userspace has no control when using VCS1 or VCS2. This patch introduces
>> a mechanism to avoid the default ping-pong mode and use one specific ring
>> through execution flag. This mechanism is usable for all the platforms
>> with 2 VCS rings.
>>
>> The open source usage is from these two commits in vaapi/intel:
>> commit 702050f04131a44ef8ac16651708ce8a8d98e4b8
>> Author: Zhao, Yakui <yakui.zhao@intel.com>
>> Date:   Mon Nov 17 12:44:19 2014 +0800
>>
>>    Allow the batchbuffer to be submitted with override flag
>>
>> commit a56efcdf27d11ad9b21664b4a2cda72d7f90f5a8
>> Author: Zhao Yakui <yakui.zhao@intel.com>
>> Date:   Mon Nov 17 12:44:22 2014 +0800
>>
>>    Add the override flag to assure that HEVC video command
>> always uses BSD ring0 for SKL GT3 machine
>>
>> v2: fix whitespace (Rodrigo)
>> v3: remove incorrect chunk that came on -collector rebase. (Rodrigo)
>> v4: change the comment (Zhipeng)
>> v5: address Daniel's comment (Zhipeng)
>
> Can you please be more specific here for the in-patch changelog? The idea
> is that people understand the changes with just this, as-is you need to
> dig out the old review thread (which is pretty much impossible).
>
> I'll add that to the commit message when merging, so no need to
> resend. I'll merge as soon as Rodrigo has doublechecked the revised
> patches.
> -Daniel
>
>>
>> Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v4)
>> ---
>>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 26 ++++++++++++++++++++++++--
>>  include/uapi/drm/i915_drm.h                |  8 +++++++-
>>  2 files changed, 31 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> index e3ef177..b773368 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> @@ -1380,13 +1380,35 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>>   return -EINVAL;
>>   }
>>
>> + if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
>> +    ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
>> + DRM_DEBUG("execbuf with non bsd ring but with invalid "
>> + "bsd dispatch flags: %d\n", (int)(args->flags));
>> + return -EINVAL;
>> + }
>> +
>>   if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
>>   ring = &dev_priv->ring[RCS];
>>   else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
>>   if (HAS_BSD2(dev)) {
>>   int ring_id;
>> - ring_id = gen8_dispatch_bsd_ring(dev, file);
>> - ring = &dev_priv->ring[ring_id];
>> +
>> + switch (args->flags & I915_EXEC_BSD_MASK) {
>> + case I915_EXEC_BSD_DEFAULT:
>> + ring_id = gen8_dispatch_bsd_ring(dev, file);
>> + ring = &dev_priv->ring[ring_id];
>> + break;
>> + case I915_EXEC_BSD_RING1:
>> + ring = &dev_priv->ring[VCS];
>> + break;
>> + case I915_EXEC_BSD_RING2:
>> + ring = &dev_priv->ring[VCS2];
>> + break;
>> + default:
>> + DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
>> +  (int)(args->flags & I915_EXEC_BSD_MASK));
>> + return -EINVAL;
>> + }
>>   } else
>>   ring = &dev_priv->ring[VCS];
>>   } else
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 2e559f6e..dc84561 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -750,7 +750,13 @@ struct drm_i915_gem_execbuffer2 {
>>   */
>>  #define I915_EXEC_HANDLE_LUT (1<<12)
>>
>> -#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
>> +/** Used for switching BSD rings on the platforms with two BSD rings */
>> +#define I915_EXEC_BSD_MASK (3<<13)
>> +#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
>> +#define I915_EXEC_BSD_RING1 (1<<13)
>> +#define I915_EXEC_BSD_RING2 (2<<13)
>> +
>> +#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
>>
>>  #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
>>  #define i915_execbuffer2_set_context_id(eb2, context) \
>> --
>> 1.8.3.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 1/2] drm/i915: Specify bsd rings through exec flag
@ 2014-08-07  7:48 Zhipeng Gong
  0 siblings, 0 replies; 7+ messages in thread
From: Zhipeng Gong @ 2014-08-07  7:48 UTC (permalink / raw)
  To: intel-gfx

On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.

Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 19 +++++++++++++++++--
 include/uapi/drm/i915_drm.h                |  8 +++++++-
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 60998fc..f9ed8e0 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1279,8 +1279,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 	else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
 		if (HAS_BSD2(dev)) {
 			int ring_id;
-			ring_id = gen8_dispatch_bsd_ring(dev, file);
-			ring = &dev_priv->ring[ring_id];
+
+			switch (args->flags & I915_EXEC_BSD_MASK) {
+			case I915_EXEC_BSD_DEFAULT:
+				ring_id = gen8_dispatch_bsd_ring(dev, file);
+				ring = &dev_priv->ring[ring_id];
+				break;
+			case I915_EXEC_BSD_RING1:
+				ring = &dev_priv->ring[VCS];
+				break;
+			case I915_EXEC_BSD_RING2:
+				ring = &dev_priv->ring[VCS2];
+				break;
+			default:
+				DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
+ 					  (int)(args->flags & I915_EXEC_BSD_MASK));
+				return -EINVAL;
+			}
 		} else
 			ring = &dev_priv->ring[VCS];
 	} else
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ff57f07..421420a 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -736,7 +736,13 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_HANDLE_LUT		(1<<12)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
+/** Used for switching BSD rings on the platforms with two BSD rings */
+#define I915_EXEC_BSD_MASK		(3<<13)
+#define I915_EXEC_BSD_DEFAULT		(0<<13) /* default ping-pong mode */
+#define I915_EXEC_BSD_RING1		(1<<13)
+#define I915_EXEC_BSD_RING2		(2<<13)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
2.0.3

^ permalink raw reply related	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2015-01-20 21:53 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-13  0:48 [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Zhipeng Gong
2015-01-13  0:48 ` [PATCH 2/2] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Zhipeng Gong
2015-01-13  6:30   ` shuang.he
2015-01-20 21:50   ` Rodrigo Vivi
2015-01-14  0:36 ` [PATCH 1/2] drm/i915: Specify bsd rings through exec flag Daniel Vetter
2015-01-20 21:53   ` Rodrigo Vivi
  -- strict thread matches above, loose matches on Subject: below --
2014-08-07  7:48 Zhipeng Gong

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