From: Alistair Francis <alistair23@gmail.com> To: Richard Henderson <richard.henderson@linaro.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, qemu-riscv@nongnu.org Subject: Re: [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Date: Mon, 26 Nov 2018 14:58:50 -0800 [thread overview] Message-ID: <CAKmqyKM-+HDbUGNjZjS5f0HaqzOpsms3j3+wVgo7gjvL-JT0CQ@mail.gmail.com> (raw) In-Reply-To: <8bacdaca-94c2-d2c7-3af7-b98517a98b64@linaro.org> On Tue, Nov 20, 2018 at 11:40 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 11/21/18 12:49 AM, Alistair Francis wrote: > > On Fri, Nov 16, 2018 at 1:14 AM Richard Henderson > > <richard.henderson@linaro.org> wrote: > >> > >> On 11/15/18 11:36 PM, Alistair Francis wrote: > >>> +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, > >>> + TCGReg arg2, TCGLabel *l) > >>> +{ > >>> + RISCVInsn op = tcg_brcond_to_riscv[cond].op; > >>> + bool swap = tcg_brcond_to_riscv[cond].swap; > >>> + > >>> + tcg_out_opc_branch(s, op, swap ? arg2 : arg1, swap ? arg1 : arg2, 0); > >> > >> You might want to tcg_debug_assert(op != 0) here. > >> > >>> + if (l->has_value) { > >>> + reloc_sbimm12(s->code_ptr - 1, l->u.value_ptr); > >> > >> I'm concerned about the conditional branch range. +-4K isn't much to work > >> with. The minimum we have for other hosts is +-32K. > >> > >> We have two options: (1) greatly reduce the max size of the TB for this host; > >> (2) be prepared to emit a 2 insn sequence: conditional branch across > >> unconditional branch, with forward branches that turn out to be small patched > >> with a nop. > >> > >> FWIW, the first case would be done via modification of tcg_op_buf_full. You > >> might have to go as low as 500 opcodes, I'm not sure. > > > > How do we do option 2? > > If l->has_value, just check the actual range. But of course backward branching > isn't that common in tcg generated code. Most branches within the TB are short > forward branches, but we also don't know how short is short. > > But every TB begins with a test of env->exit_code and a conditional branch to > the end of the block, where we place some code to return to the main loop and > return the pointer to the TB at which we exited. Thus every TB has a branch > that spans the size of the entire TB. > > So, invent (or repurpose) an R_RISCV_FOO value. It doesn't matter which > because it's private within tcg/riscv/. Just add some commentary. (See e.g. > tcg/sparc/ and its use of R_SPARC_13.) > > While generating code, emit the conditional branch as normal; leave the unknown > destination 0 for now. Emit a nop as the second insn. > > When resolving R_RISCV_FOO, if the conditional branch is in range, great! Just > patch it. If it is out of range, then you need to edit the conditional branch > to reverse the condition (insn ^ (1 << 12)) and branch to pc+8, i.e. over the > next instruction. Which was a nop during generation, but you will now install > jal r0,dest going to the real destination. Ok, I think I have done this correctly. I have something that compiles and runs. I'll send a second RFC out sometime this week. It won't be based on your latest patches and it's still missing some things but I want to keep this moving along. Thanks so much for your help Richard! Alistair > > > r~
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Richard Henderson <richard.henderson@linaro.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, qemu-riscv@nongnu.org Subject: Re: [Qemu-riscv] [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Date: Mon, 26 Nov 2018 14:58:50 -0800 [thread overview] Message-ID: <CAKmqyKM-+HDbUGNjZjS5f0HaqzOpsms3j3+wVgo7gjvL-JT0CQ@mail.gmail.com> (raw) In-Reply-To: <8bacdaca-94c2-d2c7-3af7-b98517a98b64@linaro.org> On Tue, Nov 20, 2018 at 11:40 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 11/21/18 12:49 AM, Alistair Francis wrote: > > On Fri, Nov 16, 2018 at 1:14 AM Richard Henderson > > <richard.henderson@linaro.org> wrote: > >> > >> On 11/15/18 11:36 PM, Alistair Francis wrote: > >>> +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, > >>> + TCGReg arg2, TCGLabel *l) > >>> +{ > >>> + RISCVInsn op = tcg_brcond_to_riscv[cond].op; > >>> + bool swap = tcg_brcond_to_riscv[cond].swap; > >>> + > >>> + tcg_out_opc_branch(s, op, swap ? arg2 : arg1, swap ? arg1 : arg2, 0); > >> > >> You might want to tcg_debug_assert(op != 0) here. > >> > >>> + if (l->has_value) { > >>> + reloc_sbimm12(s->code_ptr - 1, l->u.value_ptr); > >> > >> I'm concerned about the conditional branch range. +-4K isn't much to work > >> with. The minimum we have for other hosts is +-32K. > >> > >> We have two options: (1) greatly reduce the max size of the TB for this host; > >> (2) be prepared to emit a 2 insn sequence: conditional branch across > >> unconditional branch, with forward branches that turn out to be small patched > >> with a nop. > >> > >> FWIW, the first case would be done via modification of tcg_op_buf_full. You > >> might have to go as low as 500 opcodes, I'm not sure. > > > > How do we do option 2? > > If l->has_value, just check the actual range. But of course backward branching > isn't that common in tcg generated code. Most branches within the TB are short > forward branches, but we also don't know how short is short. > > But every TB begins with a test of env->exit_code and a conditional branch to > the end of the block, where we place some code to return to the main loop and > return the pointer to the TB at which we exited. Thus every TB has a branch > that spans the size of the entire TB. > > So, invent (or repurpose) an R_RISCV_FOO value. It doesn't matter which > because it's private within tcg/riscv/. Just add some commentary. (See e.g. > tcg/sparc/ and its use of R_SPARC_13.) > > While generating code, emit the conditional branch as normal; leave the unknown > destination 0 for now. Emit a nop as the second insn. > > When resolving R_RISCV_FOO, if the conditional branch is in range, great! Just > patch it. If it is out of range, then you need to edit the conditional branch > to reverse the condition (insn ^ (1 << 12)) and branch to pc+8, i.e. over the > next instruction. Which was a nop during generation, but you will now install > jal r0,dest going to the real destination. Ok, I think I have done this correctly. I have something that compiles and runs. I'll send a second RFC out sometime this week. It won't be based on your latest patches and it's still missing some things but I want to keep this moving along. Thanks so much for your help Richard! Alistair > > > r~
next prev parent reply other threads:[~2018-11-26 22:59 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-15 22:33 [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support Alistair Francis 2018-11-15 22:33 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson 2018-11-16 7:47 ` Richard Henderson 2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:47 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson 2018-11-16 17:20 ` Richard Henderson 2018-11-16 17:20 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:58 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:58 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:59 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:59 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:13 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:13 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:26 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:26 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:27 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:27 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:33 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:33 ` [Qemu-riscv] " Richard Henderson 2018-11-21 1:15 ` Alistair Francis 2018-11-21 1:15 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:25 ` Richard Henderson 2018-11-21 7:25 ` [Qemu-riscv] " Richard Henderson 2018-11-21 15:53 ` Palmer Dabbelt 2018-11-21 15:53 ` [Qemu-riscv] " Palmer Dabbelt 2018-11-21 17:01 ` Richard Henderson 2018-11-21 17:01 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:55 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:55 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:56 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:56 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:59 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:59 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 9:14 ` [Qemu-devel] " Richard Henderson 2018-11-16 9:14 ` [Qemu-riscv] " Richard Henderson 2018-11-20 23:49 ` Alistair Francis 2018-11-20 23:49 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:40 ` Richard Henderson 2018-11-21 7:40 ` [Qemu-riscv] " Richard Henderson 2018-11-26 22:58 ` Alistair Francis [this message] 2018-11-26 22:58 ` Alistair Francis 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 9:24 ` [Qemu-devel] " Richard Henderson 2018-11-16 9:24 ` [Qemu-riscv] " Richard Henderson 2018-11-21 0:18 ` Alistair Francis 2018-11-21 0:18 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:43 ` Richard Henderson 2018-11-21 7:43 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct " Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:10 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:10 ` [Qemu-riscv] " Richard Henderson 2018-11-19 23:06 ` Alistair Francis 2018-11-19 23:06 ` [Qemu-riscv] " Alistair Francis 2018-11-20 6:57 ` Richard Henderson 2018-11-20 6:57 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:22 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:22 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:25 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:25 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:26 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:26 ` [Qemu-riscv] " Richard Henderson 2018-11-19 23:04 ` Alistair Francis 2018-11-19 23:04 ` [Qemu-riscv] " Alistair Francis 2018-11-20 6:55 ` Richard Henderson 2018-11-20 6:55 ` [Qemu-riscv] " Richard Henderson 2018-11-20 23:22 ` Alistair Francis 2018-11-20 23:22 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:27 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:27 ` [Qemu-riscv] " Richard Henderson 2018-11-16 17:29 ` Richard Henderson 2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:29 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:30 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:30 ` [Qemu-riscv] " Richard Henderson 2018-11-16 8:31 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support no-reply 2018-11-16 8:31 ` [Qemu-riscv] " no-reply
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