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From: Alistair Francis <alistair23@gmail.com>
To: Jose Martins <josemartins90@gmail.com>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg
Date: Fri, 11 Jun 2021 09:12:09 +1000	[thread overview]
Message-ID: <CAKmqyKMvaLn5YUPVBngDjziud-t8P717cp-LsrOBo-VG18BMiw@mail.gmail.com> (raw)
In-Reply-To: <20210522155902.374439-1-josemartins90@gmail.com>

On Sun, May 23, 2021 at 1:59 AM Jose Martins <josemartins90@gmail.com> wrote:
>
> The specification mandates for certain bits to be hardwired in the
> hypervisor delegation registers. This was not being enforced.
>
> Signed-off-by: Jose Martins <josemartins90@gmail.com>
> ---
>  target/riscv/csr.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d2585395bf..9b74a00cc9 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -394,6 +394,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
>                                             VS_MODE_INTERRUPTS;
> +static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
>  static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
>                                       VS_MODE_INTERRUPTS;
>  static const target_ulong delegable_excps =
> @@ -416,6 +417,14 @@ static const target_ulong delegable_excps =
>      (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
>      (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
>      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
> +static const target_ulong vs_delegable_excps = delegable_excps &
> +    ~((1ULL << (RISCV_EXCP_S_ECALL)) |

> +    (1ULL << (RISCV_EXCP_VS_ECALL)) |
> +    (1ULL << (RISCV_EXCP_M_ECALL)) |

These two are both read only 0, shouldn't they not be included in this list?

> +    (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
> +    (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
> +    (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
> +    (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
>  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
>      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
>      SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
> @@ -963,7 +972,7 @@ static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    env->hedeleg = val;
> +    env->hedeleg = val & vs_delegable_excps;

Because we then allow a write to occur here.

Alistair

>      return 0;
>  }
>
> @@ -975,7 +984,7 @@ static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    env->hideleg = val;
> +    env->hideleg = val & vs_delegable_ints;
>      return 0;
>  }
>
> --
> 2.30.2
>
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Jose Martins <josemartins90@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	 "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	 Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	 Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg
Date: Fri, 11 Jun 2021 09:12:09 +1000	[thread overview]
Message-ID: <CAKmqyKMvaLn5YUPVBngDjziud-t8P717cp-LsrOBo-VG18BMiw@mail.gmail.com> (raw)
In-Reply-To: <20210522155902.374439-1-josemartins90@gmail.com>

On Sun, May 23, 2021 at 1:59 AM Jose Martins <josemartins90@gmail.com> wrote:
>
> The specification mandates for certain bits to be hardwired in the
> hypervisor delegation registers. This was not being enforced.
>
> Signed-off-by: Jose Martins <josemartins90@gmail.com>
> ---
>  target/riscv/csr.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d2585395bf..9b74a00cc9 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -394,6 +394,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
>                                             VS_MODE_INTERRUPTS;
> +static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
>  static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
>                                       VS_MODE_INTERRUPTS;
>  static const target_ulong delegable_excps =
> @@ -416,6 +417,14 @@ static const target_ulong delegable_excps =
>      (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
>      (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
>      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
> +static const target_ulong vs_delegable_excps = delegable_excps &
> +    ~((1ULL << (RISCV_EXCP_S_ECALL)) |

> +    (1ULL << (RISCV_EXCP_VS_ECALL)) |
> +    (1ULL << (RISCV_EXCP_M_ECALL)) |

These two are both read only 0, shouldn't they not be included in this list?

> +    (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
> +    (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
> +    (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
> +    (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
>  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
>      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
>      SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
> @@ -963,7 +972,7 @@ static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    env->hedeleg = val;
> +    env->hedeleg = val & vs_delegable_excps;

Because we then allow a write to occur here.

Alistair

>      return 0;
>  }
>
> @@ -975,7 +984,7 @@ static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    env->hideleg = val;
> +    env->hideleg = val & vs_delegable_ints;
>      return 0;
>  }
>
> --
> 2.30.2
>
>


  parent reply	other threads:[~2021-06-10 23:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-22 15:59 [PATCH] target/riscv: hardwire bits in hideleg and hedeleg Jose Martins
2021-05-22 15:59 ` Jose Martins
2021-05-25  7:22 ` LIU Zhiwei
2021-05-25  7:22   ` LIU Zhiwei
2021-05-25 17:50   ` Jose Martins
2021-05-25 17:50     ` Jose Martins
2021-05-28  1:56     ` LIU Zhiwei
2021-05-28  1:56       ` LIU Zhiwei
2021-05-28  2:00 ` LIU Zhiwei
2021-05-28  2:00   ` LIU Zhiwei
2021-06-10 23:12 ` Alistair Francis [this message]
2021-06-10 23:12   ` Alistair Francis
2021-06-24 13:48   ` Jose Martins
2021-06-24 13:48     ` Jose Martins
2021-07-08  4:45     ` Alistair Francis
2021-07-08  4:45       ` Alistair Francis

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