From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wxy194768@alibaba-inc.com, michaeljclark@mac.com, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com> Subject: Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Date: Thu, 22 Apr 2021 10:21:36 +1000 [thread overview] Message-ID: <CAKmqyKNEEBv4AQAhb-vNxz-DoEp3K3M+eJ2dbsbU_zjkECh=4Q@mail.gmail.com> (raw) In-Reply-To: <89137bb9-4312-ac27-5c63-c0bab0f4c139@c-sky.com> On Tue, Apr 20, 2021 at 5:20 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > > On 2021/4/20 下午2:26, Alistair Francis wrote: > > On Tue, Apr 20, 2021 at 11:45 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >> > >> On 2021/4/20 上午7:30, Alistair Francis wrote: > >>> On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >>>> This patch set gives an implementation of "RISC-V Core-Local Interrupt > >>>> Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where > >>>> you can find the pdf format or the source code. > >>>> > >>>> I take over the job from Michael Clark, who gave the first implementation > >>>> of clic-v0.7 specification. If there is any copyright question, please > >>>> let me know. > >>> You need to make sure you leave all original copyright notices and SoB in place. > >> OK. > >> > >> Is it OK that keep the original copyright notices for new files and > >> your SoB in every patch, Michael? > >> > >>>> Features: > >>>> 1. support four kinds of trigger types. > >>>> 2. Preserve the CSR WARL/WPRI semantics. > >>>> 3. Option to select different modes, such as M/S/U or M/U. > >>>> 4. At most 4096 interrupts. > >>>> 5. At most 1024 apertures. > >>>> > >>>> Todo: > >>>> 1. Encode the interrupt trigger information to exccode. > >>>> 2. Support complete CSR mclicbase when its number is fixed. > >>>> 3. Gave each aperture an independend address. > >>>> > >>>> It have passed my qtest case and freertos test. Welcome to have a try > >>>> for your hardware. > >>> It doesn't seem to be connected to any machine. How are you testing this? > >> There is a machine called SMARTL in my repository[1]. The qtest case > >> is tests/qtest/test-riscv32-clic.c. If it's better, I can upstream the > >> machine together next version. > > I don't really want to add a new hardware device when it isn't > > connected to a machine. It would be great if we could connect it to a > > machine. If not SMARTL maybe we could add it as an option to the virt > > machine? > Currently it is good to connect CLIC to virt machine. I can fix it in > the next version if it is OK for you. The CLIC seems to be gaining traction so I think it makes sense to start to think about connecting it up. We don't want to break backwards compatibility though so make sure it's an option, for example -machine virt,clic=true > > What is SMARTL? Is that a publically available board? > > SMARTL is a fpga evaluation board. We usually use it to debug programs > for XuanTie CPU serials. > It has a 32bit CPU, 1 UART, 4 timers, and the CLIC interrupt > controller. I will give a detailed documentation > when I upstream it. > > There are still many other RISC-V boards, but more complex. I plan to > upstream the XuanTie CPU > and some widely used boards after the P extension and CLIC. I would prefer to add boards that are publicly available, so if there are some that would be great! Alistair > > Zhiwei > > > > > Alistair > > > >> Zhiwei > >> > >> [1]https://github.com/romanheros/qemu, branch: riscv-clic-upstream-rfc > >> > >> > >>> Alistair > >>> > >>>> Any advice is welcomed. Thanks very much. > >>>> > >>>> Zhiwei > >>>> > >>>> [1] specification website: https://github.com/riscv/riscv-fast-interrupt. > >>>> [2] Michael Clark origin work: https://github.com/sifive/riscv-qemu/tree/sifive-clic. > >>>> > >>>> > >>>> LIU Zhiwei (11): > >>>> target/riscv: Add CLIC CSR mintstatus > >>>> target/riscv: Update CSR xintthresh in CLIC mode > >>>> hw/intc: Add CLIC device > >>>> target/riscv: Update CSR xie in CLIC mode > >>>> target/riscv: Update CSR xip in CLIC mode > >>>> target/riscv: Update CSR xtvec in CLIC mode > >>>> target/riscv: Update CSR xtvt in CLIC mode > >>>> target/riscv: Update CSR xnxti in CLIC mode > >>>> target/riscv: Update CSR mclicbase in CLIC mode > >>>> target/riscv: Update interrupt handling in CLIC mode > >>>> target/riscv: Update interrupt return in CLIC mode > >>>> > >>>> default-configs/devices/riscv32-softmmu.mak | 1 + > >>>> default-configs/devices/riscv64-softmmu.mak | 1 + > >>>> hw/intc/Kconfig | 3 + > >>>> hw/intc/meson.build | 1 + > >>>> hw/intc/riscv_clic.c | 836 ++++++++++++++++++++ > >>>> include/hw/intc/riscv_clic.h | 103 +++ > >>>> target/riscv/cpu.h | 9 + > >>>> target/riscv/cpu_bits.h | 32 + > >>>> target/riscv/cpu_helper.c | 117 ++- > >>>> target/riscv/csr.c | 247 +++++- > >>>> target/riscv/op_helper.c | 25 + > >>>> 11 files changed, 1363 insertions(+), 12 deletions(-) > >>>> create mode 100644 hw/intc/riscv_clic.c > >>>> create mode 100644 include/hw/intc/riscv_clic.h > >>>> > >>>> -- > >>>> 2.25.1 > >>>> > >>>>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: michaeljclark@mac.com, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, wxy194768@alibaba-inc.com Subject: Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Date: Thu, 22 Apr 2021 10:21:36 +1000 [thread overview] Message-ID: <CAKmqyKNEEBv4AQAhb-vNxz-DoEp3K3M+eJ2dbsbU_zjkECh=4Q@mail.gmail.com> (raw) In-Reply-To: <89137bb9-4312-ac27-5c63-c0bab0f4c139@c-sky.com> On Tue, Apr 20, 2021 at 5:20 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > > On 2021/4/20 下午2:26, Alistair Francis wrote: > > On Tue, Apr 20, 2021 at 11:45 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >> > >> On 2021/4/20 上午7:30, Alistair Francis wrote: > >>> On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >>>> This patch set gives an implementation of "RISC-V Core-Local Interrupt > >>>> Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where > >>>> you can find the pdf format or the source code. > >>>> > >>>> I take over the job from Michael Clark, who gave the first implementation > >>>> of clic-v0.7 specification. If there is any copyright question, please > >>>> let me know. > >>> You need to make sure you leave all original copyright notices and SoB in place. > >> OK. > >> > >> Is it OK that keep the original copyright notices for new files and > >> your SoB in every patch, Michael? > >> > >>>> Features: > >>>> 1. support four kinds of trigger types. > >>>> 2. Preserve the CSR WARL/WPRI semantics. > >>>> 3. Option to select different modes, such as M/S/U or M/U. > >>>> 4. At most 4096 interrupts. > >>>> 5. At most 1024 apertures. > >>>> > >>>> Todo: > >>>> 1. Encode the interrupt trigger information to exccode. > >>>> 2. Support complete CSR mclicbase when its number is fixed. > >>>> 3. Gave each aperture an independend address. > >>>> > >>>> It have passed my qtest case and freertos test. Welcome to have a try > >>>> for your hardware. > >>> It doesn't seem to be connected to any machine. How are you testing this? > >> There is a machine called SMARTL in my repository[1]. The qtest case > >> is tests/qtest/test-riscv32-clic.c. If it's better, I can upstream the > >> machine together next version. > > I don't really want to add a new hardware device when it isn't > > connected to a machine. It would be great if we could connect it to a > > machine. If not SMARTL maybe we could add it as an option to the virt > > machine? > Currently it is good to connect CLIC to virt machine. I can fix it in > the next version if it is OK for you. The CLIC seems to be gaining traction so I think it makes sense to start to think about connecting it up. We don't want to break backwards compatibility though so make sure it's an option, for example -machine virt,clic=true > > What is SMARTL? Is that a publically available board? > > SMARTL is a fpga evaluation board. We usually use it to debug programs > for XuanTie CPU serials. > It has a 32bit CPU, 1 UART, 4 timers, and the CLIC interrupt > controller. I will give a detailed documentation > when I upstream it. > > There are still many other RISC-V boards, but more complex. I plan to > upstream the XuanTie CPU > and some widely used boards after the P extension and CLIC. I would prefer to add boards that are publicly available, so if there are some that would be great! Alistair > > Zhiwei > > > > > Alistair > > > >> Zhiwei > >> > >> [1]https://github.com/romanheros/qemu, branch: riscv-clic-upstream-rfc > >> > >> > >>> Alistair > >>> > >>>> Any advice is welcomed. Thanks very much. > >>>> > >>>> Zhiwei > >>>> > >>>> [1] specification website: https://github.com/riscv/riscv-fast-interrupt. > >>>> [2] Michael Clark origin work: https://github.com/sifive/riscv-qemu/tree/sifive-clic. > >>>> > >>>> > >>>> LIU Zhiwei (11): > >>>> target/riscv: Add CLIC CSR mintstatus > >>>> target/riscv: Update CSR xintthresh in CLIC mode > >>>> hw/intc: Add CLIC device > >>>> target/riscv: Update CSR xie in CLIC mode > >>>> target/riscv: Update CSR xip in CLIC mode > >>>> target/riscv: Update CSR xtvec in CLIC mode > >>>> target/riscv: Update CSR xtvt in CLIC mode > >>>> target/riscv: Update CSR xnxti in CLIC mode > >>>> target/riscv: Update CSR mclicbase in CLIC mode > >>>> target/riscv: Update interrupt handling in CLIC mode > >>>> target/riscv: Update interrupt return in CLIC mode > >>>> > >>>> default-configs/devices/riscv32-softmmu.mak | 1 + > >>>> default-configs/devices/riscv64-softmmu.mak | 1 + > >>>> hw/intc/Kconfig | 3 + > >>>> hw/intc/meson.build | 1 + > >>>> hw/intc/riscv_clic.c | 836 ++++++++++++++++++++ > >>>> include/hw/intc/riscv_clic.h | 103 +++ > >>>> target/riscv/cpu.h | 9 + > >>>> target/riscv/cpu_bits.h | 32 + > >>>> target/riscv/cpu_helper.c | 117 ++- > >>>> target/riscv/csr.c | 247 +++++- > >>>> target/riscv/op_helper.c | 25 + > >>>> 11 files changed, 1363 insertions(+), 12 deletions(-) > >>>> create mode 100644 hw/intc/riscv_clic.c > >>>> create mode 100644 include/hw/intc/riscv_clic.h > >>>> > >>>> -- > >>>> 2.25.1 > >>>> > >>>>
next prev parent reply other threads:[~2021-04-22 0:24 UTC|newest] Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-09 7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-09 7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-19 23:23 ` Alistair Francis 2021-04-19 23:23 ` Alistair Francis 2021-04-20 0:49 ` LIU Zhiwei 2021-04-20 0:49 ` LIU Zhiwei 2021-07-01 8:45 ` Frank Chang 2021-07-01 8:45 ` Frank Chang 2021-07-01 9:38 ` LIU Zhiwei 2021-07-01 9:38 ` LIU Zhiwei 2021-07-02 5:38 ` Alistair Francis 2021-07-02 5:38 ` Alistair Francis 2021-07-02 6:09 ` LIU Zhiwei 2021-07-02 6:09 ` LIU Zhiwei 2021-07-02 7:16 ` Alistair Francis 2021-07-02 7:16 ` Alistair Francis 2021-09-28 8:10 ` Frank Chang 2021-09-28 8:10 ` Frank Chang 2021-09-29 3:55 ` Alistair Francis 2021-09-29 3:55 ` Alistair Francis 2021-04-09 7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-26 17:23 ` Frank Chang 2021-06-26 17:23 ` Frank Chang 2021-06-27 8:23 ` Frank Chang 2021-06-27 8:23 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-19 23:25 ` Alistair Francis 2021-04-19 23:25 ` Alistair Francis 2021-04-20 0:57 ` LIU Zhiwei 2021-04-20 0:57 ` LIU Zhiwei 2021-04-22 0:16 ` Alistair Francis 2021-04-22 0:16 ` Alistair Francis 2021-06-13 10:10 ` Frank Chang 2021-06-13 10:10 ` Frank Chang 2021-06-16 2:56 ` LIU Zhiwei 2021-06-16 2:56 ` LIU Zhiwei 2021-06-26 12:56 ` Frank Chang 2021-06-26 12:56 ` Frank Chang 2021-06-28 7:15 ` LIU Zhiwei 2021-06-28 7:15 ` LIU Zhiwei 2021-06-28 7:23 ` Frank Chang 2021-06-28 7:23 ` Frank Chang 2021-06-28 7:39 ` LIU Zhiwei 2021-06-28 7:39 ` LIU Zhiwei 2021-06-28 7:49 ` Frank Chang 2021-06-28 7:49 ` Frank Chang 2021-06-28 8:01 ` LIU Zhiwei 2021-06-28 8:01 ` LIU Zhiwei 2021-06-28 8:07 ` Frank Chang 2021-06-28 8:07 ` Frank Chang 2021-06-28 8:11 ` LIU Zhiwei 2021-06-28 8:11 ` LIU Zhiwei 2021-06-28 8:19 ` Frank Chang 2021-06-28 8:19 ` Frank Chang 2021-06-28 8:43 ` LIU Zhiwei 2021-06-28 8:43 ` LIU Zhiwei 2021-06-28 9:11 ` Frank Chang 2021-06-28 9:11 ` Frank Chang 2021-06-26 15:03 ` Frank Chang 2021-06-26 15:03 ` Frank Chang 2021-06-26 15:26 ` Frank Chang 2021-06-26 15:26 ` Frank Chang 2021-06-29 2:52 ` LIU Zhiwei 2021-06-29 2:52 ` LIU Zhiwei 2021-06-29 2:43 ` LIU Zhiwei 2021-06-29 2:43 ` LIU Zhiwei 2021-06-30 5:37 ` Frank Chang 2021-06-30 5:37 ` Frank Chang 2021-06-26 15:20 ` Frank Chang 2021-06-26 15:20 ` Frank Chang 2021-06-29 2:50 ` LIU Zhiwei 2021-06-29 2:50 ` LIU Zhiwei 2021-06-26 17:15 ` Frank Chang 2021-06-26 17:15 ` Frank Chang 2021-06-26 17:19 ` Frank Chang 2021-06-26 17:19 ` Frank Chang 2021-06-28 10:16 ` Frank Chang 2021-06-28 10:16 ` Frank Chang 2021-06-28 12:56 ` LIU Zhiwei 2021-06-28 12:56 ` LIU Zhiwei 2021-06-28 14:30 ` Frank Chang 2021-06-28 14:30 ` Frank Chang 2021-06-28 21:36 ` LIU Zhiwei 2021-06-28 21:36 ` LIU Zhiwei 2021-06-28 10:24 ` Frank Chang 2021-06-28 10:24 ` Frank Chang 2021-06-28 10:48 ` LIU Zhiwei 2021-06-28 10:48 ` LIU Zhiwei 2021-07-13 6:53 ` Frank Chang 2021-07-13 6:53 ` Frank Chang 2021-07-13 6:57 ` Frank Chang 2021-07-13 6:57 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 6:50 ` Frank Chang 2021-06-27 6:50 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 6:45 ` Frank Chang 2021-06-27 6:45 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 8:59 ` Frank Chang 2021-06-27 8:59 ` Frank Chang 2021-07-10 15:04 ` Frank Chang 2021-07-10 15:04 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 8:33 ` Frank Chang 2021-06-27 8:33 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-11 8:15 ` Frank Chang 2021-06-11 8:15 ` Frank Chang 2021-06-11 8:30 ` LIU Zhiwei 2021-06-11 8:30 ` LIU Zhiwei 2021-06-11 8:42 ` Frank Chang 2021-06-11 8:42 ` Frank Chang 2021-06-11 8:56 ` LIU Zhiwei 2021-06-11 8:56 ` LIU Zhiwei 2021-06-11 9:07 ` Frank Chang 2021-06-11 9:07 ` Frank Chang 2021-06-11 9:26 ` LIU Zhiwei 2021-06-11 9:26 ` LIU Zhiwei 2021-06-15 7:45 ` Alistair Francis 2021-06-15 7:45 ` Alistair Francis 2021-06-27 10:07 ` Frank Chang 2021-06-27 10:07 ` Frank Chang 2021-07-10 14:59 ` Frank Chang 2021-07-10 14:59 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-26 15:31 ` Frank Chang 2021-06-26 15:31 ` Frank Chang 2021-06-29 2:54 ` LIU Zhiwei 2021-06-29 2:54 ` LIU Zhiwei 2021-04-09 7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 15:39 ` Frank Chang 2021-06-27 15:39 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 12:08 ` Frank Chang 2021-06-27 12:08 ` Frank Chang 2021-07-13 7:15 ` Frank Chang 2021-07-13 7:15 ` Frank Chang 2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis 2021-04-19 23:30 ` Alistair Francis 2021-04-20 1:44 ` LIU Zhiwei 2021-04-20 1:44 ` LIU Zhiwei 2021-04-20 6:26 ` Alistair Francis 2021-04-20 6:26 ` Alistair Francis 2021-04-20 7:20 ` LIU Zhiwei 2021-04-20 7:20 ` LIU Zhiwei 2021-04-22 0:21 ` Alistair Francis [this message] 2021-04-22 0:21 ` Alistair Francis 2021-06-27 15:55 ` Frank Chang 2021-06-27 15:55 ` Frank Chang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to='CAKmqyKNEEBv4AQAhb-vNxz-DoEp3K3M+eJ2dbsbU_zjkECh=4Q@mail.gmail.com' \ --to=alistair23@gmail.com \ --cc=Alistair.Francis@wdc.com \ --cc=michaeljclark@mac.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=wxy194768@alibaba-inc.com \ --cc=zhiwei_liu@c-sky.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.