From: Alistair Francis <alistair23@gmail.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Date: Fri, 18 Mar 2022 17:38:39 +1000 [thread overview] Message-ID: <CAKmqyKOtbkHh3eeUNegfmy0d6UtbEEHH3KwZ9kBp9AYmn98WyQ@mail.gmail.com> (raw) In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > This adds initial support for the Sdtrig extension via the Trigger Module, > as defined in the RISC-V Debug Specification [1]. > > Only "Address / Data Match" trigger (type 2) is implemented as of now, > which is mainly used for hardware breakpoint and watchpoint. The number > of type 2 triggers implemented is 2, which is the number that we can > find in the SiFive U54/U74 cores. > > [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf > > Changes in v4: > - mention Sdtrig extension in the commit > - rename 'struct trigger_type2_t' to 'type2_trigger_t' > - move riscv_trigger_init() call to riscv_cpu_reset() > > Changes in v3: > - drop riscv_trigger_init(), which will be moved to patch #5 > - add riscv_trigger_init(), moved from patch #1 to this patch > - enable debug feature by default for all CPUs > > Changes in v2: > - new patch: add debug state description > - use 0 instead of GETPC() > - change the config option to 'disabled' by default > > Bin Meng (7): > target/riscv: Add initial support for the Sdtrig extension > target/riscv: machine: Add debug state description > target/riscv: debug: Implement debug related TCGCPUOps > target/riscv: cpu: Add a config option for native debug > target/riscv: csr: Hook debug CSR read/write > target/riscv: cpu: Enable native debug feature > hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Thanks! Applied to riscv-to-apply.next Alistair > > include/hw/core/tcg-cpu-ops.h | 1 + > target/riscv/cpu.h | 9 +- > target/riscv/debug.h | 114 +++++++++ > target/riscv/cpu.c | 12 + > target/riscv/csr.c | 57 +++++ > target/riscv/debug.c | 441 ++++++++++++++++++++++++++++++++++ > target/riscv/machine.c | 32 +++ > target/riscv/meson.build | 1 + > 8 files changed, 666 insertions(+), 1 deletion(-) > create mode 100644 target/riscv/debug.h > create mode 100644 target/riscv/debug.c > > -- > 2.25.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org> Subject: Re: [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Date: Fri, 18 Mar 2022 17:38:39 +1000 [thread overview] Message-ID: <CAKmqyKOtbkHh3eeUNegfmy0d6UtbEEHH3KwZ9kBp9AYmn98WyQ@mail.gmail.com> (raw) In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > This adds initial support for the Sdtrig extension via the Trigger Module, > as defined in the RISC-V Debug Specification [1]. > > Only "Address / Data Match" trigger (type 2) is implemented as of now, > which is mainly used for hardware breakpoint and watchpoint. The number > of type 2 triggers implemented is 2, which is the number that we can > find in the SiFive U54/U74 cores. > > [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf > > Changes in v4: > - mention Sdtrig extension in the commit > - rename 'struct trigger_type2_t' to 'type2_trigger_t' > - move riscv_trigger_init() call to riscv_cpu_reset() > > Changes in v3: > - drop riscv_trigger_init(), which will be moved to patch #5 > - add riscv_trigger_init(), moved from patch #1 to this patch > - enable debug feature by default for all CPUs > > Changes in v2: > - new patch: add debug state description > - use 0 instead of GETPC() > - change the config option to 'disabled' by default > > Bin Meng (7): > target/riscv: Add initial support for the Sdtrig extension > target/riscv: machine: Add debug state description > target/riscv: debug: Implement debug related TCGCPUOps > target/riscv: cpu: Add a config option for native debug > target/riscv: csr: Hook debug CSR read/write > target/riscv: cpu: Enable native debug feature > hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Thanks! Applied to riscv-to-apply.next Alistair > > include/hw/core/tcg-cpu-ops.h | 1 + > target/riscv/cpu.h | 9 +- > target/riscv/debug.h | 114 +++++++++ > target/riscv/cpu.c | 12 + > target/riscv/csr.c | 57 +++++ > target/riscv/debug.c | 441 ++++++++++++++++++++++++++++++++++ > target/riscv/machine.c | 32 +++ > target/riscv/meson.build | 1 + > 8 files changed, 666 insertions(+), 1 deletion(-) > create mode 100644 target/riscv/debug.h > create mode 100644 target/riscv/debug.c > > -- > 2.25.1 > >
next prev parent reply other threads:[~2022-03-18 7:40 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-15 6:55 [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng 2022-03-15 6:55 ` [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension Bin Meng 2022-03-18 2:11 ` Alistair Francis 2022-03-18 2:11 ` Alistair Francis 2022-03-15 6:55 ` [PATCH v4 2/7] target/riscv: machine: Add debug state description Bin Meng 2022-04-20 7:30 ` Alistair Francis 2022-04-20 7:30 ` Alistair Francis 2022-04-20 7:33 ` Bin Meng 2022-04-20 7:33 ` Bin Meng 2022-04-20 9:52 ` Bin Meng 2022-04-20 9:52 ` Bin Meng 2022-04-20 22:45 ` Alistair Francis 2022-04-20 22:45 ` Alistair Francis 2022-04-20 23:46 ` Bin Meng 2022-04-20 23:46 ` Bin Meng 2022-04-21 0:13 ` Alistair Francis 2022-04-21 0:13 ` Alistair Francis 2022-04-21 0:19 ` Bin Meng 2022-04-21 0:19 ` Bin Meng 2022-04-21 15:51 ` Richard Henderson 2022-04-21 15:51 ` Richard Henderson 2022-04-22 1:22 ` Bin Meng 2022-04-22 1:22 ` Bin Meng 2022-03-15 6:55 ` [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng 2022-03-15 6:55 ` [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng 2022-03-15 6:55 ` [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng 2022-03-18 2:14 ` Alistair Francis 2022-03-18 2:14 ` Alistair Francis 2022-03-15 6:55 ` [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature Bin Meng 2022-03-18 2:17 ` Alistair Francis 2022-03-18 2:17 ` Alistair Francis 2022-03-15 6:55 ` [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng 2022-03-15 6:55 ` Bin Meng 2022-03-18 7:38 ` Alistair Francis [this message] 2022-03-18 7:38 ` [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Alistair Francis
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