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From: Matthew Auld <matthew.william.auld@gmail.com>
To: John.C.Harrison@intel.com
Cc: Intel Graphics Development <Intel-GFX@lists.freedesktop.org>,
	 ML dri-devel <DRI-Devel@lists.freedesktop.org>,
	 Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Matthew Auld <matthew.auld@intel.com>,
	 Abdiel Janulgue <abdiel.janulgue@linux.intel.com>,
	 Michal Wajdeczko <michal.wajdeczko@intel.com>,
	Vinay Belgaumkar <vinay.belgaumkar@intel.com>,
	 Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>,
	Matthew Brost <matthew.brost@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: put all guc objects in lmem when available
Date: Wed, 1 Sep 2021 17:12:38 +0100	[thread overview]
Message-ID: <CAM0jSHO7xXFZBwqzw1gnkY47G+DMZUsZEF1_QYWVNa8LLn1cPA@mail.gmail.com> (raw)
In-Reply-To: <20210901022043.2395135-3-John.C.Harrison@Intel.com>

On Wed, 1 Sept 2021 at 03:21, <John.C.Harrison@intel.com> wrote:
>
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> The firmware binary has to be loaded from lmem and the recommendation is
> to put all other objects in there as well. Note that we don't fall back
> to system memory if the allocation in lmem fails because all objects are
> allocated during driver load and if we have issues with lmem at that point
> something is seriously wrong with the system, so no point in trying to
> handle it.
>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_lmem.c  | 26 ++++++++
>  drivers/gpu/drm/i915/gem/i915_gem_lmem.h  |  4 ++
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  9 ++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 13 ++--
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 14 ++++-
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 75 +++++++++++++++++++++--
>  6 files changed, 128 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> index eb345305dc52..034226c5d4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> @@ -103,6 +103,32 @@ __i915_gem_object_create_lmem_with_ps(struct drm_i915_private *i915,
>                                              size, page_size, flags);
>  }
>
> +struct drm_i915_gem_object *
> +i915_gem_object_create_lmem_from_data(struct drm_i915_private *i915,
> +                                     const void *data, size_t size)
> +{
> +       struct drm_i915_gem_object *obj;
> +       void *map;
> +
> +       obj = i915_gem_object_create_lmem(i915,
> +                                         round_up(size, PAGE_SIZE),
> +                                         I915_BO_ALLOC_CONTIGUOUS);

Maybe push the ALLOC_CONTIG into the caller and expose the flags
instead, assuming it's still needed for something GuC related?
pin_map() at least no longer has that constraint.

  reply	other threads:[~2021-09-01 16:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01  2:20 [PATCH 0/7] [CI] Enable GuC submission by default on DG1 John.C.Harrison
2021-09-01  2:20 ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 1/7] drm/i915: Do not define vma on stack John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 2/7] drm/i915/guc: put all guc objects in lmem when available John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01 16:12   ` Matthew Auld [this message]
2021-09-01  2:20 ` [PATCH 3/7] drm/i915/guc: Add DG1 GuC / HuC firmware defs John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 4/7] drm/i915/guc: Enable GuC submission by default on DG1 John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 5/7] Me: Allow relocs on DG1 for CI John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 6/7] Me: Workaround LMEM blow up John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 7/7] Me: Dump GuC log to dmesg on SLPC load failure John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev2) Patchwork
2021-09-01  3:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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