From: John.C.Harrison@Intel.com To: Intel-GFX@Lists.FreeDesktop.Org Cc: DRI-Devel@Lists.FreeDesktop.Org, John Harrison <John.C.Harrison@Intel.com>, Matthew Brost <matthew.brost@intel.com> Subject: [PATCH 0/7] [CI] Enable GuC submission by default on DG1 Date: Tue, 31 Aug 2021 19:20:36 -0700 [thread overview] Message-ID: <20210901022043.2395135-1-John.C.Harrison@Intel.com> (raw) From: John Harrison <John.C.Harrison@Intel.com> Minimum set of patches to enable GuC submission on DG1 and enable it by default. A little difficult to test as IGTs do not work with DG1 due to a bunch of uAPI features being disabled (e.g. relocations, caching memory options, etc...). Hence extra patches at the end to enable some features / add debugging info. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Daniele Ceraolo Spurio (1): drm/i915/guc: put all guc objects in lmem when available Matthew Brost (5): drm/i915/guc: Add DG1 GuC / HuC firmware defs drm/i915/guc: Enable GuC submission by default on DG1 Me: Allow relocs on DG1 for CI Me: Workaround LMEM blow up Me: Dump GuC log to dmesg on SLPC load failure Venkata Sandeep Dhanalakota (1): drm/i915: Do not define vma on stack .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 26 +++++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 13 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 3 + drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 ++- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 90 ++++++++++++++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 + drivers/gpu/drm/i915/i915_gpu_error.c | 99 ++++++++++++++++++- drivers/gpu/drm/i915/i915_gpu_error.h | 3 + 12 files changed, 244 insertions(+), 23 deletions(-) -- 2.25.1
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From: John.C.Harrison@Intel.com To: Intel-GFX@Lists.FreeDesktop.Org Cc: DRI-Devel@Lists.FreeDesktop.Org, John Harrison <John.C.Harrison@Intel.com>, Matthew Brost <matthew.brost@intel.com> Subject: [Intel-gfx] [PATCH 0/7] [CI] Enable GuC submission by default on DG1 Date: Tue, 31 Aug 2021 19:20:36 -0700 [thread overview] Message-ID: <20210901022043.2395135-1-John.C.Harrison@Intel.com> (raw) From: John Harrison <John.C.Harrison@Intel.com> Minimum set of patches to enable GuC submission on DG1 and enable it by default. A little difficult to test as IGTs do not work with DG1 due to a bunch of uAPI features being disabled (e.g. relocations, caching memory options, etc...). Hence extra patches at the end to enable some features / add debugging info. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Daniele Ceraolo Spurio (1): drm/i915/guc: put all guc objects in lmem when available Matthew Brost (5): drm/i915/guc: Add DG1 GuC / HuC firmware defs drm/i915/guc: Enable GuC submission by default on DG1 Me: Allow relocs on DG1 for CI Me: Workaround LMEM blow up Me: Dump GuC log to dmesg on SLPC load failure Venkata Sandeep Dhanalakota (1): drm/i915: Do not define vma on stack .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 26 +++++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 13 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 3 + drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 ++- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 90 ++++++++++++++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 + drivers/gpu/drm/i915/i915_gpu_error.c | 99 ++++++++++++++++++- drivers/gpu/drm/i915/i915_gpu_error.h | 3 + 12 files changed, 244 insertions(+), 23 deletions(-) -- 2.25.1
next reply other threads:[~2021-09-01 2:21 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-01 2:20 John.C.Harrison [this message] 2021-09-01 2:20 ` [Intel-gfx] [PATCH 0/7] [CI] Enable GuC submission by default on DG1 John.C.Harrison 2021-09-01 2:20 ` [PATCH 1/7] drm/i915: Do not define vma on stack John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 2:20 ` [PATCH 2/7] drm/i915/guc: put all guc objects in lmem when available John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 16:12 ` Matthew Auld 2021-09-01 2:20 ` [PATCH 3/7] drm/i915/guc: Add DG1 GuC / HuC firmware defs John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 2:20 ` [PATCH 4/7] drm/i915/guc: Enable GuC submission by default on DG1 John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 2:20 ` [PATCH 5/7] Me: Allow relocs on DG1 for CI John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 2:20 ` [PATCH 6/7] Me: Workaround LMEM blow up John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 2:20 ` [PATCH 7/7] Me: Dump GuC log to dmesg on SLPC load failure John.C.Harrison 2021-09-01 2:20 ` [Intel-gfx] " John.C.Harrison 2021-09-01 2:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev2) Patchwork 2021-09-01 3:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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