* [PATCH] riscv: fix the wrong swap value register
@ 2020-11-13 11:47 Brad Kim
2020-11-13 12:18 ` Lukas Auer
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Brad Kim @ 2020-11-13 11:47 UTC (permalink / raw)
To: u-boot
Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value
Signed-off-by: Brad Kim <brad.kim@semifive.com>
---
arch/riscv/cpu/start.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bbc737ed9a..8589509e01 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -123,7 +123,7 @@ call_board_init_f_0:
* wait for initialization to complete.
*/
la t0, hart_lottery
- li s2, 1
+ li t1, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
#else
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] riscv: fix the wrong swap value register
2020-11-13 11:47 [PATCH] riscv: fix the wrong swap value register Brad Kim
@ 2020-11-13 12:18 ` Lukas Auer
2020-11-19 10:27 ` Leo Liang
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FB2304CBC@ATCPCS16.andestech.com>
2 siblings, 0 replies; 4+ messages in thread
From: Lukas Auer @ 2020-11-13 12:18 UTC (permalink / raw)
To: u-boot
On Fri, 2020-11-13 at 20:47 +0900, Brad Kim wrote:
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
>
> Signed-off-by: Brad Kim <brad.kim@semifive.com>
> ---
> arch/riscv/cpu/start.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Thanks for catching this issue!
Reviewed-by: Lukas Auer <lukas@auer.io>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] riscv: fix the wrong swap value register
2020-11-13 11:47 [PATCH] riscv: fix the wrong swap value register Brad Kim
2020-11-13 12:18 ` Lukas Auer
@ 2020-11-19 10:27 ` Leo Liang
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FB2304CBC@ATCPCS16.andestech.com>
2 siblings, 0 replies; 4+ messages in thread
From: Leo Liang @ 2020-11-19 10:27 UTC (permalink / raw)
To: u-boot
On Fri, Nov 13, 2020 at 08:47:51PM +0900, Brad Kim wrote:
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
>
> Signed-off-by: Brad Kim <brad.kim@semifive.com>
> Reviewed-by: Lukas Auer <lukas@auer.io>
> ---
> arch/riscv/cpu/start.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index bbc737ed9a..8589509e01 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -123,7 +123,7 @@ call_board_init_f_0:
> * wait for initialization to complete.
> */
> la t0, hart_lottery
> - li s2, 1
> + li t1, 1
> amoswap.w s2, t1, 0(t0)
> bnez s2, wait_for_gd_init
> #else
Reviewed-by: Leo Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] riscv: fix the wrong swap value register
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FB2304CBC@ATCPCS16.andestech.com>
@ 2020-11-23 9:19 ` Rick Chen
0 siblings, 0 replies; 4+ messages in thread
From: Rick Chen @ 2020-11-23 9:19 UTC (permalink / raw)
To: u-boot
> From: Brad Kim [mailto:brad.kim at semifive.com]
> Sent: Friday, November 13, 2020 7:48 PM
> To: Rick Jian-Zhi Chen(???); lukas.auer at aisec.fraunhofer.de
> Cc: bmeng.cn at gmail.com; seanga2 at gmail.com; u-boot at lists.denx.de; Brad Kim
> Subject: [PATCH] riscv: fix the wrong swap value register
>
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
>
> Signed-off-by: Brad Kim <brad.kim@semifive.com>
> ---
> arch/riscv/cpu/start.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rick Chen <rick@andestech.com>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index bbc737ed9a..8589509e01 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -123,7 +123,7 @@ call_board_init_f_0:
> * wait for initialization to complete.
> */
> la t0, hart_lottery
> - li s2, 1
> + li t1, 1
> amoswap.w s2, t1, 0(t0)
> bnez s2, wait_for_gd_init
> #else
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-11-23 9:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-13 11:47 [PATCH] riscv: fix the wrong swap value register Brad Kim
2020-11-13 12:18 ` Lukas Auer
2020-11-19 10:27 ` Leo Liang
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FB2304CBC@ATCPCS16.andestech.com>
2020-11-23 9:19 ` Rick Chen
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