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From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
Date: Sat, 20 Jul 2019 17:45:33 +0800	[thread overview]
Message-ID: <DF2A53EE-E978-440A-98EF-76FF9F3DC84C@aosc.io> (raw)
In-Reply-To: <20190720094449.dh53rbxz3mc74qls@flea>



于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard <maxime.ripard@bootlin.com> 写到:
>On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
>> The MMC2 clock slices are currently not defined in V3s CCU driver,
>which
>> makes MMC2 not working.
>>
>> Fix this issue.
>>
>> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> New patch in v4.
>>
>>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> index 4eb68243e310..9c88015d4419 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data
>sun8i_v3s_hw_clks = {
>>  		[CLK_MMC1]		= &mmc1_clk.common.hw,
>>  		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
>>  		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
>> +		[CLK_MMC2]		= &mmc1_clk.common.hw,
>> +		[CLK_MMC2_SAMPLE]	= &mmc1_sample_clk.common.hw,
>> +		[CLK_MMC2_OUTPUT]	= &mmc1_output_clk.common.hw,
>
>You're using the same structures than mmc1, I guess it's a copy and
>paste mistake?

Yes.

>
>Maxime
>
>--
>Maxime Ripard, Bootlin
>Embedded Linux and Kernel engineering
>https://bootlin.com

-- 
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WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: devicetree@vger.kernel.org,
	Linus Walleij <linus.walleij@linaro.org>,
	linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
	linux-gpio@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
	Rob Herring <robh+dt@kernel.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
Date: Sat, 20 Jul 2019 17:45:33 +0800	[thread overview]
Message-ID: <DF2A53EE-E978-440A-98EF-76FF9F3DC84C@aosc.io> (raw)
In-Reply-To: <20190720094449.dh53rbxz3mc74qls@flea>



于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard <maxime.ripard@bootlin.com> 写到:
>On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
>> The MMC2 clock slices are currently not defined in V3s CCU driver,
>which
>> makes MMC2 not working.
>>
>> Fix this issue.
>>
>> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> New patch in v4.
>>
>>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> index 4eb68243e310..9c88015d4419 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data
>sun8i_v3s_hw_clks = {
>>  		[CLK_MMC1]		= &mmc1_clk.common.hw,
>>  		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
>>  		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
>> +		[CLK_MMC2]		= &mmc1_clk.common.hw,
>> +		[CLK_MMC2_SAMPLE]	= &mmc1_sample_clk.common.hw,
>> +		[CLK_MMC2_OUTPUT]	= &mmc1_output_clk.common.hw,
>
>You're using the same structures than mmc1, I guess it's a copy and
>paste mistake?

Yes.

>
>Maxime
>
>--
>Maxime Ripard, Bootlin
>Embedded Linux and Kernel engineering
>https://bootlin.com

-- 
使用 K-9 Mail 发送自我的Android设备。

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  reply	other threads:[~2019-07-20  9:45 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-13  3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-07-13  3:46 ` Icenowy Zheng
2019-07-13  3:46 ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20  9:20   ` Maxime Ripard
2019-07-20  9:20     ` Maxime Ripard
2019-07-20  9:20     ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20  9:43   ` Maxime Ripard
2019-07-20  9:43     ` Maxime Ripard
2019-07-20  9:43     ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20  9:44   ` Maxime Ripard
2019-07-20  9:44     ` Maxime Ripard
2019-07-20  9:44     ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20  9:44   ` Maxime Ripard
2019-07-20  9:44     ` Maxime Ripard
2019-07-20  9:44     ` Maxime Ripard
2019-07-20  9:45     ` Icenowy Zheng [this message]
2019-07-20  9:45       ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20  9:46   ` Maxime Ripard
2019-07-20  9:46     ` Maxime Ripard
2019-07-22 17:07   ` Rob Herring
2019-07-22 17:07     ` Rob Herring
2019-07-22 17:07     ` Rob Herring
2019-07-13  3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20  9:48   ` Maxime Ripard
2019-07-20  9:48     ` Maxime Ripard
2019-07-20  9:48     ` Maxime Ripard
2019-07-20  9:50     ` Icenowy Zheng
2019-07-20  9:50       ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-15 17:03   ` Rob Herring
2019-07-15 17:03     ` Rob Herring
2019-07-15 17:03     ` Rob Herring
2019-07-20 10:13   ` Maxime Ripard
2019-07-20 10:13     ` Maxime Ripard
2019-07-20 10:13     ` Maxime Ripard
2019-07-20 11:39     ` Icenowy Zheng
2019-07-20 11:39       ` Icenowy Zheng
2019-07-20 11:39       ` Icenowy Zheng
2019-07-22 19:29       ` Maxime Ripard
2019-07-22 19:29         ` Maxime Ripard
2019-07-24 13:09         ` Icenowy Zheng
2019-07-24 13:09           ` Icenowy Zheng
2019-07-24 14:14           ` Maxime Ripard
2019-07-24 14:14             ` Maxime Ripard
2019-07-24 14:14             ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-07-13  3:46   ` Icenowy Zheng
2019-07-20 10:12   ` Maxime Ripard
2019-07-20 10:12     ` Maxime Ripard
2019-07-20 10:12     ` Maxime Ripard

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