From: Gabriele Paoloni <gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
To: Lorenzo Pieralisi
<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>,
Shameerali Kolothum Thodi
<shameerali.kolothum.thodi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Cc: "sudeep.holla-5wv7dgnIgG8@public.gmane.org"
<sudeep.holla-5wv7dgnIgG8@public.gmane.org>,
"marc.zyngier-5wv7dgnIgG8@public.gmane.org"
<marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
"linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"will.deacon-5wv7dgnIgG8@public.gmane.org"
<will.deacon-5wv7dgnIgG8@public.gmane.org>,
Linuxarm <linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
"linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"Guohanjun (Hanjun Guo)"
<guohanjun-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
"bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org"
<bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"devel-E0kO6a4B6psdnm+yROfE0A@public.gmane.org"
<devel-E0kO6a4B6psdnm+yROfE0A@public.gmane.org>
Subject: RE: [PATCH v9 4/4] PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3
Date: Tue, 10 Oct 2017 10:19:51 +0000 [thread overview]
Message-ID: <EE11001F9E5DDD47B7634E2F8A612F2E40C5DC1F@FRAEML521-MBX.china.huawei.com> (raw)
In-Reply-To: <20171010100630.GA764@red-moon>
Hi Lorenzo
[...]
> > > Does the presence of "iommu-map" tell you this is an SMMUv3? Could
> it
> > > have a different type of IOMMU? I can't tell from reading
> > > Documentation/devicetree/bindings/pci/pci-iommu.txt.
> >
> > Only if the SMMUv3 driver is loaded and iommu-map binding property
> present,
> > the pcie devices will use SMMU translated iova for MSI doorbell
> addresses.
>
> And the iommu-map property _actually_ points at an OF node with an
> SMMUv3 compatible string - the sheer fact that the SMMUv3 driver
> is compiled in is not sufficient IIUC.
The blacklisted controller can only be present in an SoC that supports
SMMUv3 only.
>From our view checking that SMMUv3 is compiled in and also checking that
the DT contains iommu-map is sufficient to decide to blacklist the controller.
Thanks
Gab
>
> Lorenzo
>
[...]
WARNING: multiple messages have this Message-ID (diff)
From: Gabriele Paoloni <gabriele.paoloni@huawei.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
"Guohanjun (Hanjun Guo)" <guohanjun@huawei.com>,
"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"joro@8bytes.org" <joro@8bytes.org>,
John Garry <john.garry@huawei.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
Linuxarm <linuxarm@huawei.com>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"Wangzhou (B)" <wangzhou1@hisilicon.com>,
"sudeep.holla@arm.com" <sudeep.holla@arm.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robin.murphy@arm.com" <robin.murphy@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devel@acpica.org" <devel@acpica.org>
Subject: RE: [PATCH v9 4/4] PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3
Date: Tue, 10 Oct 2017 10:19:51 +0000 [thread overview]
Message-ID: <EE11001F9E5DDD47B7634E2F8A612F2E40C5DC1F@FRAEML521-MBX.china.huawei.com> (raw)
In-Reply-To: <20171010100630.GA764@red-moon>
Hi Lorenzo
[...]
> > > Does the presence of "iommu-map" tell you this is an SMMUv3? Could
> it
> > > have a different type of IOMMU? I can't tell from reading
> > > Documentation/devicetree/bindings/pci/pci-iommu.txt.
> >
> > Only if the SMMUv3 driver is loaded and iommu-map binding property
> present,
> > the pcie devices will use SMMU translated iova for MSI doorbell
> addresses.
>=20
> And the iommu-map property _actually_ points at an OF node with an
> SMMUv3 compatible string - the sheer fact that the SMMUv3 driver
> is compiled in is not sufficient IIUC.
The blacklisted controller can only be present in an SoC that supports
SMMUv3 only.
>From our view checking that SMMUv3 is compiled in and also checking that
the DT contains iommu-map is sufficient to decide to blacklist the controll=
er.
Thanks
Gab=20
>=20
> Lorenzo
>=20
[...]
WARNING: multiple messages have this Message-ID (diff)
From: gabriele.paoloni@huawei.com (Gabriele Paoloni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 4/4] PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3
Date: Tue, 10 Oct 2017 10:19:51 +0000 [thread overview]
Message-ID: <EE11001F9E5DDD47B7634E2F8A612F2E40C5DC1F@FRAEML521-MBX.china.huawei.com> (raw)
In-Reply-To: <20171010100630.GA764@red-moon>
Hi Lorenzo
[...]
> > > Does the presence of "iommu-map" tell you this is an SMMUv3? Could
> it
> > > have a different type of IOMMU? I can't tell from reading
> > > Documentation/devicetree/bindings/pci/pci-iommu.txt.
> >
> > Only if the SMMUv3 driver is loaded and iommu-map binding property
> present,
> > the pcie devices will use SMMU translated iova for MSI doorbell
> addresses.
>
> And the iommu-map property _actually_ points at an OF node with an
> SMMUv3 compatible string - the sheer fact that the SMMUv3 driver
> is compiled in is not sufficient IIUC.
The blacklisted controller can only be present in an SoC that supports
SMMUv3 only.
>From our view checking that SMMUv3 is compiled in and also checking that
the DT contains iommu-map is sufficient to decide to blacklist the controller.
Thanks
Gab
>
> Lorenzo
>
[...]
next prev parent reply other threads:[~2017-10-10 10:19 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-06 14:04 [PATCH v9 0/4] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Shameer Kolothum
2017-10-06 14:04 ` [Devel] " Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` [PATCH v9 1/4] ACPI/IORT: Add msi address regions reservation helper Shameer Kolothum
2017-10-06 14:04 ` [Devel] " Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Shameer Kolothum
2017-10-06 14:04 ` [Devel] " Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-13 19:23 ` Will Deacon
2017-10-13 19:23 ` [Devel] " Will Deacon
2017-10-13 19:23 ` Will Deacon
2017-10-13 19:23 ` Will Deacon
2017-10-16 16:09 ` Shameerali Kolothum Thodi
2017-10-16 16:09 ` [Devel] " Shameerali Kolothum Thodi
2017-10-16 16:09 ` Shameerali Kolothum Thodi
2017-10-16 16:09 ` Shameerali Kolothum Thodi
[not found] ` <5FC3163CFD30C246ABAA99954A238FA83844672A-WFPaWmAhWqtUuCJht5byYAK1hpo4iccwjNknBlVQO8k@public.gmane.org>
2017-10-18 12:34 ` Robin Murphy
2017-10-18 12:34 ` [Devel] " Robin Murphy
2017-10-18 12:34 ` Robin Murphy
2017-10-18 12:34 ` Robin Murphy
2017-10-18 14:23 ` Shameerali Kolothum Thodi
2017-10-18 14:23 ` [Devel] " Shameerali Kolothum Thodi
2017-10-18 14:23 ` Shameerali Kolothum Thodi
2017-10-18 14:23 ` Shameerali Kolothum Thodi
2017-10-26 10:11 ` Shameerali Kolothum Thodi
2017-10-26 10:11 ` [Devel] " Shameerali Kolothum Thodi
2017-10-26 10:11 ` Shameerali Kolothum Thodi
2017-10-26 10:11 ` Shameerali Kolothum Thodi
2017-11-03 11:35 ` Lorenzo Pieralisi
2017-11-03 11:35 ` [Devel] " Lorenzo Pieralisi
2017-11-03 11:35 ` Lorenzo Pieralisi
2017-11-07 9:37 ` Shameerali Kolothum Thodi
2017-11-07 9:37 ` [Devel] " Shameerali Kolothum Thodi
2017-11-07 9:37 ` Shameerali Kolothum Thodi
2017-11-07 9:37 ` Shameerali Kolothum Thodi
2017-10-06 14:04 ` [PATCH v9 3/4] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Shameer Kolothum
2017-10-06 14:04 ` [Devel] " Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` [PATCH v9 4/4] PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3 Shameer Kolothum
2017-10-06 14:04 ` [Devel] " Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:04 ` Shameer Kolothum
2017-10-06 14:27 ` Gabriele Paoloni
2017-10-06 14:27 ` Gabriele Paoloni
2017-10-06 14:27 ` Gabriele Paoloni
2017-10-09 8:32 ` Zhou Wang
2017-10-09 8:32 ` Zhou Wang
2017-10-09 8:32 ` Zhou Wang
2017-10-09 23:54 ` Bjorn Helgaas
2017-10-09 23:54 ` Bjorn Helgaas
2017-10-09 23:54 ` Bjorn Helgaas
[not found] ` <20171009235452.GP25517-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org>
2017-10-10 0:15 ` Bjorn Helgaas
2017-10-10 0:15 ` Bjorn Helgaas
2017-10-10 0:15 ` Bjorn Helgaas
2017-10-10 9:42 ` Shameerali Kolothum Thodi
2017-10-10 9:42 ` [Devel] " Shameerali Kolothum Thodi
2017-10-10 9:42 ` Shameerali Kolothum Thodi
2017-10-10 9:42 ` Shameerali Kolothum Thodi
2017-10-10 10:06 ` Lorenzo Pieralisi
2017-10-10 10:06 ` [Devel] " Lorenzo Pieralisi
2017-10-10 10:06 ` Lorenzo Pieralisi
2017-10-10 10:06 ` Lorenzo Pieralisi
2017-10-10 10:19 ` Gabriele Paoloni [this message]
2017-10-10 10:19 ` Gabriele Paoloni
2017-10-10 10:19 ` Gabriele Paoloni
2017-10-10 10:51 ` Bjorn Helgaas
2017-10-10 10:51 ` Bjorn Helgaas
2017-10-13 19:22 ` Will Deacon
2017-10-13 19:22 ` [Devel] " Will Deacon
2017-10-13 19:22 ` Will Deacon
2017-10-13 19:22 ` Will Deacon
[not found] ` <20171013192209.GH30572-5wv7dgnIgG8@public.gmane.org>
2017-10-15 7:46 ` Shameerali Kolothum Thodi
2017-10-15 7:46 ` [Devel] " Shameerali Kolothum Thodi
2017-10-15 7:46 ` Shameerali Kolothum Thodi
2017-10-15 7:46 ` Shameerali Kolothum Thodi
2017-10-18 10:51 ` Will Deacon
2017-10-18 10:51 ` [Devel] " Will Deacon
2017-10-18 10:51 ` Will Deacon
2017-10-18 10:51 ` Will Deacon
[not found] ` <20171018105145.GC11669-5wv7dgnIgG8@public.gmane.org>
2017-10-18 12:25 ` Shameerali Kolothum Thodi
2017-10-18 12:25 ` [Devel] " Shameerali Kolothum Thodi
2017-10-18 12:25 ` Shameerali Kolothum Thodi
2017-10-18 12:25 ` Shameerali Kolothum Thodi
2017-10-18 13:45 ` Will Deacon
2017-10-18 13:45 ` [Devel] " Will Deacon
2017-10-18 13:45 ` Will Deacon
2017-10-18 13:45 ` Will Deacon
[not found] ` <20171006140450.89652-1-shameerali.kolothum.thodi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-10-11 11:34 ` [PATCH v9 0/4] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Shameerali Kolothum Thodi
2017-10-11 11:34 ` [Devel] " Shameerali Kolothum Thodi
2017-10-11 11:34 ` Shameerali Kolothum Thodi
2017-10-11 11:34 ` Shameerali Kolothum Thodi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=EE11001F9E5DDD47B7634E2F8A612F2E40C5DC1F@FRAEML521-MBX.china.huawei.com \
--to=gabriele.paoloni-hv44wf8li93qt0dzr+alfa@public.gmane.org \
--cc=bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org \
--cc=devel-E0kO6a4B6psdnm+yROfE0A@public.gmane.org \
--cc=guohanjun-hv44wF8Li93QT0dZR+AlfA@public.gmane.org \
--cc=helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \
--cc=iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org \
--cc=linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
--cc=linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org \
--cc=lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org \
--cc=marc.zyngier-5wv7dgnIgG8@public.gmane.org \
--cc=shameerali.kolothum.thodi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org \
--cc=sudeep.holla-5wv7dgnIgG8@public.gmane.org \
--cc=will.deacon-5wv7dgnIgG8@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.