[PATCH V1 0/2] Disable PTM for endpoint mode

[PATCH V1 0/2] Disable PTM for endpoint mode

[Vidya Sagar]

This patch series contains patches to disable PTM for endpoint mode
as the PCIe compliance tool requires the PTM be disabled for the endpoint
mode.

Vidya Sagar (2):
  PCI: Add PCI_PTM_CAP_RES macro
  PCI: designware-ep: Disable PTM capabilities for EP mode

 .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
 include/uapi/linux/pci_regs.h                 |  1 +
 2 files changed, 19 insertions(+), 1 deletion(-)

-- 
2.17.1

[PATCH V1 1/2] PCI: Add PCI_PTM_CAP_RES macro

[Vidya Sagar]

Add macro defining Responder capable bit in Precision Time Measurement
capability register.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 include/uapi/linux/pci_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 57b8e2ffb1dd..1c3591c8e09e 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1058,6 +1058,7 @@
 /* Precision Time Measurement */
 #define PCI_PTM_CAP			0x04	    /* PTM Capability */
 #define  PCI_PTM_CAP_REQ		0x00000001  /* Requester capable */
+#define  PCI_PTM_CAP_RES		0x00000002  /* Responder capable */
 #define  PCI_PTM_CAP_ROOT		0x00000004  /* Root capable */
 #define  PCI_PTM_GRANULARITY_MASK	0x0000FF00  /* Clock granularity */
 #define PCI_PTM_CTRL			0x08	    /* PTM Control */
-- 
2.17.1

[PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode

[Vidya Sagar]

Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
in the EP mode. The PCIe compliance for the EP mode expects PTM
capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
Hence disable PTM for the EP mode.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7e9529ae3824..dc3057b18f36 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 	struct dw_pcie_ep_func *ep_func;
 	struct device *dev = pci->dev;
 	struct pci_epc *epc = ep->epc;
-	unsigned int offset;
+	unsigned int offset, ptm_cap_base;
 	unsigned int nbars;
 	u8 hdr_type;
 	u8 func_no;
@@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 	}
 
 	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+	ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
 
 	dw_pcie_dbi_ro_wr_en(pci);
 
@@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
 	}
 
+	/*
+	 * PTM responder capability can be disabled only after disabling
+	 * PTM root capability.
+	 */
+	if (ptm_cap_base) {
+		dw_pcie_dbi_ro_wr_en(pci);
+		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
+		reg &= ~PCI_PTM_CAP_ROOT;
+		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
+
+		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
+		reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
+		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
+		dw_pcie_dbi_ro_wr_dis(pci);
+	}
+
 	dw_pcie_setup(pci);
 	dw_pcie_dbi_ro_wr_dis(pci);
 
-- 
2.17.1

Re: [PATCH V1 1/2] PCI: Add PCI_PTM_CAP_RES macro

[Han Jingoo]

On Mon, Sep 19, 2022 Vidya Sagar <vidyas@nvidia.com> wrote:
>
> Add macro defining Responder capable bit in Precision Time Measurement
> capability register.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>

Reviewed-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> ---
>  include/uapi/linux/pci_regs.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..1c3591c8e09e 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1058,6 +1058,7 @@
>  /* Precision Time Measurement */
>  #define PCI_PTM_CAP                    0x04        /* PTM Capability */
>  #define  PCI_PTM_CAP_REQ               0x00000001  /* Requester capable */
> +#define  PCI_PTM_CAP_RES               0x00000002  /* Responder capable */
>  #define  PCI_PTM_CAP_ROOT              0x00000004  /* Root capable */
>  #define  PCI_PTM_GRANULARITY_MASK      0x0000FF00  /* Clock granularity */
>  #define PCI_PTM_CTRL                   0x08        /* PTM Control */
> --
> 2.17.1
>

Re: [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode

[Han Jingoo]

On Mon, Sep 19, 2022, Vidya Sagar <vidyas@nvidia.com> wrote:
>
> Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
> in the EP mode. The PCIe compliance for the EP mode expects PTM
> capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
> Hence disable PTM for the EP mode.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e9529ae3824..dc3057b18f36 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>         struct dw_pcie_ep_func *ep_func;
>         struct device *dev = pci->dev;
>         struct pci_epc *epc = ep->epc;
> -       unsigned int offset;
> +       unsigned int offset, ptm_cap_base;

Is there any reason to mix these 2 variables into 1 line?
If not, please add a new line for ptm_cap_base.

       unsigned int offset;
       unsigned int ptm_cap_base;

Also, it looks ok. When you send a new patch, just add my Acked-by.
Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

>         unsigned int nbars;
>         u8 hdr_type;
>         u8 func_no;
> @@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>         }
>
>         offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
> +       ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
>
>         dw_pcie_dbi_ro_wr_en(pci);
>
> @@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>                         dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
>         }
>
> +       /*
> +        * PTM responder capability can be disabled only after disabling
> +        * PTM root capability.
> +        */
> +       if (ptm_cap_base) {
> +               dw_pcie_dbi_ro_wr_en(pci);
> +               reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +               reg &= ~PCI_PTM_CAP_ROOT;
> +               dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +
> +               reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +               reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
> +               dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +               dw_pcie_dbi_ro_wr_dis(pci);
> +       }
> +
>         dw_pcie_setup(pci);
>         dw_pcie_dbi_ro_wr_dis(pci);
>
> --
> 2.17.1
>

Re: [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode

[Lorenzo Pieralisi]

On Mon, Sep 19, 2022 at 08:03:40PM +0530, Vidya Sagar wrote:
> Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
> in the EP mode. The PCIe compliance for the EP mode expects PTM
> capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
> Hence disable PTM for the EP mode.

"PCIe compliance" - what is this referring to ?

Was this reported to Synopsys ?

Thanks,
Lorenzo

> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e9529ae3824..dc3057b18f36 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  	struct dw_pcie_ep_func *ep_func;
>  	struct device *dev = pci->dev;
>  	struct pci_epc *epc = ep->epc;
> -	unsigned int offset;
> +	unsigned int offset, ptm_cap_base;
>  	unsigned int nbars;
>  	u8 hdr_type;
>  	u8 func_no;
> @@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  	}
>  
>  	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
> +	ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
>  
>  	dw_pcie_dbi_ro_wr_en(pci);
>  
> @@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
>  	}
>  
> +	/*
> +	 * PTM responder capability can be disabled only after disabling
> +	 * PTM root capability.
> +	 */
> +	if (ptm_cap_base) {
> +		dw_pcie_dbi_ro_wr_en(pci);
> +		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +		reg &= ~PCI_PTM_CAP_ROOT;
> +		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +
> +		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +		reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
> +		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +		dw_pcie_dbi_ro_wr_dis(pci);
> +	}
> +
>  	dw_pcie_setup(pci);
>  	dw_pcie_dbi_ro_wr_dis(pci);
>  
> -- 
> 2.17.1
> 

Re: [PATCH V1 0/2] Disable PTM for endpoint mode

[Lorenzo Pieralisi]

On Mon, 19 Sep 2022 20:03:38 +0530, Vidya Sagar wrote:
> This patch series contains patches to disable PTM for endpoint mode
> as the PCIe compliance tool requires the PTM be disabled for the endpoint
> mode.
> 
> Vidya Sagar (2):
>   PCI: Add PCI_PTM_CAP_RES macro
>   PCI: designware-ep: Disable PTM capabilities for EP mode
> 
> [...]

Applied to pci/dwc, thanks!

[1/2] PCI: Add PCI_PTM_CAP_RES macro
      https://git.kernel.org/lpieralisi/pci/c/e32e1e26c409
[2/2] PCI: designware-ep: Disable PTM capabilities for EP mode
      https://git.kernel.org/lpieralisi/pci/c/442ae919e6ca

Thanks,
Lorenzo

Re: [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode

[Han Jingoo]

On Thu, Oct 27, 2022 Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>
> On Mon, Sep 19, 2022 at 08:03:40PM +0530, Vidya Sagar wrote:
> > Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
> > in the EP mode. The PCIe compliance for the EP mode expects PTM
> > capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
> > Hence disable PTM for the EP mode.
>
> "PCIe compliance" - what is this referring to ?

Hi Lorenzo,

You can refer to the following link:
https://pcisig.com/developers/compliance-program

PCIe compliance means 'PCIe Compliance test "Compliance tests allow
for product testing against PCI-SIG test modules". Usually, USB specs
and PCIe specs define compliance tests where product manufacturers
need to pass specific test procedures. For example, in USB cases,
USB.org says that "To qualify for the right to display the certified USB logo
in conjunction with a product, the product must pass USB-IF compliance
testing for product quality."

To Vidiya,
If my understanding is not correct, please let us know what you intended.

>
> Was this reported to Synopsys ?

To Vidiya,
Would you confirm that?

Thank you.

Best regards,
Jingoo Han
>
> Thanks,
> Lorenzo
>
> > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > ---
> >  .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
> >  1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 7e9529ae3824..dc3057b18f36 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> >       struct dw_pcie_ep_func *ep_func;
> >       struct device *dev = pci->dev;
> >       struct pci_epc *epc = ep->epc;
> > -     unsigned int offset;
> > +     unsigned int offset, ptm_cap_base;
> >       unsigned int nbars;
> >       u8 hdr_type;
> >       u8 func_no;
> > @@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> >       }
> >
> >       offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
> > +     ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
> >
> >       dw_pcie_dbi_ro_wr_en(pci);
> >
> > @@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
> >                       dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
> >       }
> >
> > +     /*
> > +      * PTM responder capability can be disabled only after disabling
> > +      * PTM root capability.
> > +      */
> > +     if (ptm_cap_base) {
> > +             dw_pcie_dbi_ro_wr_en(pci);
> > +             reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> > +             reg &= ~PCI_PTM_CAP_ROOT;
> > +             dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> > +
> > +             reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> > +             reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
> > +             dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> > +             dw_pcie_dbi_ro_wr_dis(pci);
> > +     }
> > +
> >       dw_pcie_setup(pci);
> >       dw_pcie_dbi_ro_wr_dis(pci);
> >
> > --
> > 2.17.1
> >

Re: [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode

[Bjorn Helgaas]

On Mon, Sep 19, 2022 at 08:03:40PM +0530, Vidya Sagar wrote:
> Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
> in the EP mode. The PCIe compliance for the EP mode expects PTM
> capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
> Hence disable PTM for the EP mode.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e9529ae3824..dc3057b18f36 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  	struct dw_pcie_ep_func *ep_func;
>  	struct device *dev = pci->dev;
>  	struct pci_epc *epc = ep->epc;
> -	unsigned int offset;
> +	unsigned int offset, ptm_cap_base;
>  	unsigned int nbars;
>  	u8 hdr_type;
>  	u8 func_no;
> @@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  	}
>  
>  	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
> +	ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
>  
>  	dw_pcie_dbi_ro_wr_en(pci);
>  
> @@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
>  	}
>  
> +	/*
> +	 * PTM responder capability can be disabled only after disabling
> +	 * PTM root capability.
> +	 */
> +	if (ptm_cap_base) {
> +		dw_pcie_dbi_ro_wr_en(pci);
> +		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +		reg &= ~PCI_PTM_CAP_ROOT;
> +		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +
> +		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +		reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
> +		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +		dw_pcie_dbi_ro_wr_dis(pci);

Per spec, PTM Responder Capable, PTM Root Capable, and Local Clock
Granularity may only be set for Root Ports, RCRBs, and Switches (PCIe
r6.0, sec 7.9.15.2).

And this is just a matter of making an Endpoint comply with the spec,
i.e., configures the Endpoint so it doesn't advertise that it can be a
PTM Responder, right?

But the Endpoint probably still *can* be a PTM Requester?

> +	}
> +
>  	dw_pcie_setup(pci);
>  	dw_pcie_dbi_ro_wr_dis(pci);
>  
> -- 
> 2.17.1
>