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From: Peter Zijlstra <peterz@infradead.org>
To: "Christoph Müllner" <christophm30@gmail.com>
Cc: Christoph Hellwig <hch@infradead.org>,
	Guo Ren <guoren@kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-csky@vger.kernel.org,
	linux-arch <linux-arch@vger.kernel.org>,
	Guo Ren <guoren@linux.alibaba.com>, Will Deacon <will@kernel.org>,
	Ingo Molnar <mingo@redhat.com>, Waiman Long <longman@redhat.com>,
	Arnd Bergmann <arnd@arndb.de>, Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 7 Apr 2021 18:44:34 +0200	[thread overview]
Message-ID: <YG3hcg32xw/D03P2@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <YG3U677P9QKqFGMY@hirez.programming.kicks-ass.net>

On Wed, Apr 07, 2021 at 05:51:07PM +0200, Peter Zijlstra wrote:
> On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph Müllner wrote:
> > Further, it is not the case that RISC-V has no guarantees at all.
> > It just does not provide a forward progress guarantee for a
> > synchronization implementation,
> > that writes in an endless loop to a memory location while trying to
> > complete an LL/SC
> > loop on the same memory location at the same time.
> 
> Userspace can DoS the kernel that way, see futex.

The longer answer is that this means you cannot share locks (or any
atomic really) across a trust boundary, which is of course exactly what
futex does.

WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org>
To: "Christoph Müllner" <christophm30@gmail.com>
Cc: Christoph Hellwig <hch@infradead.org>,
	Guo Ren <guoren@kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-csky@vger.kernel.org,
	linux-arch <linux-arch@vger.kernel.org>,
	Guo Ren <guoren@linux.alibaba.com>, Will Deacon <will@kernel.org>,
	Ingo Molnar <mingo@redhat.com>, Waiman Long <longman@redhat.com>,
	Arnd Bergmann <arnd@arndb.de>, Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 7 Apr 2021 18:44:34 +0200	[thread overview]
Message-ID: <YG3hcg32xw/D03P2@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <YG3U677P9QKqFGMY@hirez.programming.kicks-ass.net>

On Wed, Apr 07, 2021 at 05:51:07PM +0200, Peter Zijlstra wrote:
> On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph Müllner wrote:
> > Further, it is not the case that RISC-V has no guarantees at all.
> > It just does not provide a forward progress guarantee for a
> > synchronization implementation,
> > that writes in an endless loop to a memory location while trying to
> > complete an LL/SC
> > loop on the same memory location at the same time.
> 
> Userspace can DoS the kernel that way, see futex.

The longer answer is that this means you cannot share locks (or any
atomic really) across a trust boundary, which is of course exactly what
futex does.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-04-07 16:45 UTC|newest]

Thread overview: 126+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-27 18:06 [PATCH v4 0/4] riscv: Add qspinlock/qrwlock guoren
2021-03-27 18:06 ` guoren
2021-03-27 18:06 ` [PATCH v4 1/4] riscv: cmpxchg.h: Cleanup unused code guoren
2021-03-27 18:06   ` guoren
2021-03-27 18:06 ` [PATCH v4 2/4] riscv: cmpxchg.h: Merge macros guoren
2021-03-27 18:06   ` guoren
2021-03-27 21:25   ` Arnd Bergmann
2021-03-27 21:25     ` Arnd Bergmann
2021-03-28  1:50     ` Guo Ren
2021-03-28  1:50       ` Guo Ren
2021-03-27 18:06 ` [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-27 18:06   ` guoren
2021-03-27 18:43   ` Waiman Long
2021-03-27 18:43     ` Waiman Long
2021-03-28  1:48     ` Guo Ren
2021-03-28  1:48       ` Guo Ren
2021-03-29  7:50   ` Peter Zijlstra
2021-03-29  7:50     ` Peter Zijlstra
2021-03-29  9:41     ` Arnd Bergmann
2021-03-29  9:41       ` Arnd Bergmann
2021-03-29 11:16       ` Peter Zijlstra
2021-03-29 11:16         ` Peter Zijlstra
2021-03-29 11:29         ` Peter Zijlstra
2021-03-29 11:29           ` Peter Zijlstra
2021-03-29 12:52           ` Guo Ren
2021-03-29 12:52             ` Guo Ren
2021-03-29 13:56             ` Arnd Bergmann
2021-03-29 13:56               ` Arnd Bergmann
2021-03-30  2:26               ` Guo Ren
2021-03-30  2:26                 ` Guo Ren
2021-03-30  5:51                 ` Anup Patel
2021-03-30  5:51                   ` Anup Patel
2021-03-30  6:26                   ` Guo Ren
2021-03-30  6:26                     ` Guo Ren
2021-03-30  7:11                 ` Arnd Bergmann
2021-03-30  7:11                   ` Arnd Bergmann
2021-03-31  4:18                   ` Guo Ren
2021-03-31  4:18                     ` Guo Ren
2021-03-31  5:33                     ` Paul Campbell
2021-03-31  5:33                       ` Paul Campbell
2021-04-05 16:12                       ` Guo Ren
2021-04-05 16:12                         ` Guo Ren
2021-03-31  6:44                     ` Guo Ren
2021-03-31  6:44                       ` Guo Ren
2021-03-31  7:12                       ` Arnd Bergmann
2021-03-31  7:12                         ` Arnd Bergmann
2021-03-29 11:19     ` Guo Ren
2021-03-29 11:19       ` Guo Ren
2021-03-29 11:26       ` Peter Zijlstra
2021-03-29 11:26         ` Peter Zijlstra
2021-03-29 12:01         ` Guo Ren
2021-03-29 12:01           ` Guo Ren
2021-03-29 12:49           ` Peter Zijlstra
2021-03-29 12:49             ` Peter Zijlstra
2021-03-30  3:13             ` Guo Ren
2021-03-30  3:13               ` Guo Ren
2021-03-30  4:54               ` Anup Patel
2021-03-30  4:54                 ` Anup Patel
2021-03-30  6:27                 ` Guo Ren
2021-03-30  6:27                   ` Guo Ren
2021-03-30  8:31               ` David Laight
2021-03-30  8:31                 ` David Laight
2021-03-30 14:09               ` Waiman Long
2021-03-30 14:09                 ` Waiman Long
2021-03-31 14:47                 ` Guo Ren
2021-03-31 14:47                   ` Guo Ren
2021-04-05 16:45                 ` Guo Ren
2021-04-05 16:45                   ` Guo Ren
2021-03-30 16:08               ` Peter Zijlstra
2021-03-30 16:08                 ` Peter Zijlstra
2021-03-30 22:35                 ` Stafford Horne
2021-03-30 22:35                   ` Stafford Horne
2021-03-31  7:23                   ` Arnd Bergmann
2021-03-31  7:23                     ` Arnd Bergmann
2021-03-31 12:31                     ` Stafford Horne
2021-03-31 12:31                       ` Stafford Horne
2021-03-31 15:10                       ` Guo Ren
2021-03-31 15:10                         ` Guo Ren
2021-04-06  8:51                         ` Stafford Horne
2021-04-06  8:51                           ` Stafford Horne
2021-04-06  3:50                     ` Guo Ren
2021-04-06  3:50                       ` Guo Ren
2021-04-06  8:56                       ` Stafford Horne
2021-04-06  8:56                         ` Stafford Horne
2021-04-07  8:42                         ` Arnd Bergmann
2021-04-07  8:42                           ` Arnd Bergmann
2021-04-07 11:36                           ` Peter Zijlstra
2021-04-07 11:36                             ` Peter Zijlstra
2021-04-07 11:57                             ` Arnd Bergmann
2021-04-07 11:57                               ` Arnd Bergmann
2021-04-07 12:02                             ` Peter Zijlstra
2021-04-07 12:02                               ` Peter Zijlstra
2021-04-05 16:40                 ` Guo Ren
2021-04-05 16:40                   ` Guo Ren
2021-03-31 15:22             ` Guo Ren
2021-03-31 15:22               ` Guo Ren
2021-04-06  7:15               ` Peter Zijlstra
2021-04-06  7:15                 ` Peter Zijlstra
2021-04-07  9:42                 ` Christoph Hellwig
2021-04-07  9:42                   ` Christoph Hellwig
2021-04-07 14:29                   ` Christoph Müllner
2021-04-07 14:29                     ` Christoph Müllner
2021-04-07 14:34                     ` Christoph Hellwig
2021-04-07 14:34                       ` Christoph Hellwig
2021-04-07 15:51                     ` Peter Zijlstra
2021-04-07 15:51                       ` Peter Zijlstra
2021-04-07 16:44                       ` Peter Zijlstra [this message]
2021-04-07 16:44                         ` Peter Zijlstra
2021-04-07 15:52                     ` Peter Zijlstra
2021-04-07 15:52                       ` Peter Zijlstra
2021-04-07 16:54                       ` Peter Zijlstra
2021-04-07 16:54                         ` Peter Zijlstra
2021-04-07 16:00                     ` Peter Zijlstra
2021-04-07 16:00                       ` Peter Zijlstra
2021-04-07 19:50                       ` Christoph Müllner
2021-04-07 19:50                         ` Christoph Müllner
2021-04-06 17:24               ` Boqun Feng
2021-04-06 17:24                 ` Boqun Feng
2021-04-07  9:26                 ` Peter Zijlstra
2021-04-07  9:26                   ` Peter Zijlstra
2021-03-29 12:13         ` Anup Patel
2021-03-29 12:13           ` Anup Patel
2021-03-29 12:54           ` Peter Zijlstra
2021-03-29 12:54             ` Peter Zijlstra
2021-03-27 18:06 ` [PATCH v4 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-27 18:06   ` guoren

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