From: Sam Ravnborg <sam@ravnborg.org> To: Jagan Teki <jagan@amarulasolutions.com> Cc: Inki Dae <inki.dae@samsung.com>, Joonyoung Shim <jy0922.shim@samsung.com>, Seung-Woo Kim <sw0312.kim@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>, Robert Foss <robert.foss@linaro.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Daniel Vetter <daniel.vetter@intel.com>, Marek Vasut <marex@denx.de>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Fabio Estevam <festevam@gmail.com>, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, dri-devel@lists.freedesktop.org, NXP Linux Team <linux-imx@nxp.com>, linux-amarula <linux-amarula@amarulasolutions.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH 16/17] drm: bridge: samsung-dsim: Fix PLL_P offset Date: Sun, 25 Jul 2021 19:48:38 +0200 [thread overview] Message-ID: <YP2j9k5SrZ2/o2/5@ravnborg.org> (raw) In-Reply-To: <20210704090230.26489-17-jagan@amarulasolutions.com> Hi Jagan, On Sun, Jul 04, 2021 at 02:32:29PM +0530, Jagan Teki wrote: > PMS_P offset value in existing driver is not compatible > with i.MX8MM. > > However the i.MX8M Mini Application Reference manual shows > the PMS_P offset is the same in the driver, but the i.MX8MM > downstream driver uses a different one. > > So, handle the PMS_P offset via driver_data and use the > offset value for i.MX8MM from the downstream driver. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> $subject and code speaks of PLL but the changelog says PMS. I think the changelog needs a small update here. Sam > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index 54767cbf231c..0ed218f5eefc 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -184,7 +184,7 @@ > /* DSIM_PLLCTRL */ > #define DSIM_FREQ_BAND(x) ((x) << 24) > #define DSIM_PLL_EN (1 << 23) > -#define DSIM_PLL_P(x) ((x) << 13) > +#define DSIM_PLL_P(x, offset) ((x) << (offset)) > #define DSIM_PLL_M(x) ((x) << 4) > #define DSIM_PLL_S(x) ((x) << 1) > > @@ -259,6 +259,7 @@ struct samsung_dsim_driver_data { > unsigned int max_freq; > unsigned int wait_for_reset; > unsigned int num_bits_resol; > + unsigned int pll_p_offset; > const unsigned int *reg_values; > bool exynos_specific; > }; > @@ -487,6 +488,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .exynos_specific = true, > }; > @@ -500,6 +502,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .exynos_specific = true, > }; > @@ -511,6 +514,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .exynos_specific = true, > }; > @@ -523,6 +527,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5433_reg_values, > .exynos_specific = true, > }; > @@ -535,6 +540,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 1, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5422_reg_values, > .exynos_specific = true, > }; > @@ -547,6 +553,7 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { > .max_freq = 2100, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 14, > .reg_values = imx8mm_dsim_reg_values, > }; > > @@ -662,7 +669,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, > writel(driver_data->reg_values[PLL_TIMER], > dsi->reg_base + driver_data->plltmr_reg); > > - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); > + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | > + DSIM_PLL_M(m) | DSIM_PLL_S(s); > > if (driver_data->has_freqband) { > static const unsigned long freq_bands[] = { > -- > 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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From: Sam Ravnborg <sam@ravnborg.org> To: Jagan Teki <jagan@amarulasolutions.com> Cc: Marek Vasut <marex@denx.de>, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Joonyoung Shim <jy0922.shim@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>, linux-amarula <linux-amarula@amarulasolutions.com>, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Seung-Woo Kim <sw0312.kim@samsung.com>, Robert Foss <robert.foss@linaro.org>, Frieder Schrempf <frieder.schrempf@kontron.de>, Andrzej Hajda <a.hajda@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Daniel Vetter <daniel.vetter@intel.com>, linux-arm-kernel@lists.infradead.org, NXP Linux Team <linux-imx@nxp.com> Subject: Re: [RFC PATCH 16/17] drm: bridge: samsung-dsim: Fix PLL_P offset Date: Sun, 25 Jul 2021 19:48:38 +0200 [thread overview] Message-ID: <YP2j9k5SrZ2/o2/5@ravnborg.org> (raw) In-Reply-To: <20210704090230.26489-17-jagan@amarulasolutions.com> Hi Jagan, On Sun, Jul 04, 2021 at 02:32:29PM +0530, Jagan Teki wrote: > PMS_P offset value in existing driver is not compatible > with i.MX8MM. > > However the i.MX8M Mini Application Reference manual shows > the PMS_P offset is the same in the driver, but the i.MX8MM > downstream driver uses a different one. > > So, handle the PMS_P offset via driver_data and use the > offset value for i.MX8MM from the downstream driver. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> $subject and code speaks of PLL but the changelog says PMS. I think the changelog needs a small update here. Sam > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index 54767cbf231c..0ed218f5eefc 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -184,7 +184,7 @@ > /* DSIM_PLLCTRL */ > #define DSIM_FREQ_BAND(x) ((x) << 24) > #define DSIM_PLL_EN (1 << 23) > -#define DSIM_PLL_P(x) ((x) << 13) > +#define DSIM_PLL_P(x, offset) ((x) << (offset)) > #define DSIM_PLL_M(x) ((x) << 4) > #define DSIM_PLL_S(x) ((x) << 1) > > @@ -259,6 +259,7 @@ struct samsung_dsim_driver_data { > unsigned int max_freq; > unsigned int wait_for_reset; > unsigned int num_bits_resol; > + unsigned int pll_p_offset; > const unsigned int *reg_values; > bool exynos_specific; > }; > @@ -487,6 +488,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .exynos_specific = true, > }; > @@ -500,6 +502,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .exynos_specific = true, > }; > @@ -511,6 +514,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .exynos_specific = true, > }; > @@ -523,6 +527,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5433_reg_values, > .exynos_specific = true, > }; > @@ -535,6 +540,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 1, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5422_reg_values, > .exynos_specific = true, > }; > @@ -547,6 +553,7 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { > .max_freq = 2100, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 14, > .reg_values = imx8mm_dsim_reg_values, > }; > > @@ -662,7 +669,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, > writel(driver_data->reg_values[PLL_TIMER], > dsi->reg_base + driver_data->plltmr_reg); > > - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); > + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | > + DSIM_PLL_M(m) | DSIM_PLL_S(s); > > if (driver_data->has_freqband) { > static const unsigned long freq_bands[] = { > -- > 2.25.1
next prev parent reply other threads:[~2021-07-25 17:50 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-04 9:02 [RFC PATCH 00/17] drm: bridge: Samsung MIPI DSIM bridge Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 01/17] drm/exynos: dsi: Convert to bridge driver Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-25 17:08 ` Sam Ravnborg 2021-07-25 17:08 ` Sam Ravnborg 2021-07-04 9:02 ` [RFC PATCH 02/17] drm/exynos: dsi: Handle drm_device for bridge Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-25 17:09 ` Sam Ravnborg 2021-07-25 17:09 ` Sam Ravnborg 2021-07-04 9:02 ` [RFC PATCH 03/17] drm/exynos: dsi: Use the drm_panel_bridge API Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-05 11:47 ` Marek Szyprowski 2021-07-05 11:47 ` Marek Szyprowski 2021-07-05 11:47 ` Marek Szyprowski 2021-07-05 12:00 ` Jagan Teki 2021-07-05 12:00 ` Jagan Teki 2021-07-05 12:00 ` Jagan Teki 2021-07-05 12:13 ` Marek Szyprowski 2021-07-05 12:13 ` Marek Szyprowski 2021-07-05 12:13 ` Marek Szyprowski 2021-07-05 12:34 ` Jagan Teki 2021-07-05 12:34 ` Jagan Teki 2021-07-05 12:34 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 04/17] drm/exynos: dsi: Create bridge connector for encoder Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 05/17] drm/exynos: dsi: Get the mode from bridge Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-25 17:17 ` Sam Ravnborg 2021-07-25 17:17 ` Sam Ravnborg 2021-07-29 13:20 ` Robert Foss 2021-07-29 13:20 ` Robert Foss 2021-07-29 13:20 ` Robert Foss 2021-07-29 16:50 ` Sam Ravnborg 2021-07-29 16:50 ` Sam Ravnborg 2021-07-04 9:02 ` [RFC PATCH 06/17] drm/exynos: dsi: Handle exynos specifics via driver_data Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-25 17:25 ` Sam Ravnborg 2021-07-25 17:25 ` Sam Ravnborg 2021-07-25 17:31 ` Jagan Teki 2021-07-25 17:31 ` Jagan Teki 2021-07-25 17:31 ` Jagan Teki 2021-08-13 6:50 ` Inki Dae 2021-08-13 6:50 ` Inki Dae 2021-08-13 12:16 ` Laurent Pinchart 2021-08-13 12:16 ` Laurent Pinchart 2021-08-18 6:09 ` Inki Dae 2021-08-18 6:09 ` Inki Dae 2021-07-04 9:02 ` [RFC PATCH 07/17] drm: bridge: Move exynos_drm_dsi into bridges Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 13:26 ` kernel test robot 2021-07-04 9:02 ` [RFC PATCH 08/17] dt-bindings: display: bridge: Add Samsung MIPI DSIM bridge Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-12 15:13 ` Rob Herring 2021-07-12 15:13 ` Rob Herring 2021-07-12 15:13 ` Rob Herring 2021-07-12 15:23 ` Jagan Teki 2021-07-12 15:23 ` Jagan Teki 2021-07-12 15:23 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 09/17] drm: bridge: samsung-dsim: Add module init, exit Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 10/17] drm: bridge: samsung-dsim: Update the of_node for port(s) Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 11/17] drm: bridge: samsung-dsim: Find the possible DSI devices Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 12/17] dt-bindings: display: bridge: samsung,mipi-dsim: Add i.MX8MM support Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 12/17] dt-bindings: display: bridge: samsung, mipi-dsim: " Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-14 22:59 ` [RFC PATCH 12/17] dt-bindings: display: bridge: samsung,mipi-dsim: " Rob Herring 2021-07-14 22:59 ` Rob Herring 2021-07-14 22:59 ` Rob Herring 2021-07-04 9:02 ` [RFC PATCH 13/17] drm: bridge: samsung-dsim: " Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 14/17] drm: bridge: samsung-dsim: Add input_bus_flags Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 15/17] drm: bridge: samsung-dsim: Move DSI init in bridge enable Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` [RFC PATCH 16/17] drm: bridge: samsung-dsim: Fix PLL_P offset Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-25 17:48 ` Sam Ravnborg [this message] 2021-07-25 17:48 ` Sam Ravnborg 2021-07-04 9:02 ` [RFC PATCH 17/17] drm: bridge: samsung-dsim: Add bridge mode_fixup Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-04 9:02 ` Jagan Teki 2021-07-25 17:50 ` Sam Ravnborg 2021-07-25 17:50 ` Sam Ravnborg 2021-07-25 17:05 ` [RFC PATCH 00/17] drm: bridge: Samsung MIPI DSIM bridge Sam Ravnborg 2021-07-25 17:05 ` Sam Ravnborg 2021-07-25 17:13 ` Jagan Teki 2021-07-25 17:13 ` Jagan Teki 2021-07-25 17:13 ` Jagan Teki 2021-10-05 21:43 ` Tim Harvey 2021-10-05 21:43 ` Tim Harvey 2021-12-09 8:36 ` Michael Nazzareno Trimarchi 2021-12-09 8:36 ` Michael Nazzareno Trimarchi 2021-12-09 8:36 ` Michael Nazzareno Trimarchi 2021-12-09 16:40 ` Tim Harvey 2021-12-09 16:40 ` Tim Harvey 2021-12-09 16:40 ` Tim Harvey 2021-12-09 17:09 ` Michael Nazzareno Trimarchi 2021-12-09 17:09 ` Michael Nazzareno Trimarchi 2021-12-09 17:09 ` Michael Nazzareno Trimarchi 2021-12-09 17:57 ` Tim Harvey 2021-12-09 17:57 ` Tim Harvey 2021-12-09 17:57 ` Tim Harvey 2021-12-09 20:24 ` Lucas Stach 2021-12-09 20:24 ` Lucas Stach 2021-12-09 20:24 ` Lucas Stach 2021-12-09 21:24 ` Michael Nazzareno Trimarchi 2021-12-09 21:24 ` Michael Nazzareno Trimarchi 2021-12-09 21:24 ` Michael Nazzareno Trimarchi 2021-12-15 13:34 ` Adam Ford 2021-12-15 13:34 ` Adam Ford 2021-12-15 13:34 ` Adam Ford
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