From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
Date: Wed, 6 May 2020 12:13:44 +0530 [thread overview]
Message-ID: <ae1a105d-65aa-7225-38d3-3839a7d4aa19@arm.com> (raw)
In-Reply-To: <20200505111417.GG19710@willie-the-truck>
On 05/05/2020 04:44 PM, Will Deacon wrote:
> On Sat, May 02, 2020 at 07:03:57PM +0530, Anshuman Khandual wrote:
>> Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX,
>> SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>>
>> Suggested-by: Mark Rutland <mark.rutland@arm.com>
>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++
>> 2 files changed, 21 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index f9e3b9350540..0f34927f52b9 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -790,6 +790,14 @@
>> #define ID_ISAR6_DP_SHIFT 4
>> #define ID_ISAR6_JSCVT_SHIFT 0
>>
>> +#define ID_MMFR4_EVT_SHIFT 28
>> +#define ID_MMFR4_CCIDX_SHIFT 24
>> +#define ID_MMFR4_LSM_SHIFT 20
>> +#define ID_MMFR4_HPDS_SHIFT 16
>> +#define ID_MMFR4_CNP_SHIFT 12
>> +#define ID_MMFR4_XNX_SHIFT 8
>
> Why didn't you add ID_MMFR4_AC2_SHIFT as well?
ID_MMFR4_AC2_SHIFT, which will be the replacement for an existing hard
coded bits shift encoding ('4') is being added via [PATCH 16/16] where
we replace all existing open encodings.
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: Re: [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
Date: Wed, 6 May 2020 12:13:44 +0530 [thread overview]
Message-ID: <ae1a105d-65aa-7225-38d3-3839a7d4aa19@arm.com> (raw)
In-Reply-To: <20200505111417.GG19710@willie-the-truck>
On 05/05/2020 04:44 PM, Will Deacon wrote:
> On Sat, May 02, 2020 at 07:03:57PM +0530, Anshuman Khandual wrote:
>> Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX,
>> SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>>
>> Suggested-by: Mark Rutland <mark.rutland@arm.com>
>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++
>> 2 files changed, 21 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index f9e3b9350540..0f34927f52b9 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -790,6 +790,14 @@
>> #define ID_ISAR6_DP_SHIFT 4
>> #define ID_ISAR6_JSCVT_SHIFT 0
>>
>> +#define ID_MMFR4_EVT_SHIFT 28
>> +#define ID_MMFR4_CCIDX_SHIFT 24
>> +#define ID_MMFR4_LSM_SHIFT 20
>> +#define ID_MMFR4_HPDS_SHIFT 16
>> +#define ID_MMFR4_CNP_SHIFT 12
>> +#define ID_MMFR4_XNX_SHIFT 8
>
> Why didn't you add ID_MMFR4_AC2_SHIFT as well?
ID_MMFR4_AC2_SHIFT, which will be the replacement for an existing hard
coded bits shift encoding ('4') is being added via [PATCH 16/16] where
we replace all existing open encodings.
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next prev parent reply other threads:[~2020-05-06 6:44 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-02 13:33 [PATCH V3 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-04 20:24 ` Will Deacon
2020-05-04 20:24 ` Will Deacon
2020-05-05 6:50 ` Anshuman Khandual
2020-05-05 6:50 ` Anshuman Khandual
2020-05-05 10:42 ` Will Deacon
2020-05-05 10:42 ` Will Deacon
2020-05-08 4:25 ` Anshuman Khandual
2020-05-08 4:25 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-05 11:10 ` Will Deacon
2020-05-05 11:10 ` Will Deacon
2020-05-08 4:59 ` Anshuman Khandual
2020-05-08 4:59 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-05 11:12 ` Will Deacon
2020-05-05 11:12 ` Will Deacon
2020-05-05 11:12 ` Will Deacon
2020-05-05 11:16 ` Mark Rutland
2020-05-05 11:16 ` Mark Rutland
2020-05-05 11:16 ` Mark Rutland
2020-05-05 11:18 ` Mark Rutland
2020-05-05 11:18 ` Mark Rutland
2020-05-05 11:18 ` Mark Rutland
2020-05-05 11:27 ` Will Deacon
2020-05-05 11:27 ` Will Deacon
2020-05-05 11:27 ` Will Deacon
2020-05-05 11:50 ` Mark Rutland
2020-05-05 11:50 ` Mark Rutland
2020-05-05 11:50 ` Mark Rutland
2020-05-05 12:12 ` Will Deacon
2020-05-05 12:12 ` Will Deacon
2020-05-05 12:12 ` Will Deacon
2020-05-05 12:49 ` Mark Rutland
2020-05-05 12:49 ` Mark Rutland
2020-05-05 12:49 ` Mark Rutland
2020-05-08 8:32 ` Anshuman Khandual
2020-05-08 8:32 ` Anshuman Khandual
2020-05-08 8:32 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-03 21:35 ` Suzuki K Poulose
2020-05-03 21:35 ` Suzuki K Poulose
2020-05-03 21:35 ` Suzuki K Poulose
2020-05-02 13:33 ` [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-04 20:33 ` Will Deacon
2020-05-04 20:33 ` Will Deacon
2020-05-04 20:33 ` Will Deacon
2020-05-05 7:01 ` Anshuman Khandual
2020-05-05 7:01 ` Anshuman Khandual
2020-05-05 7:01 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-05 11:14 ` Will Deacon
2020-05-05 11:14 ` Will Deacon
2020-05-06 6:43 ` Anshuman Khandual [this message]
2020-05-06 6:43 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-05 4:54 ` Suzuki K Poulose
2020-05-05 4:54 ` Suzuki K Poulose
2020-05-05 7:06 ` Anshuman Khandual
2020-05-05 7:06 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-05 4:59 ` Suzuki K Poulose
2020-05-05 4:59 ` Suzuki K Poulose
2020-05-06 6:35 ` Anshuman Khandual
2020-05-06 6:35 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-02 13:34 ` Anshuman Khandual
2020-05-05 9:24 ` Suzuki K Poulose
2020-05-05 9:24 ` Suzuki K Poulose
2020-05-06 6:33 ` Anshuman Khandual
2020-05-06 6:33 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-02 13:34 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-02 13:34 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-02 13:34 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-02 13:34 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-05-02 13:34 ` Anshuman Khandual
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