[GIT PULL] RISC-V updates for v5.4-rc1

* [GIT PULL] RISC-V updates for v5.4-rc1
@ 2019-09-16 15:20 ` Paul Walmsley
  0 siblings, 0 replies; 4+ messages in thread
From: Paul Walmsley @ 2019-09-16 15:20 UTC (permalink / raw)
  To: torvalds; +Cc: linux-riscv, linux-kernel

Linus,

The following changes since commit a256f2e329df0773022d28df2c3d206b9aaf1e61:

  RISC-V: Fix FIXMAP area corruption on RV32 systems (2019-08-28 15:30:12 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.4-rc1

for you to fetch changes up to 9ce06497c2722a0f9109e4cc3ce35b7a69617886:

  irqchip/sifive-plic: set max threshold for ignored handlers (2019-09-05 01:59:55 -0700)

----------------------------------------------------------------
RISC-V updates for v5.4-rc1

Add the following new features:

- Generic CPU topology description support for DT-based platforms,
  including ARM64, ARM and RISC-V.

- Sparsemem support

- Perf callchain support

- SiFive PLIC irqchip modifications, in preparation for M-mode Linux

and clean up the code base:

- Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
  flushing, and the RISC-V CPU-local timer code

- Kbuild cleanup from one of the Kbuild maintainers

----------------------------------------------------------------
Atish Patra (4):
      dt-binding: cpu-topology: Move cpu-map to a common binding.
      cpu-topology: Move cpu topology code to common code.
      arm: Use common cpu_topology structure and functions.
      RISC-V: Parse cpu topology during boot.

Bin Meng (1):
      riscv: Using CSR numbers to access CSRs

Christoph Hellwig (7):
      riscv: refactor the IPI code
      riscv: cleanup send_ipi_mask
      riscv: optimize send_ipi_single
      riscv: cleanup riscv_cpuid_to_hartid_mask
      riscv: don't use the rdtime(h) pseudo-instructions
      riscv: move the TLB flush logic out of line
      irqchip/sifive-plic: set max threshold for ignored handlers

Logan Gunthorpe (1):
      RISC-V: Implement sparsemem

Mao Han (3):
      riscv: Add perf callchain support
      riscv: Add support for perf registers sampling
      riscv: Add support for libdw

Masahiro Yamada (1):
      riscv: add arch/riscv/Kbuild

Paul Walmsley (1):
      Merge tag 'common/for-v5.4-rc1/cpu-topology' into for-v5.4-rc1-branch

Sudeep Holla (3):
      Documentation: DT: arm: add support for sockets defining package boundaries
      base: arch_topology: update Kconfig help description
      MAINTAINERS: Add an entry for generic architecture topology

 .../{arm/topology.txt => cpu/cpu-topology.txt}     | 256 +++++++++++------
 MAINTAINERS                                        |   7 +
 arch/arm/include/asm/topology.h                    |  20 --
 arch/arm/kernel/topology.c                         |  60 +---
 arch/arm64/include/asm/topology.h                  |  23 --
 arch/arm64/kernel/topology.c                       | 303 +--------------------
 arch/riscv/Kbuild                                  |   3 +
 arch/riscv/Kconfig                                 |  24 ++
 arch/riscv/Makefile                                |   5 +-
 arch/riscv/include/asm/page.h                      |   2 +
 arch/riscv/include/asm/pgtable.h                   |  13 +
 arch/riscv/include/asm/smp.h                       |   6 -
 arch/riscv/include/asm/sparsemem.h                 |  11 +
 arch/riscv/include/asm/timex.h                     |  44 ++-
 arch/riscv/include/asm/tlbflush.h                  |  38 +--
 arch/riscv/include/uapi/asm/perf_regs.h            |  42 +++
 arch/riscv/kernel/Makefile                         |   4 +-
 arch/riscv/kernel/entry.S                          |   6 +-
 arch/riscv/kernel/fpu.S                            |   8 +-
 arch/riscv/kernel/head.S                           |   2 +-
 arch/riscv/kernel/perf_callchain.c                 |  94 +++++++
 arch/riscv/kernel/perf_regs.c                      |  44 +++
 arch/riscv/kernel/smp.c                            |  60 ++--
 arch/riscv/kernel/smpboot.c                        |   3 +
 arch/riscv/kernel/stacktrace.c                     |   4 +-
 arch/riscv/lib/uaccess.S                           |  12 +-
 arch/riscv/mm/Makefile                             |   3 +
 arch/riscv/mm/cacheflush.c                         |   1 -
 arch/riscv/mm/context.c                            |   7 +-
 arch/riscv/mm/init.c                               |  12 +-
 arch/riscv/mm/tlbflush.c                           |  35 +++
 drivers/base/Kconfig                               |   2 +-
 drivers/base/arch_topology.c                       | 298 ++++++++++++++++++++
 drivers/clocksource/timer-riscv.c                  |  17 +-
 drivers/irqchip/irq-sifive-plic.c                  |  12 +-
 include/linux/arch_topology.h                      |  26 ++
 include/linux/topology.h                           |   1 +
 tools/arch/riscv/include/uapi/asm/perf_regs.h      |  42 +++
 tools/perf/Makefile.config                         |   6 +-
 tools/perf/arch/riscv/Build                        |   1 +
 tools/perf/arch/riscv/Makefile                     |   4 +
 tools/perf/arch/riscv/include/perf_regs.h          |  96 +++++++
 tools/perf/arch/riscv/util/Build                   |   2 +
 tools/perf/arch/riscv/util/dwarf-regs.c            |  72 +++++
 tools/perf/arch/riscv/util/unwind-libdw.c          |  57 ++++
 45 files changed, 1176 insertions(+), 612 deletions(-)
 rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%)
 create mode 100644 arch/riscv/Kbuild
 create mode 100644 arch/riscv/include/asm/sparsemem.h
 create mode 100644 arch/riscv/include/uapi/asm/perf_regs.h
 create mode 100644 arch/riscv/kernel/perf_callchain.c
 create mode 100644 arch/riscv/kernel/perf_regs.c
 create mode 100644 arch/riscv/mm/tlbflush.c
 create mode 100644 tools/arch/riscv/include/uapi/asm/perf_regs.h
 create mode 100644 tools/perf/arch/riscv/Build
 create mode 100644 tools/perf/arch/riscv/Makefile
 create mode 100644 tools/perf/arch/riscv/include/perf_regs.h
 create mode 100644 tools/perf/arch/riscv/util/Build
 create mode 100644 tools/perf/arch/riscv/util/dwarf-regs.c
 create mode 100644 tools/perf/arch/riscv/util/unwind-libdw.c

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