From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v3 07/15] hw/riscv: spike: Remove compile time XLEN checks Date: Mon, 14 Dec 2020 12:34:15 -0800 [thread overview] Message-ID: <cad9da10c3462df78a6fcb8aab19639e6fc8d0f2.1607967113.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1607967113.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> --- hw/riscv/spike.c | 45 ++++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 875f371f0f..3e47e4579d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -43,17 +43,6 @@ #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -/* - * Not like other RISC-V machines that use plain binary bios images, - * keeping ELF files here was intentional because BIN files don't work - * for the Spike machine as HTIF emulation depends on ELF parsing. - */ -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -64,7 +53,7 @@ static const struct MemmapEntry { }; static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; uint64_t addr, size; @@ -115,11 +104,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -254,7 +243,8 @@ static void spike_board_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32_bit(machine)); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", @@ -262,9 +252,22 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SPIKE_DRAM].base, - htif_symbol_callback); + /* + * Not like other RISC-V machines that use plain binary bios images, + * keeping ELF files here was intentional because BIN files don't work + * for the Spike machine as HTIF emulation depends on ELF parsing. + */ + if (riscv_is_32_bit(machine)) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(machine, -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v3 07/15] hw/riscv: spike: Remove compile time XLEN checks Date: Mon, 14 Dec 2020 12:34:15 -0800 [thread overview] Message-ID: <cad9da10c3462df78a6fcb8aab19639e6fc8d0f2.1607967113.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1607967113.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> --- hw/riscv/spike.c | 45 ++++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 875f371f0f..3e47e4579d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -43,17 +43,6 @@ #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -/* - * Not like other RISC-V machines that use plain binary bios images, - * keeping ELF files here was intentional because BIN files don't work - * for the Spike machine as HTIF emulation depends on ELF parsing. - */ -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -64,7 +53,7 @@ static const struct MemmapEntry { }; static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; uint64_t addr, size; @@ -115,11 +104,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -254,7 +243,8 @@ static void spike_board_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32_bit(machine)); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", @@ -262,9 +252,22 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SPIKE_DRAM].base, - htif_symbol_callback); + /* + * Not like other RISC-V machines that use plain binary bios images, + * keeping ELF files here was intentional because BIN files don't work + * for the Spike machine as HTIF emulation depends on ELF parsing. + */ + if (riscv_is_32_bit(machine)) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(machine, -- 2.29.2
next prev parent reply other threads:[~2020-12-14 20:40 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-14 20:33 [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis 2020-12-14 20:33 ` Alistair Francis 2020-12-14 20:33 ` [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis 2020-12-14 20:33 ` Alistair Francis 2020-12-15 9:26 ` Bin Meng 2020-12-15 9:26 ` Bin Meng 2020-12-15 16:44 ` Alistair Francis 2020-12-15 16:44 ` Alistair Francis 2020-12-15 21:25 ` Richard Henderson 2020-12-15 21:25 ` Richard Henderson 2020-12-16 18:16 ` Alistair Francis 2020-12-16 18:16 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 03/15] riscv: spike: Remove target macro conditionals Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 04/15] riscv: virt: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 06/15] hw/riscv: virt: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` Alistair Francis [this message] 2020-12-14 20:34 ` [PATCH v3 07/15] hw/riscv: spike: " Alistair Francis 2020-12-14 20:34 ` [PATCH v3 08/15] hw/riscv: sifive_u: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-15 9:38 ` Bin Meng 2020-12-15 9:38 ` Bin Meng 2020-12-15 15:13 ` Richard Henderson 2020-12-15 15:13 ` Richard Henderson 2020-12-15 17:15 ` Alistair Francis 2020-12-15 17:15 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 13/15] target/riscv: cpu_helper: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 14/15] target/riscv: csr: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-15 13:27 ` Bin Meng 2020-12-15 13:27 ` Bin Meng 2020-12-14 20:34 ` [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis 2020-12-14 20:34 ` Alistair Francis
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