* [Not Xen] Facing issues running guest OS on custom Hypervisor
@ 2018-03-20 20:24 Brijen Raval
2018-04-05 9:12 ` Julien Grall
0 siblings, 1 reply; 2+ messages in thread
From: Brijen Raval @ 2018-03-20 20:24 UTC (permalink / raw)
To: xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 1898 bytes --]
Hello Julien,
As requested I am moving the conversation to email from IRC
To summarize my setup:
1. I am running a custom kernel on QEMU ARM64(without KVM) on my linux
machine
2. I have my custom implementation of Hypervisor
3. I am trying to run the same custom kernel as guest OS on top of my
Hypervisor
- I am able to boot my kernel to shell on QEMU
- I am able to start my guest OS
- From the logs I see that my guest OS finishes booting up, I can see the
$sign for the shell and then it goes into idle state, but I cannot use the
shell
To debug further I enabled tracing in QEMU and printed the exceptions to
understand what state is my guest in
Before I paste some logs here, some more information about my system
IRQ 30 is the physical timer interrupt of my host OS running on QEMU
IRQ 27 is the virtual timer interrupt of my guest OS
I have added some extra logging in QEMU to print out the VTTBR so as to
understand where the exception is coming from
>From 1st Attachment (GIC 1) I observe that every once in a while the phys
timer interrupt occurs (IRQ 30) and its handled by the host VM, and then
after about 10-20 times the virtirq 27 level changes to 1 and back to 0
again and again..this is how its looping currently after boot up
Adding a 2nd attachment with extra logging of traps of exceptions as well.
It just shows 2 different IRQ exceptions taken, one with VTTBR = 0 (IRQ30)
and other with a VTTBR value of the guest (IRQ 27, since the irq 27 level
is changed to 1 just before it..
Any idea what am I missing, and why my guest OS is not handling the pending
interrupt.
Upon receiving the IRQ 27, I do set the HCR_EL2.VI bit to 1 to signal the
guest about a pending virual interrupt but I dont think thats working.
Another thing I noticed that the qemu logging, never shows anything for the
virt_interrupt.
Appreciate any pointers to help debug this.
Thanks,
BR
[-- Attachment #1.2: Type: text/html, Size: 2254 bytes --]
[-- Attachment #2: GIC 1 --]
[-- Type: application/octet-stream, Size: 9999 bytes --]
GIC 1
189206@1521573540.161803:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 30 level changed to 1
189206@1521573540.161831:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573540.161843:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
189206@1521573540.161867:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573540.161873:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
189206@1521573540.161883:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161887:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.161891:gicv3_icc_iar1_read GICv3 ICC_IAR1 read cpu 0x0 value 0x1e
189206@1521573540.161899:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 30 level changed to 0
189206@1521573540.161904:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161908:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.161924:gicv3_icc_eoir_write GICv3 ICC_EOIR1 write cpu 0x0 value 0x1e
189206@1521573540.161929:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161933:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.161937:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161941:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.161964:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161971:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.161982:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161987:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.161992:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.161996:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162001:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162005:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162010:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162014:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162018:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162022:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162027:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162036:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162041:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162045:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162049:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162053:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162060:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162064:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162069:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162073:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162077:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162081:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162096:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 27 level changed to 1
189206@1521573540.162101:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162105:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162131:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162136:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162144:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162148:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162176:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 27 level changed to 0
189206@1521573540.162181:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162185:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162197:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162201:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162211:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162215:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162221:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162225:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162231:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162235:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162239:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162243:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162252:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162256:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162260:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162264:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162269:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162273:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162277:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162281:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162286:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162290:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162298:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162302:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162320:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162324:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162329:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162333:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162338:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162342:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162347:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162351:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162355:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162359:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162364:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162367:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162372:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162376:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162380:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162384:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162391:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162395:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162399:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162403:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162407:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162411:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162425:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 27 level changed to 1
189206@1521573540.162429:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162433:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162458:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162463:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162470:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573540.162474:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573540.162501:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 27 level changed to 0
[-- Attachment #3: GIC 2 --]
[-- Type: application/octet-stream, Size: 9006 bytes --]
189206@1521573541.263046:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 30 level changed to 1
189206@1521573541.263066:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263076:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
189206@1521573541.263096:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263102:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c184c
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263140:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263144:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c184c
189206@1521573541.263151:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263155:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c184c
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263174:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263177:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c184c
189206@1521573541.263189:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263193:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Taking exception 5 [IRQ]
VTTBR is 0...from EL1 to EL1
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000bdd64
...to EL1 PC 0xffffffff00008280 PSTATE 0x3c5
189206@1521573541.263212:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.263216:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
189206@1521573541.263226:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263230:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573541.263234:gicv3_icc_iar1_read GICv3 ICC_IAR1 read cpu 0x0 value 0x1e
189206@1521573541.263243:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 30 level changed to 0
189206@1521573541.263247:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263251:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573541.263269:gicv3_icc_eoir_write GICv3 ICC_EOIR1 write cpu 0x0 value 0x1e
189206@1521573541.263274:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263278:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573541.263282:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263285:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL1 to AArch64 EL1 PC 0xffffffff000bdd64
189206@1521573541.263303:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263307:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c1828
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263335:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263339:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c1828
189206@1521573541.263347:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263351:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
..with ELR 0xffffffff000c1864
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263370:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263374:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c1864
189206@1521573541.263381:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263385:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c1864
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263403:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263407:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c1864
189206@1521573541.263414:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263418:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c1838
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263451:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263457:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c1838
189206@1521573541.263464:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263468:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c1864
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263489:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263492:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c1864
189206@1521573541.263499:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263503:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000005
...with ELR 0xffffffff000c10c0
...to EL2 PC 0x40140c00 PSTATE 0x3c9
189206@1521573541.263521:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263524:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573541.263538:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 27 level changed to 1
189206@1521573541.263543:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263546:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff0000349c
189206@1521573541.263575:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 255
189206@1521573541.263578:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 0
189206@1521573541.273545:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.273549:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff0000349c
189206@1521573541.273578:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.273581:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Taking exception 5 [IRQ]
VTTBR is 281476201840640...from EL1 to EL2
...with ESR 0x16/0x5a000005
...with ELR 0xffffffff0000349c
...to EL2 PC 0x40140c80 PSTATE 0x3c9
189206@1521573541.273599:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.273603:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
189206@1521573541.273630:gicv3_redist_set_irq GICv3 redistributor 0x0 interrupt 27 level changed to 0
189206@1521573541.273635:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.273638:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Exception return from AArch64 EL2 to AArch64 EL1 PC 0xffffffff000c10c0
189206@1521573541.273653:gicv3_cpuif_update GICv3 CPU i/f 0x0 HPPI update: irq 30 group 2 prio 0
189206@1521573541.273657:gicv3_cpuif_set_irqs GICv3 CPU i/f 0x0 HPPI update: setting FIQ 0 IRQ 1
Taking exception 11 [Hypervisor Call]
VTTBR is 0...from EL1 to EL2
...with ESR 0x16/0x5a000006
...with ELR 0xffffffff000c1838
...to EL2 PC 0x40140c00 PSTATE 0x3c9
[-- Attachment #4: Type: text/plain, Size: 157 bytes --]
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [Not Xen] Facing issues running guest OS on custom Hypervisor
2018-03-20 20:24 [Not Xen] Facing issues running guest OS on custom Hypervisor Brijen Raval
@ 2018-04-05 9:12 ` Julien Grall
0 siblings, 0 replies; 2+ messages in thread
From: Julien Grall @ 2018-04-05 9:12 UTC (permalink / raw)
To: Brijen Raval, xen-devel; +Cc: Andre Przywara
On 20/03/18 20:24, Brijen Raval wrote:
> Hello Julien,
Hello,
> As requested I am moving the conversation to email from IRC
>
> To summarize my setup:
>
> 1. I am running a custom kernel on QEMU ARM64(without KVM) on my linux
> machine
> 2. I have my custom implementation of Hypervisor
> 3. I am trying to run the same custom kernel as guest OS on top of my
> Hypervisor
>
> - I am able to boot my kernel to shell on QEMU
> - I am able to start my guest OS
> - From the logs I see that my guest OS finishes booting up, I can see
> the $sign for the shell and then it goes into idle state, but I cannot
> use the shell
>
> To debug further I enabled tracing in QEMU and printed the exceptions to
> understand what state is my guest in
>
> Before I paste some logs here, some more information about my system
>
> IRQ 30 is the physical timer interrupt of my host OS running on QEMU
> IRQ 27 is the virtual timer interrupt of my guest OS
>
> I have added some extra logging in QEMU to print out the VTTBR so as to
> understand where the exception is coming from
>
> From 1st Attachment (GIC 1) I observe that every once in a while the
> phys timer interrupt occurs (IRQ 30) and its handled by the host VM, and
> then after about 10-20 times the virtirq 27 level changes to 1 and back
> to 0 again and again..this is how its looping currently after boot up
>
>
> Adding a 2nd attachment with extra logging of traps of exceptions as
> well. It just shows 2 different IRQ exceptions taken, one with VTTBR = 0
> (IRQ30) and other with a VTTBR value of the guest (IRQ 27, since the irq
> 27 level is changed to 1 just before it..
>
>
> Any idea what am I missing, and why my guest OS is not handling the
> pending interrupt.
>
> Upon receiving the IRQ 27, I do set the HCR_EL2.VI <http://HCR_EL2.VI>
> bit to 1 to signal the guest about a pending virual interrupt but I dont
> think thats working.
HCR_EL2.VI should not be necessary is you are using the GIC HW
virtualization extension. Can you confirm you are using it?
If so, I would recommend to look at the content of the LRs and checking
you effectively have IRQ 27 pending in it.
>
> Another thing I noticed that the qemu logging, never shows anything for
> the virt_interrupt.
What do you mean by "virt_interrupt"? is it a message QEMU is supposed
to print when injecting interrupt to the guest?
Cheers,
--
Julien Grall
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end of thread, other threads:[~2018-04-05 9:13 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
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2018-03-20 20:24 [Not Xen] Facing issues running guest OS on custom Hypervisor Brijen Raval
2018-04-05 9:12 ` Julien Grall
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