* [PATCHv2-RFC 0/2] RFC: standard pci bridge device
@ 2012-02-13 9:15 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:15 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: Kevin Wolf, Isaku Yamahata, Avi Kivity
Here's a new version of the patch. It works for me.
Deep nesting of bridges is supported.
You need a small BIOS patch to support the OSHP method
if you want hotplug to work. I will post this separately.
We'd need a full ACPI driver to make hotplug work for guests
without an SHPC driver (e.g. windows XP).
Management support will also be needed.
One small wrinkle is that the pci_addr property
wants data in a format bus:device.function which is
broken as guests can change bus numbers.
For testing I used the 'addr' property which
encodes slot*8+function#. We probably want to
extend pci_addr in some way (e.g. :device.function ?
Thoughts?).
The SHPC controller supports up to 31 devices
(out of 32 slots) so slot 0 doesn't support hotplug.
Non hot-pluggable devices behind the bridge
don't work currectly (we'll try to unplug them)
so don't do this.
For now I just blocked adding devices in slot 0,
in the future it might be possible to add
a non-hotpluggable device there.
Example:
qemu-system-x86_64 -enable-kvm -m 1G
-drive file=/home/mst/rhel6.qcow2
-netdev
tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
-device pci-bridge,id=bog
-device virtio-net-pci,netdev=foo,bus=bog,addr=8
Hot-unplug currently causes qemu to crash, this
happens without this patch too, so I'm not worried :)
New since v1:
hotplug support
--
MST
Michael S. Tsirkin (2):
shpc: standard hot plug controller
pci: add standard bridge device
Makefile.objs | 3 +-
hw/pci.h | 6 +
hw/pci_bridge_dev.c | 136 +++++++++++
hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/shpc.h | 40 ++++
qemu-common.h | 1 +
6 files changed, 831 insertions(+), 1 deletions(-)
create mode 100644 hw/pci_bridge_dev.c
create mode 100644 hw/shpc.c
create mode 100644 hw/shpc.h
--
1.7.9.111.gf3fb0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Qemu-devel] [PATCHv2-RFC 0/2] RFC: standard pci bridge device
@ 2012-02-13 9:15 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:15 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: Kevin Wolf, Isaku Yamahata, Avi Kivity
Here's a new version of the patch. It works for me.
Deep nesting of bridges is supported.
You need a small BIOS patch to support the OSHP method
if you want hotplug to work. I will post this separately.
We'd need a full ACPI driver to make hotplug work for guests
without an SHPC driver (e.g. windows XP).
Management support will also be needed.
One small wrinkle is that the pci_addr property
wants data in a format bus:device.function which is
broken as guests can change bus numbers.
For testing I used the 'addr' property which
encodes slot*8+function#. We probably want to
extend pci_addr in some way (e.g. :device.function ?
Thoughts?).
The SHPC controller supports up to 31 devices
(out of 32 slots) so slot 0 doesn't support hotplug.
Non hot-pluggable devices behind the bridge
don't work currectly (we'll try to unplug them)
so don't do this.
For now I just blocked adding devices in slot 0,
in the future it might be possible to add
a non-hotpluggable device there.
Example:
qemu-system-x86_64 -enable-kvm -m 1G
-drive file=/home/mst/rhel6.qcow2
-netdev
tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
-device pci-bridge,id=bog
-device virtio-net-pci,netdev=foo,bus=bog,addr=8
Hot-unplug currently causes qemu to crash, this
happens without this patch too, so I'm not worried :)
New since v1:
hotplug support
--
MST
Michael S. Tsirkin (2):
shpc: standard hot plug controller
pci: add standard bridge device
Makefile.objs | 3 +-
hw/pci.h | 6 +
hw/pci_bridge_dev.c | 136 +++++++++++
hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/shpc.h | 40 ++++
qemu-common.h | 1 +
6 files changed, 831 insertions(+), 1 deletions(-)
create mode 100644 hw/pci_bridge_dev.c
create mode 100644 hw/shpc.c
create mode 100644 hw/shpc.h
--
1.7.9.111.gf3fb0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCHv2-RFC 1/2] shpc: standard hot plug controller
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-13 9:15 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:15 UTC (permalink / raw)
To: qemu-devel, kvm
Cc: Wen Congyang, Avi Kivity, Kevin Wolf, Anthony Liguori,
Isaku Yamahata, berrange
This adds support for SHPC interface, as defined by PCI Standard
Hot-Plug Controller and Subsystem Specification, Rev 1.0
http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
Only SHPC intergrated with a PCI-to-PCI bridge is supported,
SHPC integrated with a host bridge would need more work.
All main SHPC features are supported:
- MRL sensor
- Attention button
- Attention indicator
- Power indicator
Wake on hotplug and serr generation are stubbed out but unused
as we don't have interfaces to generate these events ATM.
One issue that isn't completely resolved is that qemu currently
expects an "eject" interface, which SHPC does not provide: it merely
removes the power to device and it's up to the user to remove the device
from slot. This patch works around that by ejecting the device
when power is removed and power LED goes off.
TODO:
- migration support
- fix dependency on pci_internals.h
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
Makefile.objs | 1 +
hw/pci.h | 6 +
hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/shpc.h | 40 ++++
qemu-common.h | 1 +
5 files changed, 694 insertions(+), 0 deletions(-)
create mode 100644 hw/shpc.c
create mode 100644 hw/shpc.h
diff --git a/Makefile.objs b/Makefile.objs
index 391e524..4546477 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
hw-obj-y += fw_cfg.o
hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
hw-obj-$(CONFIG_PCI) += msix.o msi.o
+hw-obj-$(CONFIG_PCI) += shpc.o
hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
hw-obj-y += watchdog.o
diff --git a/hw/pci.h b/hw/pci.h
index 33b0b18..756577e 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -125,6 +125,9 @@ enum {
/* command register SERR bit enabled */
#define QEMU_PCI_CAP_SERR_BITNR 4
QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
+ /* Standard hot plug controller. */
+#define QEMU_PCI_SHPC_BITNR 5
+ QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
@@ -229,6 +232,9 @@ struct PCIDevice {
/* PCI Express */
PCIExpressDevice exp;
+ /* SHPC */
+ SHPCDevice *shpc;
+
/* Location of option rom */
char *romfile;
bool has_rom;
diff --git a/hw/shpc.c b/hw/shpc.c
new file mode 100644
index 0000000..4baec29
--- /dev/null
+++ b/hw/shpc.c
@@ -0,0 +1,646 @@
+#include <strings.h>
+#include <stdint.h>
+#include "range.h"
+#include "shpc.h"
+#include "pci.h"
+#include "pci_internals.h"
+
+/* TODO: model power only and disabled slot states. */
+/* TODO: handle SERR and wakeups */
+/* TODO: consider enabling 66MHz support */
+
+/* TODO: remove fully only on state DISABLED and LED off.
+ * track state to properly record this. */
+
+/* SHPC Working Register Set */
+#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
+#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
+#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
+#define SHPC_NSLOTS 0x0C /* 1 byte */
+#define SHPC_FIRST_DEV 0x0D /* 1 byte */
+#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
+#define SHPC_PHYS_NUM_MAX 0x7ff
+#define SHPC_PHYS_NUM_UP 0x1000
+#define SHPC_PHYS_MRL 0x4000
+#define SHPC_PHYS_BUTTON 0x8000
+#define SHPC_SEC_BUS 0x10 /* 2 bytes */
+#define SHPC_SEC_BUS_33 0x0
+#define SHPC_SEC_BUS_66 0x1 /* Unused */
+#define SHPC_SEC_BUS_MASK 0x7
+#define SHPC_MSI_CTL 0x12 /* 1 byte */
+#define SHPC_PROG_IFC 0x13 /* 1 byte */
+#define SHPC_PROG_IFC_1_0 0x1
+#define SHPC_CMD_CODE 0x14 /* 1 byte */
+#define SHPC_CMD_TRGT 0x15 /* 1 byte */
+#define SHPC_CMD_TRGT_MIN 0x1
+#define SHPC_CMD_TRGT_MAX 0x1f
+#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
+#define SHPC_CMD_STATUS_BUSY 0x1
+#define SHPC_CMD_STATUS_MRL_OPEN 0x2
+#define SHPC_CMD_STATUS_INVALID_CMD 0x4
+#define SHPC_CMD_STATUS_INVALID_MODE 0x8
+#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
+#define SHPC_INT_COMMAND 0x1
+#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
+#define SHPC_SERR_INT 0x20 /* 4 bytes */
+#define SHPC_INT_DIS 0x1
+#define SHPC_SERR_DIS 0x2
+#define SHPC_CMD_INT_DIS 0x4
+#define SHPC_ARB_SERR_DIS 0x8
+#define SHPC_CMD_DETECTED 0x10000
+#define SHPC_ARB_DETECTED 0x20000
+ /* 4 bytes * slot # (start from 0) */
+#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
+ /* 2 bytes */
+#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
+
+/* Same slot state masks are used for command and status registers */
+#define SHPC_SLOT_STATE_MASK 0x03
+#define SHPC_SLOT_STATE_SHIFT \
+ (ffs(SHPC_SLOT_STATE_MASK) - 1)
+
+#define SHPC_STATE_NO 0x0
+#define SHPC_STATE_PWRONLY 0x1
+#define SHPC_STATE_ENABLED 0x2
+#define SHPC_STATE_DISABLED 0x3
+
+#define SHPC_SLOT_PWR_LED_MASK 0xC
+#define SHPC_SLOT_PWR_LED_SHIFT \
+ (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
+#define SHPC_SLOT_ATTN_LED_MASK 0x30
+#define SHPC_SLOT_ATTN_LED_SHIFT \
+ (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
+
+#define SHPC_LED_NO 0x0
+#define SHPC_LED_ON 0x1
+#define SHPC_LED_BLINK 0x2
+#define SHPC_LED_OFF 0x3
+
+#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
+#define SHPC_SLOT_STATUS_BUTTON 0x80
+#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
+#define SHPC_SLOT_STATUS_66 0x200
+#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
+#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
+#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
+#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
+#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
+
+#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
+
+
+ /* 1 byte */
+#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
+ /* 1 byte */
+#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
+#define SHPC_SLOT_EVENT_PRESENCE 0x01
+#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
+#define SHPC_SLOT_EVENT_BUTTON 0x04
+#define SHPC_SLOT_EVENT_MRL 0x08
+#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
+/* Bits below are used for Serr/Int disable only */
+#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
+#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
+
+#define SHPC_MIN_SLOTS 1
+#define SHPC_MAX_SLOTS 31
+#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
+
+/* SHPC Slot identifiers */
+
+/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
+ and give the rest of them physical *and* pci numbers starting from 1, so
+ they match logical numbers. Note: this means that multiple slots must have
+ different chassis number values, to make chassis+physical slot unique.
+ TODO: make this configurable? */
+#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
+#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
+#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
+#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
+#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
+
+static int roundup_pow_of_two(int x)
+{
+ x |= (x >> 1);
+ x |= (x >> 2);
+ x |= (x >> 4);
+ x |= (x >> 8);
+ x |= (x >> 16);
+ return x + 1;
+}
+
+static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
+{
+ uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
+ return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
+}
+
+static void shpc_set_status(SHPCDevice *shpc,
+ int slot, uint8_t value, uint16_t msk)
+{
+ uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
+ pci_word_test_and_clear_mask(status, msk);
+ pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
+}
+
+static void shpc_interrupt_update(PCIDevice *d)
+{
+ SHPCDevice *shpc = d->shpc;
+ int slot;
+ int level = 0;
+ uint32_t serr_int;
+ uint32_t int_locator = 0;
+
+ /* Update interrupt locator register */
+ for (slot = 0; slot < shpc->nslots; ++slot) {
+ uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
+ uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
+ uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
+ if (event & ~disable) {
+ int_locator |= mask;
+ }
+ }
+ serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
+ if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
+ int_locator |= SHPC_INT_COMMAND;
+ }
+ pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
+ level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
+ qemu_set_irq(d->irq[0], level);
+}
+
+static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
+{
+ switch (speed) {
+ case SHPC_SEC_BUS_33:
+ shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
+ shpc->config[SHPC_SEC_BUS] |= speed;
+ break;
+ default:
+ pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
+ SHPC_CMD_STATUS_INVALID_MODE);
+ }
+}
+
+void shpc_reset(PCIDevice *d)
+{
+ SHPCDevice *shpc = d->shpc;
+ int nslots = shpc->nslots;
+ int i;
+ memset(shpc->config, 0, SHPC_SIZEOF(d));
+ pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
+ pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
+ pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
+ pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
+ pci_set_word(shpc->config + SHPC_PHYS_SLOT,
+ SHPC_IDX_TO_PHYSICAL(0) |
+ SHPC_PHYS_NUM_UP |
+ SHPC_PHYS_MRL |
+ SHPC_PHYS_BUTTON);
+ pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
+ SHPC_SERR_DIS |
+ SHPC_CMD_INT_DIS |
+ SHPC_ARB_SERR_DIS);
+ pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
+ pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
+ for (i = 0; i < shpc->nslots; ++i) {
+ pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
+ SHPC_SLOT_EVENT_PRESENCE |
+ SHPC_SLOT_EVENT_ISOLATED_FAULT |
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT |
+ SHPC_SLOT_EVENT_MRL_SERR_DIS |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
+ if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
+ shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
+ shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
+ } else {
+ shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
+ shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
+ }
+ shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
+ }
+ shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
+ shpc_interrupt_update(d);
+}
+
+static void shpc_invalid_command(SHPCDevice *shpc)
+{
+ pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
+ SHPC_CMD_STATUS_INVALID_CMD);
+}
+
+static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
+{
+ int devfn;
+ int pci_slot = SHPC_IDX_TO_PCI(slot);
+ for (devfn = PCI_DEVFN(pci_slot, 0);
+ devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
+ ++devfn) {
+ PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
+ if (affected_dev) {
+ qdev_free(&affected_dev->qdev);
+ }
+ }
+}
+
+static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
+ uint8_t state, uint8_t power, uint8_t attn)
+{
+ uint8_t current_state;
+ int slot = SHPC_LOGICAL_TO_IDX(target);
+ if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
+ shpc_invalid_command(shpc);
+ return;
+ }
+ current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
+ if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
+ shpc_invalid_command(shpc);
+ return;
+ }
+
+ switch (power) {
+ case SHPC_LED_NO:
+ break;
+ default:
+ /* TODO: send event to monitor */
+ shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
+ }
+ switch (attn) {
+ case SHPC_LED_NO:
+ break;
+ default:
+ /* TODO: send event to monitor */
+ shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
+ }
+
+ if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
+ (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
+ shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
+ } else if ((current_state == SHPC_STATE_ENABLED ||
+ current_state == SHPC_STATE_PWRONLY) &&
+ state == SHPC_STATE_DISABLED) {
+ shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
+ power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
+ /* TODO: track what monitor requested. */
+ /* Look at LED to figure out whether it's ok to remove the device. */
+ if (power == SHPC_LED_OFF) {
+ shpc_free_devices_in_slot(shpc, slot);
+ shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_PRESENCE;
+ }
+ }
+}
+
+static void shpc_command(SHPCDevice *shpc)
+{
+ uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
+ uint8_t speed;
+ uint8_t target;
+ uint8_t attn;
+ uint8_t power;
+ uint8_t state;
+ int i;
+
+ /* Clear status from the previous command. */
+ pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
+ SHPC_CMD_STATUS_BUSY |
+ SHPC_CMD_STATUS_MRL_OPEN |
+ SHPC_CMD_STATUS_INVALID_CMD |
+ SHPC_CMD_STATUS_INVALID_MODE);
+ switch (code) {
+ case 0x00 ... 0x3f:
+ target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
+ state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
+ power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
+ attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
+ shpc_slot_command(shpc, target, state, power, attn);
+ break;
+ case 0x40 ... 0x47:
+ speed = code & SHPC_SEC_BUS_MASK;
+ shpc_set_sec_bus_speed(shpc, speed);
+ break;
+ case 0x48:
+ /* Power only all slots */
+ /* first verify no slots are enabled */
+ for (i = 0; i < shpc->nslots; ++i) {
+ state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
+ if (state == SHPC_STATE_ENABLED) {
+ shpc_invalid_command(shpc);
+ goto done;
+ }
+ }
+ for (i = 0; i < shpc->nslots; ++i) {
+ if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
+ } else {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
+ }
+ }
+ break;
+ case 0x49:
+ /* Enable all slots */
+ /* TODO: Spec says this shall fail if some are already enabled.
+ * This doesn't make sense - why not? a spec bug? */
+ for (i = 0; i < shpc->nslots; ++i) {
+ state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
+ if (state == SHPC_STATE_ENABLED) {
+ shpc_invalid_command(shpc);
+ goto done;
+ }
+ }
+ for (i = 0; i < shpc->nslots; ++i) {
+ if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
+ } else {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
+ }
+ }
+ break;
+ default:
+ shpc_invalid_command(shpc);
+ break;
+ }
+done:
+ pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
+}
+
+static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
+{
+ SHPCDevice *shpc = d->shpc;
+ int i;
+ if (addr >= SHPC_SIZEOF(d)) {
+ return;
+ }
+ l = MIN(l, SHPC_SIZEOF(d) - addr);
+
+ /* TODO: code duplicated from pci.c */
+ for (i = 0; i < l; val >>= 8, ++i) {
+ unsigned a = addr + i;
+ uint8_t wmask = shpc->wmask[a];
+ uint8_t w1cmask = shpc->w1cmask[a];
+ assert(!(wmask & w1cmask));
+ shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
+ shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
+ }
+ if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
+ shpc_command(shpc);
+ }
+ shpc_interrupt_update(d);
+}
+
+static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
+{
+ uint64_t val = 0x0;
+ if (addr >= SHPC_SIZEOF(d)) {
+ return val;
+ }
+ l = MIN(l, SHPC_SIZEOF(d) - addr);
+ memcpy(&val, d->shpc->config + addr, l);
+ return val;
+}
+
+/* SHPC Bridge Capability */
+#define SHPC_CAP_LENGTH 0x08
+#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
+#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
+#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
+#define SHPC_CAP_CSP_MASK 0x4
+#define SHPC_CAP_CIP_MASK 0x8
+
+static uint8_t shpc_cap_dword(PCIDevice *d)
+{
+ return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
+}
+
+/* Update dword data capability register */
+static void shpc_cap_update_dword(PCIDevice *d)
+{
+ unsigned data;
+ data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
+ pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
+}
+
+/* Add SHPC capability to the config space for the device. */
+static int shpc_cap_add_config(PCIDevice *d)
+{
+ uint8_t *config;
+ int config_offset;
+ config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
+ 0, SHPC_CAP_LENGTH);
+ if (config_offset < 0) {
+ return config_offset;
+ }
+ config = d->config + config_offset;
+
+ pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
+ pci_set_byte(config + SHPC_CAP_CxP, 0);
+ pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
+ d->shpc->cap = config_offset;
+ /* Make dword select and data writeable. */
+ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
+ pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
+ return 0;
+}
+
+static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+ return shpc_read(opaque, addr, size);
+}
+
+static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ shpc_write(opaque, addr, val, size);
+}
+
+static const MemoryRegionOps shpc_mmio_ops = {
+ .read = shpc_mmio_read,
+ .write = shpc_mmio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
+ * It's easier to suppport all sizes than worry about it. */
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
+ PCIHotplugState hotplug_state)
+{
+ int pci_slot = PCI_SLOT(affected_dev->devfn);
+ uint8_t state;
+ uint8_t led;
+ PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+ SHPCDevice *shpc = d->shpc;
+ int slot = SHPC_PCI_TO_IDX(pci_slot);
+ if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
+ error_report("Unsupported PCI slot %d for standard hotplug "
+ "controller. Valid slots are between %d and %d.",
+ pci_slot, SHPC_IDX_TO_PCI(0),
+ SHPC_IDX_TO_PCI(shpc->nslots) - 1);
+ return -1;
+ }
+ /* Don't send event when device is enabled during qemu machine creation:
+ * it is present on boot, no hotplug event is necessary. We do send an
+ * event when the device is disabled later. */
+ if (hotplug_state == PCI_COLDPLUG_ENABLED) {
+ shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ return 0;
+ }
+ if (hotplug_state == PCI_HOTPLUG_DISABLED) {
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
+ state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
+ led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
+ if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
+ shpc_free_devices_in_slot(shpc, slot);
+ shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_PRESENCE;
+ }
+ } else {
+ /* This could be a cancellation of the previous removal.
+ * We check MRL state to figure out. */
+ if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
+ shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_PRESENCE;
+ } else {
+ /* Press attention button to cancel removal */
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_BUTTON;
+ }
+ }
+ shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
+ shpc_interrupt_update(d);
+ return 0;
+}
+
+/* Initialize the SHPC structure in bridge's BAR. */
+int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
+{
+ int i, ret;
+ int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
+ SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
+ shpc->sec_bus = sec_bus;
+ ret = shpc_cap_add_config(d);
+ if (ret) {
+ g_free(d->shpc);
+ return ret;
+ }
+ if (nslots < SHPC_MIN_SLOTS) {
+ return 0;
+ }
+ if (nslots > SHPC_MAX_SLOTS ||
+ SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
+ /* TODO: report an error mesage that makes sense. */
+ return -EINVAL;
+ }
+ shpc->nslots = nslots;
+ shpc->config = g_malloc0(SHPC_SIZEOF(d));
+ shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
+ shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
+ shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
+
+ shpc_reset(d);
+
+ pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
+
+ pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
+ pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
+ pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
+ pci_set_long(shpc->wmask + SHPC_SERR_INT,
+ SHPC_INT_DIS |
+ SHPC_SERR_DIS |
+ SHPC_CMD_INT_DIS |
+ SHPC_ARB_SERR_DIS);
+ pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
+ SHPC_CMD_DETECTED |
+ SHPC_ARB_DETECTED);
+ for (i = 0; i < nslots; ++i) {
+ pci_set_byte(shpc->wmask +
+ SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
+ SHPC_SLOT_EVENT_PRESENCE |
+ SHPC_SLOT_EVENT_ISOLATED_FAULT |
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT |
+ SHPC_SLOT_EVENT_MRL_SERR_DIS |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
+ pci_set_byte(shpc->w1cmask +
+ SHPC_SLOT_EVENT_LATCH(i),
+ SHPC_SLOT_EVENT_PRESENCE |
+ SHPC_SLOT_EVENT_ISOLATED_FAULT |
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT);
+ }
+
+ /* TODO: init cmask */
+ memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
+ SHPC_SIZEOF(d));
+ shpc_cap_update_dword(d);
+ memory_region_add_subregion(bar, offset, &shpc->mmio);
+ pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
+ return 0;
+}
+
+int shpc_bar_size(PCIDevice *d)
+{
+ return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
+}
+
+void shpc_cleanup(PCIDevice *d)
+{
+ SHPCDevice *shpc = d->shpc;
+ /* TODO: cleanup config space changes? */
+ g_free(shpc->config);
+ g_free(shpc->cmask);
+ g_free(shpc->wmask);
+ g_free(shpc->w1cmask);
+ memory_region_destroy(&shpc->mmio);
+ g_free(shpc);
+}
+
+void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
+{
+ if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
+ return;
+ }
+ fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
+ if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
+ unsigned dword_data;
+ dword_data = pci_get_long(d->shpc->config + d->shpc->cap
+ + SHPC_CAP_DWORD_DATA);
+ shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
+ }
+ /* Update cap dword data in case guest is going to read it. */
+ shpc_cap_update_dword(d);
+}
diff --git a/hw/shpc.h b/hw/shpc.h
new file mode 100644
index 0000000..389b178
--- /dev/null
+++ b/hw/shpc.h
@@ -0,0 +1,40 @@
+#ifndef SHPC_H
+#define SHPC_H
+
+#include "qemu-common.h"
+#include "memory.h"
+
+struct SHPCDevice {
+ /* Capability offset in device's config space */
+ int cap;
+
+ /* # of hot-pluggable slots */
+ int nslots;
+
+ /* SHPC WRS: working register set */
+ uint8_t *config;
+
+ /* Used to enable checks on load. Note that writable bits are
+ * never checked even if set in cmask. */
+ uint8_t *cmask;
+
+ /* Used to implement R/W bytes */
+ uint8_t *wmask;
+
+ /* Used to implement RW1C(Write 1 to Clear) bytes */
+ uint8_t *w1cmask;
+
+ /* MMIO for the SHPC BAR */
+ MemoryRegion mmio;
+
+ /* Bus controlled by this SHPC */
+ PCIBus *sec_bus;
+};
+
+void shpc_reset(PCIDevice *d);
+int shpc_bar_size(PCIDevice *dev);
+int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
+void shpc_cleanup(PCIDevice *dev);
+void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
+
+#endif
diff --git a/qemu-common.h b/qemu-common.h
index 9b997f8..4ff9c95 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
typedef struct EventNotifier EventNotifier;
typedef struct VirtIODevice VirtIODevice;
typedef struct QEMUSGList QEMUSGList;
+typedef struct SHPCDevice SHPCDevice;
typedef uint64_t pcibus_t;
--
1.7.9.111.gf3fb0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PATCHv2-RFC 1/2] shpc: standard hot plug controller
@ 2012-02-13 9:15 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:15 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: Kevin Wolf, Isaku Yamahata, Avi Kivity
This adds support for SHPC interface, as defined by PCI Standard
Hot-Plug Controller and Subsystem Specification, Rev 1.0
http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
Only SHPC intergrated with a PCI-to-PCI bridge is supported,
SHPC integrated with a host bridge would need more work.
All main SHPC features are supported:
- MRL sensor
- Attention button
- Attention indicator
- Power indicator
Wake on hotplug and serr generation are stubbed out but unused
as we don't have interfaces to generate these events ATM.
One issue that isn't completely resolved is that qemu currently
expects an "eject" interface, which SHPC does not provide: it merely
removes the power to device and it's up to the user to remove the device
from slot. This patch works around that by ejecting the device
when power is removed and power LED goes off.
TODO:
- migration support
- fix dependency on pci_internals.h
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
Makefile.objs | 1 +
hw/pci.h | 6 +
hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/shpc.h | 40 ++++
qemu-common.h | 1 +
5 files changed, 694 insertions(+), 0 deletions(-)
create mode 100644 hw/shpc.c
create mode 100644 hw/shpc.h
diff --git a/Makefile.objs b/Makefile.objs
index 391e524..4546477 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
hw-obj-y += fw_cfg.o
hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
hw-obj-$(CONFIG_PCI) += msix.o msi.o
+hw-obj-$(CONFIG_PCI) += shpc.o
hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
hw-obj-y += watchdog.o
diff --git a/hw/pci.h b/hw/pci.h
index 33b0b18..756577e 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -125,6 +125,9 @@ enum {
/* command register SERR bit enabled */
#define QEMU_PCI_CAP_SERR_BITNR 4
QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
+ /* Standard hot plug controller. */
+#define QEMU_PCI_SHPC_BITNR 5
+ QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
@@ -229,6 +232,9 @@ struct PCIDevice {
/* PCI Express */
PCIExpressDevice exp;
+ /* SHPC */
+ SHPCDevice *shpc;
+
/* Location of option rom */
char *romfile;
bool has_rom;
diff --git a/hw/shpc.c b/hw/shpc.c
new file mode 100644
index 0000000..4baec29
--- /dev/null
+++ b/hw/shpc.c
@@ -0,0 +1,646 @@
+#include <strings.h>
+#include <stdint.h>
+#include "range.h"
+#include "shpc.h"
+#include "pci.h"
+#include "pci_internals.h"
+
+/* TODO: model power only and disabled slot states. */
+/* TODO: handle SERR and wakeups */
+/* TODO: consider enabling 66MHz support */
+
+/* TODO: remove fully only on state DISABLED and LED off.
+ * track state to properly record this. */
+
+/* SHPC Working Register Set */
+#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
+#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
+#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
+#define SHPC_NSLOTS 0x0C /* 1 byte */
+#define SHPC_FIRST_DEV 0x0D /* 1 byte */
+#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
+#define SHPC_PHYS_NUM_MAX 0x7ff
+#define SHPC_PHYS_NUM_UP 0x1000
+#define SHPC_PHYS_MRL 0x4000
+#define SHPC_PHYS_BUTTON 0x8000
+#define SHPC_SEC_BUS 0x10 /* 2 bytes */
+#define SHPC_SEC_BUS_33 0x0
+#define SHPC_SEC_BUS_66 0x1 /* Unused */
+#define SHPC_SEC_BUS_MASK 0x7
+#define SHPC_MSI_CTL 0x12 /* 1 byte */
+#define SHPC_PROG_IFC 0x13 /* 1 byte */
+#define SHPC_PROG_IFC_1_0 0x1
+#define SHPC_CMD_CODE 0x14 /* 1 byte */
+#define SHPC_CMD_TRGT 0x15 /* 1 byte */
+#define SHPC_CMD_TRGT_MIN 0x1
+#define SHPC_CMD_TRGT_MAX 0x1f
+#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
+#define SHPC_CMD_STATUS_BUSY 0x1
+#define SHPC_CMD_STATUS_MRL_OPEN 0x2
+#define SHPC_CMD_STATUS_INVALID_CMD 0x4
+#define SHPC_CMD_STATUS_INVALID_MODE 0x8
+#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
+#define SHPC_INT_COMMAND 0x1
+#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
+#define SHPC_SERR_INT 0x20 /* 4 bytes */
+#define SHPC_INT_DIS 0x1
+#define SHPC_SERR_DIS 0x2
+#define SHPC_CMD_INT_DIS 0x4
+#define SHPC_ARB_SERR_DIS 0x8
+#define SHPC_CMD_DETECTED 0x10000
+#define SHPC_ARB_DETECTED 0x20000
+ /* 4 bytes * slot # (start from 0) */
+#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
+ /* 2 bytes */
+#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
+
+/* Same slot state masks are used for command and status registers */
+#define SHPC_SLOT_STATE_MASK 0x03
+#define SHPC_SLOT_STATE_SHIFT \
+ (ffs(SHPC_SLOT_STATE_MASK) - 1)
+
+#define SHPC_STATE_NO 0x0
+#define SHPC_STATE_PWRONLY 0x1
+#define SHPC_STATE_ENABLED 0x2
+#define SHPC_STATE_DISABLED 0x3
+
+#define SHPC_SLOT_PWR_LED_MASK 0xC
+#define SHPC_SLOT_PWR_LED_SHIFT \
+ (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
+#define SHPC_SLOT_ATTN_LED_MASK 0x30
+#define SHPC_SLOT_ATTN_LED_SHIFT \
+ (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
+
+#define SHPC_LED_NO 0x0
+#define SHPC_LED_ON 0x1
+#define SHPC_LED_BLINK 0x2
+#define SHPC_LED_OFF 0x3
+
+#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
+#define SHPC_SLOT_STATUS_BUTTON 0x80
+#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
+#define SHPC_SLOT_STATUS_66 0x200
+#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
+#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
+#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
+#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
+#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
+
+#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
+
+
+ /* 1 byte */
+#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
+ /* 1 byte */
+#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
+#define SHPC_SLOT_EVENT_PRESENCE 0x01
+#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
+#define SHPC_SLOT_EVENT_BUTTON 0x04
+#define SHPC_SLOT_EVENT_MRL 0x08
+#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
+/* Bits below are used for Serr/Int disable only */
+#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
+#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
+
+#define SHPC_MIN_SLOTS 1
+#define SHPC_MAX_SLOTS 31
+#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
+
+/* SHPC Slot identifiers */
+
+/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
+ and give the rest of them physical *and* pci numbers starting from 1, so
+ they match logical numbers. Note: this means that multiple slots must have
+ different chassis number values, to make chassis+physical slot unique.
+ TODO: make this configurable? */
+#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
+#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
+#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
+#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
+#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
+
+static int roundup_pow_of_two(int x)
+{
+ x |= (x >> 1);
+ x |= (x >> 2);
+ x |= (x >> 4);
+ x |= (x >> 8);
+ x |= (x >> 16);
+ return x + 1;
+}
+
+static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
+{
+ uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
+ return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
+}
+
+static void shpc_set_status(SHPCDevice *shpc,
+ int slot, uint8_t value, uint16_t msk)
+{
+ uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
+ pci_word_test_and_clear_mask(status, msk);
+ pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
+}
+
+static void shpc_interrupt_update(PCIDevice *d)
+{
+ SHPCDevice *shpc = d->shpc;
+ int slot;
+ int level = 0;
+ uint32_t serr_int;
+ uint32_t int_locator = 0;
+
+ /* Update interrupt locator register */
+ for (slot = 0; slot < shpc->nslots; ++slot) {
+ uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
+ uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
+ uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
+ if (event & ~disable) {
+ int_locator |= mask;
+ }
+ }
+ serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
+ if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
+ int_locator |= SHPC_INT_COMMAND;
+ }
+ pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
+ level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
+ qemu_set_irq(d->irq[0], level);
+}
+
+static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
+{
+ switch (speed) {
+ case SHPC_SEC_BUS_33:
+ shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
+ shpc->config[SHPC_SEC_BUS] |= speed;
+ break;
+ default:
+ pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
+ SHPC_CMD_STATUS_INVALID_MODE);
+ }
+}
+
+void shpc_reset(PCIDevice *d)
+{
+ SHPCDevice *shpc = d->shpc;
+ int nslots = shpc->nslots;
+ int i;
+ memset(shpc->config, 0, SHPC_SIZEOF(d));
+ pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
+ pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
+ pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
+ pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
+ pci_set_word(shpc->config + SHPC_PHYS_SLOT,
+ SHPC_IDX_TO_PHYSICAL(0) |
+ SHPC_PHYS_NUM_UP |
+ SHPC_PHYS_MRL |
+ SHPC_PHYS_BUTTON);
+ pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
+ SHPC_SERR_DIS |
+ SHPC_CMD_INT_DIS |
+ SHPC_ARB_SERR_DIS);
+ pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
+ pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
+ for (i = 0; i < shpc->nslots; ++i) {
+ pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
+ SHPC_SLOT_EVENT_PRESENCE |
+ SHPC_SLOT_EVENT_ISOLATED_FAULT |
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT |
+ SHPC_SLOT_EVENT_MRL_SERR_DIS |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
+ if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
+ shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
+ shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
+ } else {
+ shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
+ shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
+ }
+ shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
+ }
+ shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
+ shpc_interrupt_update(d);
+}
+
+static void shpc_invalid_command(SHPCDevice *shpc)
+{
+ pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
+ SHPC_CMD_STATUS_INVALID_CMD);
+}
+
+static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
+{
+ int devfn;
+ int pci_slot = SHPC_IDX_TO_PCI(slot);
+ for (devfn = PCI_DEVFN(pci_slot, 0);
+ devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
+ ++devfn) {
+ PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
+ if (affected_dev) {
+ qdev_free(&affected_dev->qdev);
+ }
+ }
+}
+
+static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
+ uint8_t state, uint8_t power, uint8_t attn)
+{
+ uint8_t current_state;
+ int slot = SHPC_LOGICAL_TO_IDX(target);
+ if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
+ shpc_invalid_command(shpc);
+ return;
+ }
+ current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
+ if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
+ shpc_invalid_command(shpc);
+ return;
+ }
+
+ switch (power) {
+ case SHPC_LED_NO:
+ break;
+ default:
+ /* TODO: send event to monitor */
+ shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
+ }
+ switch (attn) {
+ case SHPC_LED_NO:
+ break;
+ default:
+ /* TODO: send event to monitor */
+ shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
+ }
+
+ if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
+ (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
+ shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
+ } else if ((current_state == SHPC_STATE_ENABLED ||
+ current_state == SHPC_STATE_PWRONLY) &&
+ state == SHPC_STATE_DISABLED) {
+ shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
+ power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
+ /* TODO: track what monitor requested. */
+ /* Look at LED to figure out whether it's ok to remove the device. */
+ if (power == SHPC_LED_OFF) {
+ shpc_free_devices_in_slot(shpc, slot);
+ shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_PRESENCE;
+ }
+ }
+}
+
+static void shpc_command(SHPCDevice *shpc)
+{
+ uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
+ uint8_t speed;
+ uint8_t target;
+ uint8_t attn;
+ uint8_t power;
+ uint8_t state;
+ int i;
+
+ /* Clear status from the previous command. */
+ pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
+ SHPC_CMD_STATUS_BUSY |
+ SHPC_CMD_STATUS_MRL_OPEN |
+ SHPC_CMD_STATUS_INVALID_CMD |
+ SHPC_CMD_STATUS_INVALID_MODE);
+ switch (code) {
+ case 0x00 ... 0x3f:
+ target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
+ state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
+ power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
+ attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
+ shpc_slot_command(shpc, target, state, power, attn);
+ break;
+ case 0x40 ... 0x47:
+ speed = code & SHPC_SEC_BUS_MASK;
+ shpc_set_sec_bus_speed(shpc, speed);
+ break;
+ case 0x48:
+ /* Power only all slots */
+ /* first verify no slots are enabled */
+ for (i = 0; i < shpc->nslots; ++i) {
+ state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
+ if (state == SHPC_STATE_ENABLED) {
+ shpc_invalid_command(shpc);
+ goto done;
+ }
+ }
+ for (i = 0; i < shpc->nslots; ++i) {
+ if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
+ } else {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
+ }
+ }
+ break;
+ case 0x49:
+ /* Enable all slots */
+ /* TODO: Spec says this shall fail if some are already enabled.
+ * This doesn't make sense - why not? a spec bug? */
+ for (i = 0; i < shpc->nslots; ++i) {
+ state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
+ if (state == SHPC_STATE_ENABLED) {
+ shpc_invalid_command(shpc);
+ goto done;
+ }
+ }
+ for (i = 0; i < shpc->nslots; ++i) {
+ if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
+ } else {
+ shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
+ SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
+ }
+ }
+ break;
+ default:
+ shpc_invalid_command(shpc);
+ break;
+ }
+done:
+ pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
+}
+
+static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
+{
+ SHPCDevice *shpc = d->shpc;
+ int i;
+ if (addr >= SHPC_SIZEOF(d)) {
+ return;
+ }
+ l = MIN(l, SHPC_SIZEOF(d) - addr);
+
+ /* TODO: code duplicated from pci.c */
+ for (i = 0; i < l; val >>= 8, ++i) {
+ unsigned a = addr + i;
+ uint8_t wmask = shpc->wmask[a];
+ uint8_t w1cmask = shpc->w1cmask[a];
+ assert(!(wmask & w1cmask));
+ shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
+ shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
+ }
+ if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
+ shpc_command(shpc);
+ }
+ shpc_interrupt_update(d);
+}
+
+static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
+{
+ uint64_t val = 0x0;
+ if (addr >= SHPC_SIZEOF(d)) {
+ return val;
+ }
+ l = MIN(l, SHPC_SIZEOF(d) - addr);
+ memcpy(&val, d->shpc->config + addr, l);
+ return val;
+}
+
+/* SHPC Bridge Capability */
+#define SHPC_CAP_LENGTH 0x08
+#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
+#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
+#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
+#define SHPC_CAP_CSP_MASK 0x4
+#define SHPC_CAP_CIP_MASK 0x8
+
+static uint8_t shpc_cap_dword(PCIDevice *d)
+{
+ return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
+}
+
+/* Update dword data capability register */
+static void shpc_cap_update_dword(PCIDevice *d)
+{
+ unsigned data;
+ data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
+ pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
+}
+
+/* Add SHPC capability to the config space for the device. */
+static int shpc_cap_add_config(PCIDevice *d)
+{
+ uint8_t *config;
+ int config_offset;
+ config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
+ 0, SHPC_CAP_LENGTH);
+ if (config_offset < 0) {
+ return config_offset;
+ }
+ config = d->config + config_offset;
+
+ pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
+ pci_set_byte(config + SHPC_CAP_CxP, 0);
+ pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
+ d->shpc->cap = config_offset;
+ /* Make dword select and data writeable. */
+ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
+ pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
+ return 0;
+}
+
+static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+ return shpc_read(opaque, addr, size);
+}
+
+static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ shpc_write(opaque, addr, val, size);
+}
+
+static const MemoryRegionOps shpc_mmio_ops = {
+ .read = shpc_mmio_read,
+ .write = shpc_mmio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
+ * It's easier to suppport all sizes than worry about it. */
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
+ PCIHotplugState hotplug_state)
+{
+ int pci_slot = PCI_SLOT(affected_dev->devfn);
+ uint8_t state;
+ uint8_t led;
+ PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+ SHPCDevice *shpc = d->shpc;
+ int slot = SHPC_PCI_TO_IDX(pci_slot);
+ if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
+ error_report("Unsupported PCI slot %d for standard hotplug "
+ "controller. Valid slots are between %d and %d.",
+ pci_slot, SHPC_IDX_TO_PCI(0),
+ SHPC_IDX_TO_PCI(shpc->nslots) - 1);
+ return -1;
+ }
+ /* Don't send event when device is enabled during qemu machine creation:
+ * it is present on boot, no hotplug event is necessary. We do send an
+ * event when the device is disabled later. */
+ if (hotplug_state == PCI_COLDPLUG_ENABLED) {
+ shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ return 0;
+ }
+ if (hotplug_state == PCI_HOTPLUG_DISABLED) {
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
+ state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
+ led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
+ if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
+ shpc_free_devices_in_slot(shpc, slot);
+ shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_PRESENCE;
+ }
+ } else {
+ /* This could be a cancellation of the previous removal.
+ * We check MRL state to figure out. */
+ if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
+ shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
+ shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
+ SHPC_SLOT_STATUS_PRSNT_MASK);
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_PRESENCE;
+ } else {
+ /* Press attention button to cancel removal */
+ shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
+ SHPC_SLOT_EVENT_BUTTON;
+ }
+ }
+ shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
+ shpc_interrupt_update(d);
+ return 0;
+}
+
+/* Initialize the SHPC structure in bridge's BAR. */
+int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
+{
+ int i, ret;
+ int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
+ SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
+ shpc->sec_bus = sec_bus;
+ ret = shpc_cap_add_config(d);
+ if (ret) {
+ g_free(d->shpc);
+ return ret;
+ }
+ if (nslots < SHPC_MIN_SLOTS) {
+ return 0;
+ }
+ if (nslots > SHPC_MAX_SLOTS ||
+ SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
+ /* TODO: report an error mesage that makes sense. */
+ return -EINVAL;
+ }
+ shpc->nslots = nslots;
+ shpc->config = g_malloc0(SHPC_SIZEOF(d));
+ shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
+ shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
+ shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
+
+ shpc_reset(d);
+
+ pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
+
+ pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
+ pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
+ pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
+ pci_set_long(shpc->wmask + SHPC_SERR_INT,
+ SHPC_INT_DIS |
+ SHPC_SERR_DIS |
+ SHPC_CMD_INT_DIS |
+ SHPC_ARB_SERR_DIS);
+ pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
+ SHPC_CMD_DETECTED |
+ SHPC_ARB_DETECTED);
+ for (i = 0; i < nslots; ++i) {
+ pci_set_byte(shpc->wmask +
+ SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
+ SHPC_SLOT_EVENT_PRESENCE |
+ SHPC_SLOT_EVENT_ISOLATED_FAULT |
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT |
+ SHPC_SLOT_EVENT_MRL_SERR_DIS |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
+ pci_set_byte(shpc->w1cmask +
+ SHPC_SLOT_EVENT_LATCH(i),
+ SHPC_SLOT_EVENT_PRESENCE |
+ SHPC_SLOT_EVENT_ISOLATED_FAULT |
+ SHPC_SLOT_EVENT_BUTTON |
+ SHPC_SLOT_EVENT_MRL |
+ SHPC_SLOT_EVENT_CONNECTED_FAULT);
+ }
+
+ /* TODO: init cmask */
+ memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
+ SHPC_SIZEOF(d));
+ shpc_cap_update_dword(d);
+ memory_region_add_subregion(bar, offset, &shpc->mmio);
+ pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
+ return 0;
+}
+
+int shpc_bar_size(PCIDevice *d)
+{
+ return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
+}
+
+void shpc_cleanup(PCIDevice *d)
+{
+ SHPCDevice *shpc = d->shpc;
+ /* TODO: cleanup config space changes? */
+ g_free(shpc->config);
+ g_free(shpc->cmask);
+ g_free(shpc->wmask);
+ g_free(shpc->w1cmask);
+ memory_region_destroy(&shpc->mmio);
+ g_free(shpc);
+}
+
+void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
+{
+ if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
+ return;
+ }
+ fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
+ if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
+ unsigned dword_data;
+ dword_data = pci_get_long(d->shpc->config + d->shpc->cap
+ + SHPC_CAP_DWORD_DATA);
+ shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
+ }
+ /* Update cap dword data in case guest is going to read it. */
+ shpc_cap_update_dword(d);
+}
diff --git a/hw/shpc.h b/hw/shpc.h
new file mode 100644
index 0000000..389b178
--- /dev/null
+++ b/hw/shpc.h
@@ -0,0 +1,40 @@
+#ifndef SHPC_H
+#define SHPC_H
+
+#include "qemu-common.h"
+#include "memory.h"
+
+struct SHPCDevice {
+ /* Capability offset in device's config space */
+ int cap;
+
+ /* # of hot-pluggable slots */
+ int nslots;
+
+ /* SHPC WRS: working register set */
+ uint8_t *config;
+
+ /* Used to enable checks on load. Note that writable bits are
+ * never checked even if set in cmask. */
+ uint8_t *cmask;
+
+ /* Used to implement R/W bytes */
+ uint8_t *wmask;
+
+ /* Used to implement RW1C(Write 1 to Clear) bytes */
+ uint8_t *w1cmask;
+
+ /* MMIO for the SHPC BAR */
+ MemoryRegion mmio;
+
+ /* Bus controlled by this SHPC */
+ PCIBus *sec_bus;
+};
+
+void shpc_reset(PCIDevice *d);
+int shpc_bar_size(PCIDevice *dev);
+int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
+void shpc_cleanup(PCIDevice *dev);
+void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
+
+#endif
diff --git a/qemu-common.h b/qemu-common.h
index 9b997f8..4ff9c95 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
typedef struct EventNotifier EventNotifier;
typedef struct VirtIODevice VirtIODevice;
typedef struct QEMUSGList QEMUSGList;
+typedef struct SHPCDevice SHPCDevice;
typedef uint64_t pcibus_t;
--
1.7.9.111.gf3fb0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-13 9:16 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:16 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: Kevin Wolf, Isaku Yamahata, Avi Kivity
This adds support for a standard pci to pci bridge,
enabling support for more than 32 PCI devices in the system.
Device hotplug is supported by means of SHPC controller.
For guests with an SHPC driver, this allows robust hotplug
and even hotplug of nested bridges, up to 31 devices
per bridge.
TODO:
- chassis capability support
- migration support
- remove dependency on pci_internals.h
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
Makefile.objs | 2 +-
hw/pci_bridge_dev.c | 136 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 137 insertions(+), 1 deletions(-)
create mode 100644 hw/pci_bridge_dev.c
diff --git a/Makefile.objs b/Makefile.objs
index 4546477..e89112c 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -193,7 +193,7 @@ hw-obj-$(CONFIG_VIRTIO) += virtio-console.o
hw-obj-y += usb-libhw.o
hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
hw-obj-y += fw_cfg.o
-hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
+hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o pci_bridge_dev.o
hw-obj-$(CONFIG_PCI) += msix.o msi.o
hw-obj-$(CONFIG_PCI) += shpc.o
hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c
new file mode 100644
index 0000000..f48cd2d
--- /dev/null
+++ b/hw/pci_bridge_dev.c
@@ -0,0 +1,136 @@
+/*
+ * Standard PCI Bridge Device
+ *
+ * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pci_bridge.h"
+#include "pci_ids.h"
+#include "shpc.h"
+#include "memory.h"
+#include "pci_internals.h"
+
+#define REDHAT_PCI_VENDOR_ID 0x1b36
+#define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
+#define PCI_BRIDGE_DEV_DEVICE_ID 0x1
+
+struct PCIBridgeDev {
+ PCIBridge bridge;
+ MemoryRegion bar;
+};
+typedef struct PCIBridgeDev PCIBridgeDev;
+
+/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
+ * revision 1.2 */
+/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
+static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
+{
+ return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
+}
+
+static int pci_bridge_dev_initfn(PCIDevice *dev)
+{
+ PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
+ PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
+ int err;
+ br->map_irq = pci_bridge_dev_map_irq_fn;
+ /* If we don't specify the name, the bus will be addressed as <id>.0, where
+ * id is the parent id. But it seems more natural to address the bus using
+ * the parent device name. */
+ if (dev->qdev.id && *dev->qdev.id) {
+ br->bus_name = dev->qdev.id;
+ }
+ err = pci_bridge_initfn(dev);
+ if (err) {
+ goto bridge_error;
+ }
+ memory_region_init(&bridge_dev->bar, "shpc-bar", shpc_bar_size(dev));
+ err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
+ if (err) {
+ goto error;
+ }
+ /* TODO: spec recommends using 64 bit prefetcheable BAR.
+ * Check whether that works well. */
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &bridge_dev->bar);
+ dev->config[PCI_INTERRUPT_PIN] = 0x1;
+ return 0;
+error:
+ memory_region_destroy(&bridge_dev->bar);
+bridge_error:
+ return err;
+}
+
+static int pci_bridge_dev_exitfn(PCIDevice *dev)
+{
+ PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
+ PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
+ int ret;
+ shpc_cleanup(dev);
+ memory_region_destroy(&bridge_dev->bar);
+ ret = pci_bridge_exitfn(dev);
+ assert(!ret);
+ return 0;
+}
+
+static void pci_bridge_dev_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ pci_bridge_write_config(d, address, val, len);
+ shpc_cap_write_config(d, address, val, len);
+}
+
+static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
+{
+ PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
+ pci_bridge_reset(qdev);
+ shpc_reset(dev);
+}
+
+static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ k->init = pci_bridge_dev_initfn;
+ k->exit = pci_bridge_dev_exitfn;
+ k->config_write = pci_bridge_dev_write_config;
+ k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID;
+ k->device_id = PCI_BRIDGE_DEV_DEVICE_ID;
+ k->class_id = PCI_CLASS_BRIDGE_PCI;
+ k->is_bridge = 1,
+ dc->desc = "Standard PCI Bridge";
+ dc->reset = qdev_pci_bridge_dev_reset;
+ /*
+ * TODO: migration.
+ * dc->vmsd =
+ * dc->props =
+ */
+}
+
+static TypeInfo pci_bridge_dev_info = {
+ .name = "pci-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PCIBridgeDev),
+ .class_init = pci_bridge_dev_class_init,
+};
+
+static void pci_bridge_dev_register(void)
+{
+ type_register_static(&pci_bridge_dev_info);
+}
+
+device_init(pci_bridge_dev_register);
--
1.7.9.111.gf3fb0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-13 9:16 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:16 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: Kevin Wolf, Isaku Yamahata, Avi Kivity
This adds support for a standard pci to pci bridge,
enabling support for more than 32 PCI devices in the system.
Device hotplug is supported by means of SHPC controller.
For guests with an SHPC driver, this allows robust hotplug
and even hotplug of nested bridges, up to 31 devices
per bridge.
TODO:
- chassis capability support
- migration support
- remove dependency on pci_internals.h
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
Makefile.objs | 2 +-
hw/pci_bridge_dev.c | 136 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 137 insertions(+), 1 deletions(-)
create mode 100644 hw/pci_bridge_dev.c
diff --git a/Makefile.objs b/Makefile.objs
index 4546477..e89112c 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -193,7 +193,7 @@ hw-obj-$(CONFIG_VIRTIO) += virtio-console.o
hw-obj-y += usb-libhw.o
hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
hw-obj-y += fw_cfg.o
-hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
+hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o pci_bridge_dev.o
hw-obj-$(CONFIG_PCI) += msix.o msi.o
hw-obj-$(CONFIG_PCI) += shpc.o
hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c
new file mode 100644
index 0000000..f48cd2d
--- /dev/null
+++ b/hw/pci_bridge_dev.c
@@ -0,0 +1,136 @@
+/*
+ * Standard PCI Bridge Device
+ *
+ * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pci_bridge.h"
+#include "pci_ids.h"
+#include "shpc.h"
+#include "memory.h"
+#include "pci_internals.h"
+
+#define REDHAT_PCI_VENDOR_ID 0x1b36
+#define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
+#define PCI_BRIDGE_DEV_DEVICE_ID 0x1
+
+struct PCIBridgeDev {
+ PCIBridge bridge;
+ MemoryRegion bar;
+};
+typedef struct PCIBridgeDev PCIBridgeDev;
+
+/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
+ * revision 1.2 */
+/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
+static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
+{
+ return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
+}
+
+static int pci_bridge_dev_initfn(PCIDevice *dev)
+{
+ PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
+ PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
+ int err;
+ br->map_irq = pci_bridge_dev_map_irq_fn;
+ /* If we don't specify the name, the bus will be addressed as <id>.0, where
+ * id is the parent id. But it seems more natural to address the bus using
+ * the parent device name. */
+ if (dev->qdev.id && *dev->qdev.id) {
+ br->bus_name = dev->qdev.id;
+ }
+ err = pci_bridge_initfn(dev);
+ if (err) {
+ goto bridge_error;
+ }
+ memory_region_init(&bridge_dev->bar, "shpc-bar", shpc_bar_size(dev));
+ err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
+ if (err) {
+ goto error;
+ }
+ /* TODO: spec recommends using 64 bit prefetcheable BAR.
+ * Check whether that works well. */
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &bridge_dev->bar);
+ dev->config[PCI_INTERRUPT_PIN] = 0x1;
+ return 0;
+error:
+ memory_region_destroy(&bridge_dev->bar);
+bridge_error:
+ return err;
+}
+
+static int pci_bridge_dev_exitfn(PCIDevice *dev)
+{
+ PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
+ PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
+ int ret;
+ shpc_cleanup(dev);
+ memory_region_destroy(&bridge_dev->bar);
+ ret = pci_bridge_exitfn(dev);
+ assert(!ret);
+ return 0;
+}
+
+static void pci_bridge_dev_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ pci_bridge_write_config(d, address, val, len);
+ shpc_cap_write_config(d, address, val, len);
+}
+
+static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
+{
+ PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
+ pci_bridge_reset(qdev);
+ shpc_reset(dev);
+}
+
+static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ k->init = pci_bridge_dev_initfn;
+ k->exit = pci_bridge_dev_exitfn;
+ k->config_write = pci_bridge_dev_write_config;
+ k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID;
+ k->device_id = PCI_BRIDGE_DEV_DEVICE_ID;
+ k->class_id = PCI_CLASS_BRIDGE_PCI;
+ k->is_bridge = 1,
+ dc->desc = "Standard PCI Bridge";
+ dc->reset = qdev_pci_bridge_dev_reset;
+ /*
+ * TODO: migration.
+ * dc->vmsd =
+ * dc->props =
+ */
+}
+
+static TypeInfo pci_bridge_dev_info = {
+ .name = "pci-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PCIBridgeDev),
+ .class_init = pci_bridge_dev_class_init,
+};
+
+static void pci_bridge_dev_register(void)
+{
+ type_register_static(&pci_bridge_dev_info);
+}
+
+device_init(pci_bridge_dev_register);
--
1.7.9.111.gf3fb0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH RFC] seabios: add OSHP method stub
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-13 9:33 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:33 UTC (permalink / raw)
To: seabios
Cc: qemu-devel, kvm, Wen Congyang, Avi Kivity, Kevin Wolf,
Anthony Liguori, Isaku Yamahata, berrange
To allow guests to load the native SHPC driver
for a bridge, we must declare an OSHP method
for the appropriate device which lets the OS
take control of the SHPC.
As we don't access SHPC at the moment, we
don't need to do anything - just report success.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
diff --git a/src/ssdt-pcihp.dsl b/src/ssdt-pcihp.dsl
index 442e7a8..3f50169 100644
--- a/src/ssdt-pcihp.dsl
+++ b/src/ssdt-pcihp.dsl
@@ -24,6 +24,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
ACPI_EXTRACT_METHOD_STRING aml_ej0_name \
Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \
Name (_SUN, 0x##slot) \
+ Method (OSHP, 1) { Return(0x0) } \
}
hotplug_slot(03)
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-13 9:33 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:33 UTC (permalink / raw)
To: seabios; +Cc: Kevin Wolf, kvm, qemu-devel, Isaku Yamahata, Avi Kivity
To allow guests to load the native SHPC driver
for a bridge, we must declare an OSHP method
for the appropriate device which lets the OS
take control of the SHPC.
As we don't access SHPC at the moment, we
don't need to do anything - just report success.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
diff --git a/src/ssdt-pcihp.dsl b/src/ssdt-pcihp.dsl
index 442e7a8..3f50169 100644
--- a/src/ssdt-pcihp.dsl
+++ b/src/ssdt-pcihp.dsl
@@ -24,6 +24,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
ACPI_EXTRACT_METHOD_STRING aml_ej0_name \
Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \
Name (_SUN, 0x##slot) \
+ Method (OSHP, 1) { Return(0x0) } \
}
hotplug_slot(03)
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 0/2] RFC: standard pci bridge device
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-13 9:38 ` Wen Congyang
-1 siblings, 0 replies; 52+ messages in thread
From: Wen Congyang @ 2012-02-13 9:38 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qemu-devel, kvm, Avi Kivity, Kevin Wolf, Anthony Liguori,
Isaku Yamahata, berrange
At 02/13/2012 05:15 PM, Michael S. Tsirkin Wrote:
> Here's a new version of the patch. It works for me.
> Deep nesting of bridges is supported.
> You need a small BIOS patch to support the OSHP method
> if you want hotplug to work. I will post this separately.
> We'd need a full ACPI driver to make hotplug work for guests
> without an SHPC driver (e.g. windows XP).
> Management support will also be needed.
>
> One small wrinkle is that the pci_addr property
> wants data in a format bus:device.function which is
> broken as guests can change bus numbers.
> For testing I used the 'addr' property which
> encodes slot*8+function#. We probably want to
> extend pci_addr in some way (e.g. :device.function ?
> Thoughts?).
What about using id+device(slot)+function to set the address?
>
> The SHPC controller supports up to 31 devices
> (out of 32 slots) so slot 0 doesn't support hotplug.
> Non hot-pluggable devices behind the bridge
> don't work currectly (we'll try to unplug them)
> so don't do this.
> For now I just blocked adding devices in slot 0,
> in the future it might be possible to add
> a non-hotpluggable device there.
>
> Example:
>
> qemu-system-x86_64 -enable-kvm -m 1G
> -drive file=/home/mst/rhel6.qcow2
> -netdev
> tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
> -device pci-bridge,id=bog
> -device virtio-net-pci,netdev=foo,bus=bog,addr=8
>
>
> Hot-unplug currently causes qemu to crash, this
> happens without this patch too, so I'm not worried :)
How to trigger this bug without this patch?
Thanks
Wen Congyang
>
> New since v1:
> hotplug support
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 0/2] RFC: standard pci bridge device
@ 2012-02-13 9:38 ` Wen Congyang
0 siblings, 0 replies; 52+ messages in thread
From: Wen Congyang @ 2012-02-13 9:38 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, qemu-devel, Isaku Yamahata, Avi Kivity
At 02/13/2012 05:15 PM, Michael S. Tsirkin Wrote:
> Here's a new version of the patch. It works for me.
> Deep nesting of bridges is supported.
> You need a small BIOS patch to support the OSHP method
> if you want hotplug to work. I will post this separately.
> We'd need a full ACPI driver to make hotplug work for guests
> without an SHPC driver (e.g. windows XP).
> Management support will also be needed.
>
> One small wrinkle is that the pci_addr property
> wants data in a format bus:device.function which is
> broken as guests can change bus numbers.
> For testing I used the 'addr' property which
> encodes slot*8+function#. We probably want to
> extend pci_addr in some way (e.g. :device.function ?
> Thoughts?).
What about using id+device(slot)+function to set the address?
>
> The SHPC controller supports up to 31 devices
> (out of 32 slots) so slot 0 doesn't support hotplug.
> Non hot-pluggable devices behind the bridge
> don't work currectly (we'll try to unplug them)
> so don't do this.
> For now I just blocked adding devices in slot 0,
> in the future it might be possible to add
> a non-hotpluggable device there.
>
> Example:
>
> qemu-system-x86_64 -enable-kvm -m 1G
> -drive file=/home/mst/rhel6.qcow2
> -netdev
> tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
> -device pci-bridge,id=bog
> -device virtio-net-pci,netdev=foo,bus=bog,addr=8
>
>
> Hot-unplug currently causes qemu to crash, this
> happens without this patch too, so I'm not worried :)
How to trigger this bug without this patch?
Thanks
Wen Congyang
>
> New since v1:
> hotplug support
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 0/2] RFC: standard pci bridge device
2012-02-13 9:38 ` [Qemu-devel] " Wen Congyang
@ 2012-02-13 9:56 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:56 UTC (permalink / raw)
To: Wen Congyang
Cc: qemu-devel, kvm, Avi Kivity, Kevin Wolf, Anthony Liguori,
Isaku Yamahata, berrange
On Mon, Feb 13, 2012 at 05:38:26PM +0800, Wen Congyang wrote:
> At 02/13/2012 05:15 PM, Michael S. Tsirkin Wrote:
> > Here's a new version of the patch. It works for me.
> > Deep nesting of bridges is supported.
> > You need a small BIOS patch to support the OSHP method
> > if you want hotplug to work. I will post this separately.
> > We'd need a full ACPI driver to make hotplug work for guests
> > without an SHPC driver (e.g. windows XP).
> > Management support will also be needed.
> >
> > One small wrinkle is that the pci_addr property
> > wants data in a format bus:device.function which is
> > broken as guests can change bus numbers.
> > For testing I used the 'addr' property which
> > encodes slot*8+function#. We probably want to
> > extend pci_addr in some way (e.g. :device.function ?
> > Thoughts?).
>
> What about using id+device(slot)+function to set the address?
That's exactly what this patch does: addr encodes
slot+function.
I was asking about a friendlier format for this.
> >
> > The SHPC controller supports up to 31 devices
> > (out of 32 slots) so slot 0 doesn't support hotplug.
> > Non hot-pluggable devices behind the bridge
> > don't work currectly (we'll try to unplug them)
> > so don't do this.
> > For now I just blocked adding devices in slot 0,
> > in the future it might be possible to add
> > a non-hotpluggable device there.
> >
> > Example:
> >
> > qemu-system-x86_64 -enable-kvm -m 1G
> > -drive file=/home/mst/rhel6.qcow2
> > -netdev
> > tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
> > -device pci-bridge,id=bog
> > -device virtio-net-pci,netdev=foo,bus=bog,addr=8
> >
> >
> > Hot-unplug currently causes qemu to crash, this
> > happens without this patch too, so I'm not worried :)
>
> How to trigger this bug without this patch?
>
> Thanks
> Wen Congyang
start with
qemu-system-x86_64 -enable-kvm -m 1G
-drive file=/home/mst/rhel6.qcow2
-netdev
tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
next do:
device_add virtio-net-pci,netdev=foo,id=bla
<wait a bit for guest to notice the device>
device_del bla
<wait for device to go away>
and it will crash on next malloc, to trigger
malloc give another command, e.g.
info pci
> >
> > New since v1:
> > hotplug support
> >
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 0/2] RFC: standard pci bridge device
@ 2012-02-13 9:56 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 9:56 UTC (permalink / raw)
To: Wen Congyang; +Cc: Kevin Wolf, kvm, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 05:38:26PM +0800, Wen Congyang wrote:
> At 02/13/2012 05:15 PM, Michael S. Tsirkin Wrote:
> > Here's a new version of the patch. It works for me.
> > Deep nesting of bridges is supported.
> > You need a small BIOS patch to support the OSHP method
> > if you want hotplug to work. I will post this separately.
> > We'd need a full ACPI driver to make hotplug work for guests
> > without an SHPC driver (e.g. windows XP).
> > Management support will also be needed.
> >
> > One small wrinkle is that the pci_addr property
> > wants data in a format bus:device.function which is
> > broken as guests can change bus numbers.
> > For testing I used the 'addr' property which
> > encodes slot*8+function#. We probably want to
> > extend pci_addr in some way (e.g. :device.function ?
> > Thoughts?).
>
> What about using id+device(slot)+function to set the address?
That's exactly what this patch does: addr encodes
slot+function.
I was asking about a friendlier format for this.
> >
> > The SHPC controller supports up to 31 devices
> > (out of 32 slots) so slot 0 doesn't support hotplug.
> > Non hot-pluggable devices behind the bridge
> > don't work currectly (we'll try to unplug them)
> > so don't do this.
> > For now I just blocked adding devices in slot 0,
> > in the future it might be possible to add
> > a non-hotpluggable device there.
> >
> > Example:
> >
> > qemu-system-x86_64 -enable-kvm -m 1G
> > -drive file=/home/mst/rhel6.qcow2
> > -netdev
> > tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
> > -device pci-bridge,id=bog
> > -device virtio-net-pci,netdev=foo,bus=bog,addr=8
> >
> >
> > Hot-unplug currently causes qemu to crash, this
> > happens without this patch too, so I'm not worried :)
>
> How to trigger this bug without this patch?
>
> Thanks
> Wen Congyang
start with
qemu-system-x86_64 -enable-kvm -m 1G
-drive file=/home/mst/rhel6.qcow2
-netdev
tap,id=foo,ifname=msttap0,script=/home/mst/ifup,downscript=no,vhost=on
next do:
device_add virtio-net-pci,netdev=foo,id=bla
<wait a bit for guest to notice the device>
device_del bla
<wait for device to go away>
and it will crash on next malloc, to trigger
malloc give another command, e.g.
info pci
> >
> > New since v1:
> > hotplug support
> >
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 1/2] shpc: standard hot plug controller
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-13 10:03 ` Isaku Yamahata
-1 siblings, 0 replies; 52+ messages in thread
From: Isaku Yamahata @ 2012-02-13 10:03 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qemu-devel, kvm, Wen Congyang, Avi Kivity, Kevin Wolf,
Anthony Liguori, berrange
Oh nice work.
On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> This adds support for SHPC interface, as defined by PCI Standard
> Hot-Plug Controller and Subsystem Specification, Rev 1.0
> http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
>
> Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> SHPC integrated with a host bridge would need more work.
>
> All main SHPC features are supported:
> - MRL sensor
Does this just report latch status? (It seems so.)
Do you plan to provide interfaces to manipulate the latch?
> - Attention button
> - Attention indicator
> - Power indicator
>
> Wake on hotplug and serr generation are stubbed out but unused
> as we don't have interfaces to generate these events ATM.
>
> One issue that isn't completely resolved is that qemu currently
> expects an "eject" interface, which SHPC does not provide: it merely
> removes the power to device and it's up to the user to remove the device
> from slot. This patch works around that by ejecting the device
> when power is removed and power LED goes off.
>
> TODO:
> - migration support
> - fix dependency on pci_internals.h
If I didn't miss the code,
- QMP command for pushing attention button.
- QMP command to get LED status
- QMP events for LED on/off
thanks,
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> Makefile.objs | 1 +
> hw/pci.h | 6 +
> hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/shpc.h | 40 ++++
> qemu-common.h | 1 +
> 5 files changed, 694 insertions(+), 0 deletions(-)
> create mode 100644 hw/shpc.c
> create mode 100644 hw/shpc.h
>
> diff --git a/Makefile.objs b/Makefile.objs
> index 391e524..4546477 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> hw-obj-y += fw_cfg.o
> hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> hw-obj-$(CONFIG_PCI) += msix.o msi.o
> +hw-obj-$(CONFIG_PCI) += shpc.o
> hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> hw-obj-y += watchdog.o
> diff --git a/hw/pci.h b/hw/pci.h
> index 33b0b18..756577e 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -125,6 +125,9 @@ enum {
> /* command register SERR bit enabled */
> #define QEMU_PCI_CAP_SERR_BITNR 4
> QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> + /* Standard hot plug controller. */
> +#define QEMU_PCI_SHPC_BITNR 5
> + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> };
>
> #define TYPE_PCI_DEVICE "pci-device"
> @@ -229,6 +232,9 @@ struct PCIDevice {
> /* PCI Express */
> PCIExpressDevice exp;
>
> + /* SHPC */
> + SHPCDevice *shpc;
> +
> /* Location of option rom */
> char *romfile;
> bool has_rom;
> diff --git a/hw/shpc.c b/hw/shpc.c
> new file mode 100644
> index 0000000..4baec29
> --- /dev/null
> +++ b/hw/shpc.c
> @@ -0,0 +1,646 @@
> +#include <strings.h>
> +#include <stdint.h>
> +#include "range.h"
> +#include "shpc.h"
> +#include "pci.h"
> +#include "pci_internals.h"
> +
> +/* TODO: model power only and disabled slot states. */
> +/* TODO: handle SERR and wakeups */
> +/* TODO: consider enabling 66MHz support */
> +
> +/* TODO: remove fully only on state DISABLED and LED off.
> + * track state to properly record this. */
> +
> +/* SHPC Working Register Set */
> +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> +#define SHPC_NSLOTS 0x0C /* 1 byte */
> +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> +#define SHPC_PHYS_NUM_MAX 0x7ff
> +#define SHPC_PHYS_NUM_UP 0x1000
> +#define SHPC_PHYS_MRL 0x4000
> +#define SHPC_PHYS_BUTTON 0x8000
> +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> +#define SHPC_SEC_BUS_33 0x0
> +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> +#define SHPC_SEC_BUS_MASK 0x7
> +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> +#define SHPC_PROG_IFC_1_0 0x1
> +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> +#define SHPC_CMD_TRGT_MIN 0x1
> +#define SHPC_CMD_TRGT_MAX 0x1f
> +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> +#define SHPC_CMD_STATUS_BUSY 0x1
> +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> +#define SHPC_INT_COMMAND 0x1
> +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> +#define SHPC_INT_DIS 0x1
> +#define SHPC_SERR_DIS 0x2
> +#define SHPC_CMD_INT_DIS 0x4
> +#define SHPC_ARB_SERR_DIS 0x8
> +#define SHPC_CMD_DETECTED 0x10000
> +#define SHPC_ARB_DETECTED 0x20000
> + /* 4 bytes * slot # (start from 0) */
> +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> + /* 2 bytes */
> +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> +
> +/* Same slot state masks are used for command and status registers */
> +#define SHPC_SLOT_STATE_MASK 0x03
> +#define SHPC_SLOT_STATE_SHIFT \
> + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> +
> +#define SHPC_STATE_NO 0x0
> +#define SHPC_STATE_PWRONLY 0x1
> +#define SHPC_STATE_ENABLED 0x2
> +#define SHPC_STATE_DISABLED 0x3
> +
> +#define SHPC_SLOT_PWR_LED_MASK 0xC
> +#define SHPC_SLOT_PWR_LED_SHIFT \
> + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> +#define SHPC_SLOT_ATTN_LED_SHIFT \
> + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> +
> +#define SHPC_LED_NO 0x0
> +#define SHPC_LED_ON 0x1
> +#define SHPC_LED_BLINK 0x2
> +#define SHPC_LED_OFF 0x3
> +
> +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> +#define SHPC_SLOT_STATUS_BUTTON 0x80
> +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> +#define SHPC_SLOT_STATUS_66 0x200
> +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> +
> +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> +
> +
> + /* 1 byte */
> +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> + /* 1 byte */
> +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> +#define SHPC_SLOT_EVENT_BUTTON 0x04
> +#define SHPC_SLOT_EVENT_MRL 0x08
> +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> +/* Bits below are used for Serr/Int disable only */
> +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> +
> +#define SHPC_MIN_SLOTS 1
> +#define SHPC_MAX_SLOTS 31
> +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> +
> +/* SHPC Slot identifiers */
> +
> +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> + and give the rest of them physical *and* pci numbers starting from 1, so
> + they match logical numbers. Note: this means that multiple slots must have
> + different chassis number values, to make chassis+physical slot unique.
> + TODO: make this configurable? */
> +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> +
> +static int roundup_pow_of_two(int x)
> +{
> + x |= (x >> 1);
> + x |= (x >> 2);
> + x |= (x >> 4);
> + x |= (x >> 8);
> + x |= (x >> 16);
> + return x + 1;
> +}
> +
> +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> +{
> + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> +}
> +
> +static void shpc_set_status(SHPCDevice *shpc,
> + int slot, uint8_t value, uint16_t msk)
> +{
> + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> + pci_word_test_and_clear_mask(status, msk);
> + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> +}
> +
> +static void shpc_interrupt_update(PCIDevice *d)
> +{
> + SHPCDevice *shpc = d->shpc;
> + int slot;
> + int level = 0;
> + uint32_t serr_int;
> + uint32_t int_locator = 0;
> +
> + /* Update interrupt locator register */
> + for (slot = 0; slot < shpc->nslots; ++slot) {
> + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> + if (event & ~disable) {
> + int_locator |= mask;
> + }
> + }
> + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> + int_locator |= SHPC_INT_COMMAND;
> + }
> + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> + qemu_set_irq(d->irq[0], level);
> +}
> +
> +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> +{
> + switch (speed) {
> + case SHPC_SEC_BUS_33:
> + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> + shpc->config[SHPC_SEC_BUS] |= speed;
> + break;
> + default:
> + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> + SHPC_CMD_STATUS_INVALID_MODE);
> + }
> +}
> +
> +void shpc_reset(PCIDevice *d)
> +{
> + SHPCDevice *shpc = d->shpc;
> + int nslots = shpc->nslots;
> + int i;
> + memset(shpc->config, 0, SHPC_SIZEOF(d));
> + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> + SHPC_IDX_TO_PHYSICAL(0) |
> + SHPC_PHYS_NUM_UP |
> + SHPC_PHYS_MRL |
> + SHPC_PHYS_BUTTON);
> + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> + SHPC_SERR_DIS |
> + SHPC_CMD_INT_DIS |
> + SHPC_ARB_SERR_DIS);
> + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> + for (i = 0; i < shpc->nslots; ++i) {
> + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> + SHPC_SLOT_EVENT_PRESENCE |
> + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> + } else {
> + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> + }
> + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> + }
> + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> + shpc_interrupt_update(d);
> +}
> +
> +static void shpc_invalid_command(SHPCDevice *shpc)
> +{
> + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> + SHPC_CMD_STATUS_INVALID_CMD);
> +}
> +
> +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> +{
> + int devfn;
> + int pci_slot = SHPC_IDX_TO_PCI(slot);
> + for (devfn = PCI_DEVFN(pci_slot, 0);
> + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> + ++devfn) {
> + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> + if (affected_dev) {
> + qdev_free(&affected_dev->qdev);
> + }
> + }
> +}
> +
> +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> + uint8_t state, uint8_t power, uint8_t attn)
> +{
> + uint8_t current_state;
> + int slot = SHPC_LOGICAL_TO_IDX(target);
> + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> + shpc_invalid_command(shpc);
> + return;
> + }
> + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> + shpc_invalid_command(shpc);
> + return;
> + }
> +
> + switch (power) {
> + case SHPC_LED_NO:
> + break;
> + default:
> + /* TODO: send event to monitor */
> + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> + }
> + switch (attn) {
> + case SHPC_LED_NO:
> + break;
> + default:
> + /* TODO: send event to monitor */
> + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> + }
> +
> + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> + } else if ((current_state == SHPC_STATE_ENABLED ||
> + current_state == SHPC_STATE_PWRONLY) &&
> + state == SHPC_STATE_DISABLED) {
> + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> + /* TODO: track what monitor requested. */
> + /* Look at LED to figure out whether it's ok to remove the device. */
> + if (power == SHPC_LED_OFF) {
> + shpc_free_devices_in_slot(shpc, slot);
> + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_PRESENCE;
> + }
> + }
> +}
> +
> +static void shpc_command(SHPCDevice *shpc)
> +{
> + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> + uint8_t speed;
> + uint8_t target;
> + uint8_t attn;
> + uint8_t power;
> + uint8_t state;
> + int i;
> +
> + /* Clear status from the previous command. */
> + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> + SHPC_CMD_STATUS_BUSY |
> + SHPC_CMD_STATUS_MRL_OPEN |
> + SHPC_CMD_STATUS_INVALID_CMD |
> + SHPC_CMD_STATUS_INVALID_MODE);
> + switch (code) {
> + case 0x00 ... 0x3f:
> + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> + shpc_slot_command(shpc, target, state, power, attn);
> + break;
> + case 0x40 ... 0x47:
> + speed = code & SHPC_SEC_BUS_MASK;
> + shpc_set_sec_bus_speed(shpc, speed);
> + break;
> + case 0x48:
> + /* Power only all slots */
> + /* first verify no slots are enabled */
> + for (i = 0; i < shpc->nslots; ++i) {
> + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> + if (state == SHPC_STATE_ENABLED) {
> + shpc_invalid_command(shpc);
> + goto done;
> + }
> + }
> + for (i = 0; i < shpc->nslots; ++i) {
> + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> + } else {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> + }
> + }
> + break;
> + case 0x49:
> + /* Enable all slots */
> + /* TODO: Spec says this shall fail if some are already enabled.
> + * This doesn't make sense - why not? a spec bug? */
> + for (i = 0; i < shpc->nslots; ++i) {
> + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> + if (state == SHPC_STATE_ENABLED) {
> + shpc_invalid_command(shpc);
> + goto done;
> + }
> + }
> + for (i = 0; i < shpc->nslots; ++i) {
> + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> + } else {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> + }
> + }
> + break;
> + default:
> + shpc_invalid_command(shpc);
> + break;
> + }
> +done:
> + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> +}
> +
> +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> +{
> + SHPCDevice *shpc = d->shpc;
> + int i;
> + if (addr >= SHPC_SIZEOF(d)) {
> + return;
> + }
> + l = MIN(l, SHPC_SIZEOF(d) - addr);
> +
> + /* TODO: code duplicated from pci.c */
> + for (i = 0; i < l; val >>= 8, ++i) {
> + unsigned a = addr + i;
> + uint8_t wmask = shpc->wmask[a];
> + uint8_t w1cmask = shpc->w1cmask[a];
> + assert(!(wmask & w1cmask));
> + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> + }
> + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> + shpc_command(shpc);
> + }
> + shpc_interrupt_update(d);
> +}
> +
> +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> +{
> + uint64_t val = 0x0;
> + if (addr >= SHPC_SIZEOF(d)) {
> + return val;
> + }
> + l = MIN(l, SHPC_SIZEOF(d) - addr);
> + memcpy(&val, d->shpc->config + addr, l);
> + return val;
> +}
> +
> +/* SHPC Bridge Capability */
> +#define SHPC_CAP_LENGTH 0x08
> +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> +#define SHPC_CAP_CSP_MASK 0x4
> +#define SHPC_CAP_CIP_MASK 0x8
> +
> +static uint8_t shpc_cap_dword(PCIDevice *d)
> +{
> + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> +}
> +
> +/* Update dword data capability register */
> +static void shpc_cap_update_dword(PCIDevice *d)
> +{
> + unsigned data;
> + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> +}
> +
> +/* Add SHPC capability to the config space for the device. */
> +static int shpc_cap_add_config(PCIDevice *d)
> +{
> + uint8_t *config;
> + int config_offset;
> + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> + 0, SHPC_CAP_LENGTH);
> + if (config_offset < 0) {
> + return config_offset;
> + }
> + config = d->config + config_offset;
> +
> + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> + pci_set_byte(config + SHPC_CAP_CxP, 0);
> + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> + d->shpc->cap = config_offset;
> + /* Make dword select and data writeable. */
> + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> + return 0;
> +}
> +
> +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> +{
> + return shpc_read(opaque, addr, size);
> +}
> +
> +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> + uint64_t val, unsigned size)
> +{
> + shpc_write(opaque, addr, val, size);
> +}
> +
> +static const MemoryRegionOps shpc_mmio_ops = {
> + .read = shpc_mmio_read,
> + .write = shpc_mmio_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> + * It's easier to suppport all sizes than worry about it. */
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> + PCIHotplugState hotplug_state)
> +{
> + int pci_slot = PCI_SLOT(affected_dev->devfn);
> + uint8_t state;
> + uint8_t led;
> + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> + SHPCDevice *shpc = d->shpc;
> + int slot = SHPC_PCI_TO_IDX(pci_slot);
> + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> + error_report("Unsupported PCI slot %d for standard hotplug "
> + "controller. Valid slots are between %d and %d.",
> + pci_slot, SHPC_IDX_TO_PCI(0),
> + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> + return -1;
> + }
> + /* Don't send event when device is enabled during qemu machine creation:
> + * it is present on boot, no hotplug event is necessary. We do send an
> + * event when the device is disabled later. */
> + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + return 0;
> + }
> + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> + shpc_free_devices_in_slot(shpc, slot);
> + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_PRESENCE;
> + }
> + } else {
> + /* This could be a cancellation of the previous removal.
> + * We check MRL state to figure out. */
> + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_PRESENCE;
> + } else {
> + /* Press attention button to cancel removal */
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_BUTTON;
> + }
> + }
> + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> + shpc_interrupt_update(d);
> + return 0;
> +}
> +
> +/* Initialize the SHPC structure in bridge's BAR. */
> +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> +{
> + int i, ret;
> + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> + shpc->sec_bus = sec_bus;
> + ret = shpc_cap_add_config(d);
> + if (ret) {
> + g_free(d->shpc);
> + return ret;
> + }
> + if (nslots < SHPC_MIN_SLOTS) {
> + return 0;
> + }
> + if (nslots > SHPC_MAX_SLOTS ||
> + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> + /* TODO: report an error mesage that makes sense. */
> + return -EINVAL;
> + }
> + shpc->nslots = nslots;
> + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> +
> + shpc_reset(d);
> +
> + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> +
> + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> + SHPC_INT_DIS |
> + SHPC_SERR_DIS |
> + SHPC_CMD_INT_DIS |
> + SHPC_ARB_SERR_DIS);
> + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> + SHPC_CMD_DETECTED |
> + SHPC_ARB_DETECTED);
> + for (i = 0; i < nslots; ++i) {
> + pci_set_byte(shpc->wmask +
> + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> + SHPC_SLOT_EVENT_PRESENCE |
> + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> + pci_set_byte(shpc->w1cmask +
> + SHPC_SLOT_EVENT_LATCH(i),
> + SHPC_SLOT_EVENT_PRESENCE |
> + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> + }
> +
> + /* TODO: init cmask */
> + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> + SHPC_SIZEOF(d));
> + shpc_cap_update_dword(d);
> + memory_region_add_subregion(bar, offset, &shpc->mmio);
> + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> + return 0;
> +}
> +
> +int shpc_bar_size(PCIDevice *d)
> +{
> + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> +}
> +
> +void shpc_cleanup(PCIDevice *d)
> +{
> + SHPCDevice *shpc = d->shpc;
> + /* TODO: cleanup config space changes? */
> + g_free(shpc->config);
> + g_free(shpc->cmask);
> + g_free(shpc->wmask);
> + g_free(shpc->w1cmask);
> + memory_region_destroy(&shpc->mmio);
> + g_free(shpc);
> +}
> +
> +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> +{
> + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> + return;
> + }
> + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> + unsigned dword_data;
> + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> + + SHPC_CAP_DWORD_DATA);
> + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> + }
> + /* Update cap dword data in case guest is going to read it. */
> + shpc_cap_update_dword(d);
> +}
> diff --git a/hw/shpc.h b/hw/shpc.h
> new file mode 100644
> index 0000000..389b178
> --- /dev/null
> +++ b/hw/shpc.h
> @@ -0,0 +1,40 @@
> +#ifndef SHPC_H
> +#define SHPC_H
> +
> +#include "qemu-common.h"
> +#include "memory.h"
> +
> +struct SHPCDevice {
> + /* Capability offset in device's config space */
> + int cap;
> +
> + /* # of hot-pluggable slots */
> + int nslots;
> +
> + /* SHPC WRS: working register set */
> + uint8_t *config;
> +
> + /* Used to enable checks on load. Note that writable bits are
> + * never checked even if set in cmask. */
> + uint8_t *cmask;
> +
> + /* Used to implement R/W bytes */
> + uint8_t *wmask;
> +
> + /* Used to implement RW1C(Write 1 to Clear) bytes */
> + uint8_t *w1cmask;
> +
> + /* MMIO for the SHPC BAR */
> + MemoryRegion mmio;
> +
> + /* Bus controlled by this SHPC */
> + PCIBus *sec_bus;
> +};
> +
> +void shpc_reset(PCIDevice *d);
> +int shpc_bar_size(PCIDevice *dev);
> +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> +void shpc_cleanup(PCIDevice *dev);
> +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> +
> +#endif
> diff --git a/qemu-common.h b/qemu-common.h
> index 9b997f8..4ff9c95 100644
> --- a/qemu-common.h
> +++ b/qemu-common.h
> @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> typedef struct EventNotifier EventNotifier;
> typedef struct VirtIODevice VirtIODevice;
> typedef struct QEMUSGList QEMUSGList;
> +typedef struct SHPCDevice SHPCDevice;
>
> typedef uint64_t pcibus_t;
>
> --
> 1.7.9.111.gf3fb0
>
--
yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 1/2] shpc: standard hot plug controller
@ 2012-02-13 10:03 ` Isaku Yamahata
0 siblings, 0 replies; 52+ messages in thread
From: Isaku Yamahata @ 2012-02-13 10:03 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Kevin Wolf, kvm, qemu-devel, Avi Kivity
Oh nice work.
On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> This adds support for SHPC interface, as defined by PCI Standard
> Hot-Plug Controller and Subsystem Specification, Rev 1.0
> http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
>
> Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> SHPC integrated with a host bridge would need more work.
>
> All main SHPC features are supported:
> - MRL sensor
Does this just report latch status? (It seems so.)
Do you plan to provide interfaces to manipulate the latch?
> - Attention button
> - Attention indicator
> - Power indicator
>
> Wake on hotplug and serr generation are stubbed out but unused
> as we don't have interfaces to generate these events ATM.
>
> One issue that isn't completely resolved is that qemu currently
> expects an "eject" interface, which SHPC does not provide: it merely
> removes the power to device and it's up to the user to remove the device
> from slot. This patch works around that by ejecting the device
> when power is removed and power LED goes off.
>
> TODO:
> - migration support
> - fix dependency on pci_internals.h
If I didn't miss the code,
- QMP command for pushing attention button.
- QMP command to get LED status
- QMP events for LED on/off
thanks,
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> Makefile.objs | 1 +
> hw/pci.h | 6 +
> hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/shpc.h | 40 ++++
> qemu-common.h | 1 +
> 5 files changed, 694 insertions(+), 0 deletions(-)
> create mode 100644 hw/shpc.c
> create mode 100644 hw/shpc.h
>
> diff --git a/Makefile.objs b/Makefile.objs
> index 391e524..4546477 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> hw-obj-y += fw_cfg.o
> hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> hw-obj-$(CONFIG_PCI) += msix.o msi.o
> +hw-obj-$(CONFIG_PCI) += shpc.o
> hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> hw-obj-y += watchdog.o
> diff --git a/hw/pci.h b/hw/pci.h
> index 33b0b18..756577e 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -125,6 +125,9 @@ enum {
> /* command register SERR bit enabled */
> #define QEMU_PCI_CAP_SERR_BITNR 4
> QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> + /* Standard hot plug controller. */
> +#define QEMU_PCI_SHPC_BITNR 5
> + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> };
>
> #define TYPE_PCI_DEVICE "pci-device"
> @@ -229,6 +232,9 @@ struct PCIDevice {
> /* PCI Express */
> PCIExpressDevice exp;
>
> + /* SHPC */
> + SHPCDevice *shpc;
> +
> /* Location of option rom */
> char *romfile;
> bool has_rom;
> diff --git a/hw/shpc.c b/hw/shpc.c
> new file mode 100644
> index 0000000..4baec29
> --- /dev/null
> +++ b/hw/shpc.c
> @@ -0,0 +1,646 @@
> +#include <strings.h>
> +#include <stdint.h>
> +#include "range.h"
> +#include "shpc.h"
> +#include "pci.h"
> +#include "pci_internals.h"
> +
> +/* TODO: model power only and disabled slot states. */
> +/* TODO: handle SERR and wakeups */
> +/* TODO: consider enabling 66MHz support */
> +
> +/* TODO: remove fully only on state DISABLED and LED off.
> + * track state to properly record this. */
> +
> +/* SHPC Working Register Set */
> +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> +#define SHPC_NSLOTS 0x0C /* 1 byte */
> +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> +#define SHPC_PHYS_NUM_MAX 0x7ff
> +#define SHPC_PHYS_NUM_UP 0x1000
> +#define SHPC_PHYS_MRL 0x4000
> +#define SHPC_PHYS_BUTTON 0x8000
> +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> +#define SHPC_SEC_BUS_33 0x0
> +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> +#define SHPC_SEC_BUS_MASK 0x7
> +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> +#define SHPC_PROG_IFC_1_0 0x1
> +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> +#define SHPC_CMD_TRGT_MIN 0x1
> +#define SHPC_CMD_TRGT_MAX 0x1f
> +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> +#define SHPC_CMD_STATUS_BUSY 0x1
> +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> +#define SHPC_INT_COMMAND 0x1
> +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> +#define SHPC_INT_DIS 0x1
> +#define SHPC_SERR_DIS 0x2
> +#define SHPC_CMD_INT_DIS 0x4
> +#define SHPC_ARB_SERR_DIS 0x8
> +#define SHPC_CMD_DETECTED 0x10000
> +#define SHPC_ARB_DETECTED 0x20000
> + /* 4 bytes * slot # (start from 0) */
> +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> + /* 2 bytes */
> +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> +
> +/* Same slot state masks are used for command and status registers */
> +#define SHPC_SLOT_STATE_MASK 0x03
> +#define SHPC_SLOT_STATE_SHIFT \
> + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> +
> +#define SHPC_STATE_NO 0x0
> +#define SHPC_STATE_PWRONLY 0x1
> +#define SHPC_STATE_ENABLED 0x2
> +#define SHPC_STATE_DISABLED 0x3
> +
> +#define SHPC_SLOT_PWR_LED_MASK 0xC
> +#define SHPC_SLOT_PWR_LED_SHIFT \
> + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> +#define SHPC_SLOT_ATTN_LED_SHIFT \
> + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> +
> +#define SHPC_LED_NO 0x0
> +#define SHPC_LED_ON 0x1
> +#define SHPC_LED_BLINK 0x2
> +#define SHPC_LED_OFF 0x3
> +
> +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> +#define SHPC_SLOT_STATUS_BUTTON 0x80
> +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> +#define SHPC_SLOT_STATUS_66 0x200
> +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> +
> +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> +
> +
> + /* 1 byte */
> +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> + /* 1 byte */
> +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> +#define SHPC_SLOT_EVENT_BUTTON 0x04
> +#define SHPC_SLOT_EVENT_MRL 0x08
> +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> +/* Bits below are used for Serr/Int disable only */
> +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> +
> +#define SHPC_MIN_SLOTS 1
> +#define SHPC_MAX_SLOTS 31
> +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> +
> +/* SHPC Slot identifiers */
> +
> +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> + and give the rest of them physical *and* pci numbers starting from 1, so
> + they match logical numbers. Note: this means that multiple slots must have
> + different chassis number values, to make chassis+physical slot unique.
> + TODO: make this configurable? */
> +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> +
> +static int roundup_pow_of_two(int x)
> +{
> + x |= (x >> 1);
> + x |= (x >> 2);
> + x |= (x >> 4);
> + x |= (x >> 8);
> + x |= (x >> 16);
> + return x + 1;
> +}
> +
> +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> +{
> + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> +}
> +
> +static void shpc_set_status(SHPCDevice *shpc,
> + int slot, uint8_t value, uint16_t msk)
> +{
> + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> + pci_word_test_and_clear_mask(status, msk);
> + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> +}
> +
> +static void shpc_interrupt_update(PCIDevice *d)
> +{
> + SHPCDevice *shpc = d->shpc;
> + int slot;
> + int level = 0;
> + uint32_t serr_int;
> + uint32_t int_locator = 0;
> +
> + /* Update interrupt locator register */
> + for (slot = 0; slot < shpc->nslots; ++slot) {
> + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> + if (event & ~disable) {
> + int_locator |= mask;
> + }
> + }
> + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> + int_locator |= SHPC_INT_COMMAND;
> + }
> + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> + qemu_set_irq(d->irq[0], level);
> +}
> +
> +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> +{
> + switch (speed) {
> + case SHPC_SEC_BUS_33:
> + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> + shpc->config[SHPC_SEC_BUS] |= speed;
> + break;
> + default:
> + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> + SHPC_CMD_STATUS_INVALID_MODE);
> + }
> +}
> +
> +void shpc_reset(PCIDevice *d)
> +{
> + SHPCDevice *shpc = d->shpc;
> + int nslots = shpc->nslots;
> + int i;
> + memset(shpc->config, 0, SHPC_SIZEOF(d));
> + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> + SHPC_IDX_TO_PHYSICAL(0) |
> + SHPC_PHYS_NUM_UP |
> + SHPC_PHYS_MRL |
> + SHPC_PHYS_BUTTON);
> + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> + SHPC_SERR_DIS |
> + SHPC_CMD_INT_DIS |
> + SHPC_ARB_SERR_DIS);
> + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> + for (i = 0; i < shpc->nslots; ++i) {
> + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> + SHPC_SLOT_EVENT_PRESENCE |
> + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> + } else {
> + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> + }
> + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> + }
> + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> + shpc_interrupt_update(d);
> +}
> +
> +static void shpc_invalid_command(SHPCDevice *shpc)
> +{
> + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> + SHPC_CMD_STATUS_INVALID_CMD);
> +}
> +
> +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> +{
> + int devfn;
> + int pci_slot = SHPC_IDX_TO_PCI(slot);
> + for (devfn = PCI_DEVFN(pci_slot, 0);
> + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> + ++devfn) {
> + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> + if (affected_dev) {
> + qdev_free(&affected_dev->qdev);
> + }
> + }
> +}
> +
> +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> + uint8_t state, uint8_t power, uint8_t attn)
> +{
> + uint8_t current_state;
> + int slot = SHPC_LOGICAL_TO_IDX(target);
> + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> + shpc_invalid_command(shpc);
> + return;
> + }
> + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> + shpc_invalid_command(shpc);
> + return;
> + }
> +
> + switch (power) {
> + case SHPC_LED_NO:
> + break;
> + default:
> + /* TODO: send event to monitor */
> + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> + }
> + switch (attn) {
> + case SHPC_LED_NO:
> + break;
> + default:
> + /* TODO: send event to monitor */
> + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> + }
> +
> + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> + } else if ((current_state == SHPC_STATE_ENABLED ||
> + current_state == SHPC_STATE_PWRONLY) &&
> + state == SHPC_STATE_DISABLED) {
> + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> + /* TODO: track what monitor requested. */
> + /* Look at LED to figure out whether it's ok to remove the device. */
> + if (power == SHPC_LED_OFF) {
> + shpc_free_devices_in_slot(shpc, slot);
> + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_PRESENCE;
> + }
> + }
> +}
> +
> +static void shpc_command(SHPCDevice *shpc)
> +{
> + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> + uint8_t speed;
> + uint8_t target;
> + uint8_t attn;
> + uint8_t power;
> + uint8_t state;
> + int i;
> +
> + /* Clear status from the previous command. */
> + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> + SHPC_CMD_STATUS_BUSY |
> + SHPC_CMD_STATUS_MRL_OPEN |
> + SHPC_CMD_STATUS_INVALID_CMD |
> + SHPC_CMD_STATUS_INVALID_MODE);
> + switch (code) {
> + case 0x00 ... 0x3f:
> + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> + shpc_slot_command(shpc, target, state, power, attn);
> + break;
> + case 0x40 ... 0x47:
> + speed = code & SHPC_SEC_BUS_MASK;
> + shpc_set_sec_bus_speed(shpc, speed);
> + break;
> + case 0x48:
> + /* Power only all slots */
> + /* first verify no slots are enabled */
> + for (i = 0; i < shpc->nslots; ++i) {
> + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> + if (state == SHPC_STATE_ENABLED) {
> + shpc_invalid_command(shpc);
> + goto done;
> + }
> + }
> + for (i = 0; i < shpc->nslots; ++i) {
> + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> + } else {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> + }
> + }
> + break;
> + case 0x49:
> + /* Enable all slots */
> + /* TODO: Spec says this shall fail if some are already enabled.
> + * This doesn't make sense - why not? a spec bug? */
> + for (i = 0; i < shpc->nslots; ++i) {
> + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> + if (state == SHPC_STATE_ENABLED) {
> + shpc_invalid_command(shpc);
> + goto done;
> + }
> + }
> + for (i = 0; i < shpc->nslots; ++i) {
> + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> + } else {
> + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> + }
> + }
> + break;
> + default:
> + shpc_invalid_command(shpc);
> + break;
> + }
> +done:
> + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> +}
> +
> +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> +{
> + SHPCDevice *shpc = d->shpc;
> + int i;
> + if (addr >= SHPC_SIZEOF(d)) {
> + return;
> + }
> + l = MIN(l, SHPC_SIZEOF(d) - addr);
> +
> + /* TODO: code duplicated from pci.c */
> + for (i = 0; i < l; val >>= 8, ++i) {
> + unsigned a = addr + i;
> + uint8_t wmask = shpc->wmask[a];
> + uint8_t w1cmask = shpc->w1cmask[a];
> + assert(!(wmask & w1cmask));
> + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> + }
> + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> + shpc_command(shpc);
> + }
> + shpc_interrupt_update(d);
> +}
> +
> +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> +{
> + uint64_t val = 0x0;
> + if (addr >= SHPC_SIZEOF(d)) {
> + return val;
> + }
> + l = MIN(l, SHPC_SIZEOF(d) - addr);
> + memcpy(&val, d->shpc->config + addr, l);
> + return val;
> +}
> +
> +/* SHPC Bridge Capability */
> +#define SHPC_CAP_LENGTH 0x08
> +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> +#define SHPC_CAP_CSP_MASK 0x4
> +#define SHPC_CAP_CIP_MASK 0x8
> +
> +static uint8_t shpc_cap_dword(PCIDevice *d)
> +{
> + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> +}
> +
> +/* Update dword data capability register */
> +static void shpc_cap_update_dword(PCIDevice *d)
> +{
> + unsigned data;
> + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> +}
> +
> +/* Add SHPC capability to the config space for the device. */
> +static int shpc_cap_add_config(PCIDevice *d)
> +{
> + uint8_t *config;
> + int config_offset;
> + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> + 0, SHPC_CAP_LENGTH);
> + if (config_offset < 0) {
> + return config_offset;
> + }
> + config = d->config + config_offset;
> +
> + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> + pci_set_byte(config + SHPC_CAP_CxP, 0);
> + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> + d->shpc->cap = config_offset;
> + /* Make dword select and data writeable. */
> + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> + return 0;
> +}
> +
> +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> +{
> + return shpc_read(opaque, addr, size);
> +}
> +
> +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> + uint64_t val, unsigned size)
> +{
> + shpc_write(opaque, addr, val, size);
> +}
> +
> +static const MemoryRegionOps shpc_mmio_ops = {
> + .read = shpc_mmio_read,
> + .write = shpc_mmio_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> + * It's easier to suppport all sizes than worry about it. */
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> + PCIHotplugState hotplug_state)
> +{
> + int pci_slot = PCI_SLOT(affected_dev->devfn);
> + uint8_t state;
> + uint8_t led;
> + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> + SHPCDevice *shpc = d->shpc;
> + int slot = SHPC_PCI_TO_IDX(pci_slot);
> + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> + error_report("Unsupported PCI slot %d for standard hotplug "
> + "controller. Valid slots are between %d and %d.",
> + pci_slot, SHPC_IDX_TO_PCI(0),
> + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> + return -1;
> + }
> + /* Don't send event when device is enabled during qemu machine creation:
> + * it is present on boot, no hotplug event is necessary. We do send an
> + * event when the device is disabled later. */
> + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + return 0;
> + }
> + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> + shpc_free_devices_in_slot(shpc, slot);
> + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_PRESENCE;
> + }
> + } else {
> + /* This could be a cancellation of the previous removal.
> + * We check MRL state to figure out. */
> + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> + SHPC_SLOT_STATUS_PRSNT_MASK);
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_PRESENCE;
> + } else {
> + /* Press attention button to cancel removal */
> + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> + SHPC_SLOT_EVENT_BUTTON;
> + }
> + }
> + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> + shpc_interrupt_update(d);
> + return 0;
> +}
> +
> +/* Initialize the SHPC structure in bridge's BAR. */
> +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> +{
> + int i, ret;
> + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> + shpc->sec_bus = sec_bus;
> + ret = shpc_cap_add_config(d);
> + if (ret) {
> + g_free(d->shpc);
> + return ret;
> + }
> + if (nslots < SHPC_MIN_SLOTS) {
> + return 0;
> + }
> + if (nslots > SHPC_MAX_SLOTS ||
> + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> + /* TODO: report an error mesage that makes sense. */
> + return -EINVAL;
> + }
> + shpc->nslots = nslots;
> + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> +
> + shpc_reset(d);
> +
> + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> +
> + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> + SHPC_INT_DIS |
> + SHPC_SERR_DIS |
> + SHPC_CMD_INT_DIS |
> + SHPC_ARB_SERR_DIS);
> + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> + SHPC_CMD_DETECTED |
> + SHPC_ARB_DETECTED);
> + for (i = 0; i < nslots; ++i) {
> + pci_set_byte(shpc->wmask +
> + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> + SHPC_SLOT_EVENT_PRESENCE |
> + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> + pci_set_byte(shpc->w1cmask +
> + SHPC_SLOT_EVENT_LATCH(i),
> + SHPC_SLOT_EVENT_PRESENCE |
> + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> + SHPC_SLOT_EVENT_BUTTON |
> + SHPC_SLOT_EVENT_MRL |
> + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> + }
> +
> + /* TODO: init cmask */
> + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> + SHPC_SIZEOF(d));
> + shpc_cap_update_dword(d);
> + memory_region_add_subregion(bar, offset, &shpc->mmio);
> + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> + return 0;
> +}
> +
> +int shpc_bar_size(PCIDevice *d)
> +{
> + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> +}
> +
> +void shpc_cleanup(PCIDevice *d)
> +{
> + SHPCDevice *shpc = d->shpc;
> + /* TODO: cleanup config space changes? */
> + g_free(shpc->config);
> + g_free(shpc->cmask);
> + g_free(shpc->wmask);
> + g_free(shpc->w1cmask);
> + memory_region_destroy(&shpc->mmio);
> + g_free(shpc);
> +}
> +
> +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> +{
> + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> + return;
> + }
> + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> + unsigned dword_data;
> + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> + + SHPC_CAP_DWORD_DATA);
> + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> + }
> + /* Update cap dword data in case guest is going to read it. */
> + shpc_cap_update_dword(d);
> +}
> diff --git a/hw/shpc.h b/hw/shpc.h
> new file mode 100644
> index 0000000..389b178
> --- /dev/null
> +++ b/hw/shpc.h
> @@ -0,0 +1,40 @@
> +#ifndef SHPC_H
> +#define SHPC_H
> +
> +#include "qemu-common.h"
> +#include "memory.h"
> +
> +struct SHPCDevice {
> + /* Capability offset in device's config space */
> + int cap;
> +
> + /* # of hot-pluggable slots */
> + int nslots;
> +
> + /* SHPC WRS: working register set */
> + uint8_t *config;
> +
> + /* Used to enable checks on load. Note that writable bits are
> + * never checked even if set in cmask. */
> + uint8_t *cmask;
> +
> + /* Used to implement R/W bytes */
> + uint8_t *wmask;
> +
> + /* Used to implement RW1C(Write 1 to Clear) bytes */
> + uint8_t *w1cmask;
> +
> + /* MMIO for the SHPC BAR */
> + MemoryRegion mmio;
> +
> + /* Bus controlled by this SHPC */
> + PCIBus *sec_bus;
> +};
> +
> +void shpc_reset(PCIDevice *d);
> +int shpc_bar_size(PCIDevice *dev);
> +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> +void shpc_cleanup(PCIDevice *dev);
> +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> +
> +#endif
> diff --git a/qemu-common.h b/qemu-common.h
> index 9b997f8..4ff9c95 100644
> --- a/qemu-common.h
> +++ b/qemu-common.h
> @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> typedef struct EventNotifier EventNotifier;
> typedef struct VirtIODevice VirtIODevice;
> typedef struct QEMUSGList QEMUSGList;
> +typedef struct SHPCDevice SHPCDevice;
>
> typedef uint64_t pcibus_t;
>
> --
> 1.7.9.111.gf3fb0
>
--
yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 1/2] shpc: standard hot plug controller
2012-02-13 10:03 ` [Qemu-devel] " Isaku Yamahata
@ 2012-02-13 11:49 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 11:49 UTC (permalink / raw)
To: Isaku Yamahata
Cc: qemu-devel, kvm, Wen Congyang, Avi Kivity, Kevin Wolf,
Anthony Liguori, berrange
On Mon, Feb 13, 2012 at 07:03:52PM +0900, Isaku Yamahata wrote:
> Oh nice work.
>
> On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> > This adds support for SHPC interface, as defined by PCI Standard
> > Hot-Plug Controller and Subsystem Specification, Rev 1.0
> > http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
> >
> > Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> > SHPC integrated with a host bridge would need more work.
> >
> > All main SHPC features are supported:
> > - MRL sensor
>
> Does this just report latch status? (It seems so.)
What happens is that adding a device closes the latch, removing a device
opens the latch. This simplifies the number of supported configurations
significantly.
> Do you plan to provide interfaces to manipulate the latch?
I didn't plan to do this, and this is non-trivial.
Do you just want this for empty slots? And why?
>
> > - Attention button
> > - Attention indicator
> > - Power indicator
> >
> > Wake on hotplug and serr generation are stubbed out but unused
> > as we don't have interfaces to generate these events ATM.
> >
> > One issue that isn't completely resolved is that qemu currently
> > expects an "eject" interface, which SHPC does not provide: it merely
> > removes the power to device and it's up to the user to remove the device
> > from slot. This patch works around that by ejecting the device
> > when power is removed and power LED goes off.
> >
> > TODO:
> > - migration support
> > - fix dependency on pci_internals.h
>
> If I didn't miss the code,
> - QMP command for pushing attention button.
> - QMP command to get LED status
It's easy to add these, so I'd accept such a patch,
but I wonder why.
> - QMP events for LED on/off
There's also blink :)
>
> thanks,
I'm concerned that a guest can flood the management with such events.
It's better to send a single "LED change" event, then we
can suppress further events until next "get LED status" command.
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > ---
> > Makefile.objs | 1 +
> > hw/pci.h | 6 +
> > hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > hw/shpc.h | 40 ++++
> > qemu-common.h | 1 +
> > 5 files changed, 694 insertions(+), 0 deletions(-)
> > create mode 100644 hw/shpc.c
> > create mode 100644 hw/shpc.h
> >
> > diff --git a/Makefile.objs b/Makefile.objs
> > index 391e524..4546477 100644
> > --- a/Makefile.objs
> > +++ b/Makefile.objs
> > @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> > hw-obj-y += fw_cfg.o
> > hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> > hw-obj-$(CONFIG_PCI) += msix.o msi.o
> > +hw-obj-$(CONFIG_PCI) += shpc.o
> > hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> > hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> > hw-obj-y += watchdog.o
> > diff --git a/hw/pci.h b/hw/pci.h
> > index 33b0b18..756577e 100644
> > --- a/hw/pci.h
> > +++ b/hw/pci.h
> > @@ -125,6 +125,9 @@ enum {
> > /* command register SERR bit enabled */
> > #define QEMU_PCI_CAP_SERR_BITNR 4
> > QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> > + /* Standard hot plug controller. */
> > +#define QEMU_PCI_SHPC_BITNR 5
> > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> > };
> >
> > #define TYPE_PCI_DEVICE "pci-device"
> > @@ -229,6 +232,9 @@ struct PCIDevice {
> > /* PCI Express */
> > PCIExpressDevice exp;
> >
> > + /* SHPC */
> > + SHPCDevice *shpc;
> > +
> > /* Location of option rom */
> > char *romfile;
> > bool has_rom;
> > diff --git a/hw/shpc.c b/hw/shpc.c
> > new file mode 100644
> > index 0000000..4baec29
> > --- /dev/null
> > +++ b/hw/shpc.c
> > @@ -0,0 +1,646 @@
> > +#include <strings.h>
> > +#include <stdint.h>
> > +#include "range.h"
> > +#include "shpc.h"
> > +#include "pci.h"
> > +#include "pci_internals.h"
> > +
> > +/* TODO: model power only and disabled slot states. */
> > +/* TODO: handle SERR and wakeups */
> > +/* TODO: consider enabling 66MHz support */
> > +
> > +/* TODO: remove fully only on state DISABLED and LED off.
> > + * track state to properly record this. */
> > +
> > +/* SHPC Working Register Set */
> > +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> > +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> > +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> > +#define SHPC_NSLOTS 0x0C /* 1 byte */
> > +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> > +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> > +#define SHPC_PHYS_NUM_MAX 0x7ff
> > +#define SHPC_PHYS_NUM_UP 0x1000
> > +#define SHPC_PHYS_MRL 0x4000
> > +#define SHPC_PHYS_BUTTON 0x8000
> > +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> > +#define SHPC_SEC_BUS_33 0x0
> > +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> > +#define SHPC_SEC_BUS_MASK 0x7
> > +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> > +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> > +#define SHPC_PROG_IFC_1_0 0x1
> > +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> > +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> > +#define SHPC_CMD_TRGT_MIN 0x1
> > +#define SHPC_CMD_TRGT_MAX 0x1f
> > +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> > +#define SHPC_CMD_STATUS_BUSY 0x1
> > +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> > +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> > +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> > +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> > +#define SHPC_INT_COMMAND 0x1
> > +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> > +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> > +#define SHPC_INT_DIS 0x1
> > +#define SHPC_SERR_DIS 0x2
> > +#define SHPC_CMD_INT_DIS 0x4
> > +#define SHPC_ARB_SERR_DIS 0x8
> > +#define SHPC_CMD_DETECTED 0x10000
> > +#define SHPC_ARB_DETECTED 0x20000
> > + /* 4 bytes * slot # (start from 0) */
> > +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> > + /* 2 bytes */
> > +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> > +
> > +/* Same slot state masks are used for command and status registers */
> > +#define SHPC_SLOT_STATE_MASK 0x03
> > +#define SHPC_SLOT_STATE_SHIFT \
> > + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> > +
> > +#define SHPC_STATE_NO 0x0
> > +#define SHPC_STATE_PWRONLY 0x1
> > +#define SHPC_STATE_ENABLED 0x2
> > +#define SHPC_STATE_DISABLED 0x3
> > +
> > +#define SHPC_SLOT_PWR_LED_MASK 0xC
> > +#define SHPC_SLOT_PWR_LED_SHIFT \
> > + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> > +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> > +#define SHPC_SLOT_ATTN_LED_SHIFT \
> > + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> > +
> > +#define SHPC_LED_NO 0x0
> > +#define SHPC_LED_ON 0x1
> > +#define SHPC_LED_BLINK 0x2
> > +#define SHPC_LED_OFF 0x3
> > +
> > +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> > +#define SHPC_SLOT_STATUS_BUTTON 0x80
> > +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> > +#define SHPC_SLOT_STATUS_66 0x200
> > +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> > +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> > +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> > +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> > +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> > +
> > +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> > +
> > +
> > + /* 1 byte */
> > +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> > + /* 1 byte */
> > +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> > +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> > +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> > +#define SHPC_SLOT_EVENT_BUTTON 0x04
> > +#define SHPC_SLOT_EVENT_MRL 0x08
> > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> > +/* Bits below are used for Serr/Int disable only */
> > +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> > +
> > +#define SHPC_MIN_SLOTS 1
> > +#define SHPC_MAX_SLOTS 31
> > +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> > +
> > +/* SHPC Slot identifiers */
> > +
> > +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> > + and give the rest of them physical *and* pci numbers starting from 1, so
> > + they match logical numbers. Note: this means that multiple slots must have
> > + different chassis number values, to make chassis+physical slot unique.
> > + TODO: make this configurable? */
> > +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> > +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> > +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> > +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> > +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> > +
> > +static int roundup_pow_of_two(int x)
> > +{
> > + x |= (x >> 1);
> > + x |= (x >> 2);
> > + x |= (x >> 4);
> > + x |= (x >> 8);
> > + x |= (x >> 16);
> > + return x + 1;
> > +}
> > +
> > +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> > +{
> > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> > +}
> > +
> > +static void shpc_set_status(SHPCDevice *shpc,
> > + int slot, uint8_t value, uint16_t msk)
> > +{
> > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > + pci_word_test_and_clear_mask(status, msk);
> > + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> > +}
> > +
> > +static void shpc_interrupt_update(PCIDevice *d)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + int slot;
> > + int level = 0;
> > + uint32_t serr_int;
> > + uint32_t int_locator = 0;
> > +
> > + /* Update interrupt locator register */
> > + for (slot = 0; slot < shpc->nslots; ++slot) {
> > + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> > + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> > + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> > + if (event & ~disable) {
> > + int_locator |= mask;
> > + }
> > + }
> > + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> > + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> > + int_locator |= SHPC_INT_COMMAND;
> > + }
> > + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> > + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> > + qemu_set_irq(d->irq[0], level);
> > +}
> > +
> > +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> > +{
> > + switch (speed) {
> > + case SHPC_SEC_BUS_33:
> > + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> > + shpc->config[SHPC_SEC_BUS] |= speed;
> > + break;
> > + default:
> > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > + SHPC_CMD_STATUS_INVALID_MODE);
> > + }
> > +}
> > +
> > +void shpc_reset(PCIDevice *d)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + int nslots = shpc->nslots;
> > + int i;
> > + memset(shpc->config, 0, SHPC_SIZEOF(d));
> > + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> > + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> > + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> > + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> > + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> > + SHPC_IDX_TO_PHYSICAL(0) |
> > + SHPC_PHYS_NUM_UP |
> > + SHPC_PHYS_MRL |
> > + SHPC_PHYS_BUTTON);
> > + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> > + SHPC_SERR_DIS |
> > + SHPC_CMD_INT_DIS |
> > + SHPC_ARB_SERR_DIS);
> > + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> > + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > + SHPC_SLOT_EVENT_PRESENCE |
> > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> > + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> > + } else {
> > + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> > + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> > + }
> > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> > + }
> > + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> > + shpc_interrupt_update(d);
> > +}
> > +
> > +static void shpc_invalid_command(SHPCDevice *shpc)
> > +{
> > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > + SHPC_CMD_STATUS_INVALID_CMD);
> > +}
> > +
> > +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> > +{
> > + int devfn;
> > + int pci_slot = SHPC_IDX_TO_PCI(slot);
> > + for (devfn = PCI_DEVFN(pci_slot, 0);
> > + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> > + ++devfn) {
> > + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> > + if (affected_dev) {
> > + qdev_free(&affected_dev->qdev);
> > + }
> > + }
> > +}
> > +
> > +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> > + uint8_t state, uint8_t power, uint8_t attn)
> > +{
> > + uint8_t current_state;
> > + int slot = SHPC_LOGICAL_TO_IDX(target);
> > + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> > + shpc_invalid_command(shpc);
> > + return;
> > + }
> > + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> > + shpc_invalid_command(shpc);
> > + return;
> > + }
> > +
> > + switch (power) {
> > + case SHPC_LED_NO:
> > + break;
> > + default:
> > + /* TODO: send event to monitor */
> > + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> > + }
> > + switch (attn) {
> > + case SHPC_LED_NO:
> > + break;
> > + default:
> > + /* TODO: send event to monitor */
> > + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> > + }
> > +
> > + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> > + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > + } else if ((current_state == SHPC_STATE_ENABLED ||
> > + current_state == SHPC_STATE_PWRONLY) &&
> > + state == SHPC_STATE_DISABLED) {
> > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > + /* TODO: track what monitor requested. */
> > + /* Look at LED to figure out whether it's ok to remove the device. */
> > + if (power == SHPC_LED_OFF) {
> > + shpc_free_devices_in_slot(shpc, slot);
> > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_PRESENCE;
> > + }
> > + }
> > +}
> > +
> > +static void shpc_command(SHPCDevice *shpc)
> > +{
> > + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> > + uint8_t speed;
> > + uint8_t target;
> > + uint8_t attn;
> > + uint8_t power;
> > + uint8_t state;
> > + int i;
> > +
> > + /* Clear status from the previous command. */
> > + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> > + SHPC_CMD_STATUS_BUSY |
> > + SHPC_CMD_STATUS_MRL_OPEN |
> > + SHPC_CMD_STATUS_INVALID_CMD |
> > + SHPC_CMD_STATUS_INVALID_MODE);
> > + switch (code) {
> > + case 0x00 ... 0x3f:
> > + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> > + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> > + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> > + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> > + shpc_slot_command(shpc, target, state, power, attn);
> > + break;
> > + case 0x40 ... 0x47:
> > + speed = code & SHPC_SEC_BUS_MASK;
> > + shpc_set_sec_bus_speed(shpc, speed);
> > + break;
> > + case 0x48:
> > + /* Power only all slots */
> > + /* first verify no slots are enabled */
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > + if (state == SHPC_STATE_ENABLED) {
> > + shpc_invalid_command(shpc);
> > + goto done;
> > + }
> > + }
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> > + } else {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > + }
> > + }
> > + break;
> > + case 0x49:
> > + /* Enable all slots */
> > + /* TODO: Spec says this shall fail if some are already enabled.
> > + * This doesn't make sense - why not? a spec bug? */
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > + if (state == SHPC_STATE_ENABLED) {
> > + shpc_invalid_command(shpc);
> > + goto done;
> > + }
> > + }
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> > + } else {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > + }
> > + }
> > + break;
> > + default:
> > + shpc_invalid_command(shpc);
> > + break;
> > + }
> > +done:
> > + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> > +}
> > +
> > +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + int i;
> > + if (addr >= SHPC_SIZEOF(d)) {
> > + return;
> > + }
> > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > +
> > + /* TODO: code duplicated from pci.c */
> > + for (i = 0; i < l; val >>= 8, ++i) {
> > + unsigned a = addr + i;
> > + uint8_t wmask = shpc->wmask[a];
> > + uint8_t w1cmask = shpc->w1cmask[a];
> > + assert(!(wmask & w1cmask));
> > + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> > + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> > + }
> > + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> > + shpc_command(shpc);
> > + }
> > + shpc_interrupt_update(d);
> > +}
> > +
> > +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> > +{
> > + uint64_t val = 0x0;
> > + if (addr >= SHPC_SIZEOF(d)) {
> > + return val;
> > + }
> > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > + memcpy(&val, d->shpc->config + addr, l);
> > + return val;
> > +}
> > +
> > +/* SHPC Bridge Capability */
> > +#define SHPC_CAP_LENGTH 0x08
> > +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> > +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> > +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> > +#define SHPC_CAP_CSP_MASK 0x4
> > +#define SHPC_CAP_CIP_MASK 0x8
> > +
> > +static uint8_t shpc_cap_dword(PCIDevice *d)
> > +{
> > + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> > +}
> > +
> > +/* Update dword data capability register */
> > +static void shpc_cap_update_dword(PCIDevice *d)
> > +{
> > + unsigned data;
> > + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> > + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> > +}
> > +
> > +/* Add SHPC capability to the config space for the device. */
> > +static int shpc_cap_add_config(PCIDevice *d)
> > +{
> > + uint8_t *config;
> > + int config_offset;
> > + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> > + 0, SHPC_CAP_LENGTH);
> > + if (config_offset < 0) {
> > + return config_offset;
> > + }
> > + config = d->config + config_offset;
> > +
> > + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> > + pci_set_byte(config + SHPC_CAP_CxP, 0);
> > + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> > + d->shpc->cap = config_offset;
> > + /* Make dword select and data writeable. */
> > + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> > + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> > + return 0;
> > +}
> > +
> > +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> > + unsigned size)
> > +{
> > + return shpc_read(opaque, addr, size);
> > +}
> > +
> > +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> > + uint64_t val, unsigned size)
> > +{
> > + shpc_write(opaque, addr, val, size);
> > +}
> > +
> > +static const MemoryRegionOps shpc_mmio_ops = {
> > + .read = shpc_mmio_read,
> > + .write = shpc_mmio_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> > + * It's easier to suppport all sizes than worry about it. */
> > + .min_access_size = 1,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> > + PCIHotplugState hotplug_state)
> > +{
> > + int pci_slot = PCI_SLOT(affected_dev->devfn);
> > + uint8_t state;
> > + uint8_t led;
> > + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> > + SHPCDevice *shpc = d->shpc;
> > + int slot = SHPC_PCI_TO_IDX(pci_slot);
> > + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> > + error_report("Unsupported PCI slot %d for standard hotplug "
> > + "controller. Valid slots are between %d and %d.",
> > + pci_slot, SHPC_IDX_TO_PCI(0),
> > + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> > + return -1;
> > + }
> > + /* Don't send event when device is enabled during qemu machine creation:
> > + * it is present on boot, no hotplug event is necessary. We do send an
> > + * event when the device is disabled later. */
> > + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + return 0;
> > + }
> > + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> > + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> > + shpc_free_devices_in_slot(shpc, slot);
> > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_PRESENCE;
> > + }
> > + } else {
> > + /* This could be a cancellation of the previous removal.
> > + * We check MRL state to figure out. */
> > + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_PRESENCE;
> > + } else {
> > + /* Press attention button to cancel removal */
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_BUTTON;
> > + }
> > + }
> > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> > + shpc_interrupt_update(d);
> > + return 0;
> > +}
> > +
> > +/* Initialize the SHPC structure in bridge's BAR. */
> > +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> > +{
> > + int i, ret;
> > + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> > + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> > + shpc->sec_bus = sec_bus;
> > + ret = shpc_cap_add_config(d);
> > + if (ret) {
> > + g_free(d->shpc);
> > + return ret;
> > + }
> > + if (nslots < SHPC_MIN_SLOTS) {
> > + return 0;
> > + }
> > + if (nslots > SHPC_MAX_SLOTS ||
> > + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> > + /* TODO: report an error mesage that makes sense. */
> > + return -EINVAL;
> > + }
> > + shpc->nslots = nslots;
> > + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> > + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> > + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> > + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> > +
> > + shpc_reset(d);
> > +
> > + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> > +
> > + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> > + SHPC_INT_DIS |
> > + SHPC_SERR_DIS |
> > + SHPC_CMD_INT_DIS |
> > + SHPC_ARB_SERR_DIS);
> > + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> > + SHPC_CMD_DETECTED |
> > + SHPC_ARB_DETECTED);
> > + for (i = 0; i < nslots; ++i) {
> > + pci_set_byte(shpc->wmask +
> > + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > + SHPC_SLOT_EVENT_PRESENCE |
> > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > + pci_set_byte(shpc->w1cmask +
> > + SHPC_SLOT_EVENT_LATCH(i),
> > + SHPC_SLOT_EVENT_PRESENCE |
> > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> > + }
> > +
> > + /* TODO: init cmask */
> > + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> > + SHPC_SIZEOF(d));
> > + shpc_cap_update_dword(d);
> > + memory_region_add_subregion(bar, offset, &shpc->mmio);
> > + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> > + return 0;
> > +}
> > +
> > +int shpc_bar_size(PCIDevice *d)
> > +{
> > + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> > +}
> > +
> > +void shpc_cleanup(PCIDevice *d)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + /* TODO: cleanup config space changes? */
> > + g_free(shpc->config);
> > + g_free(shpc->cmask);
> > + g_free(shpc->wmask);
> > + g_free(shpc->w1cmask);
> > + memory_region_destroy(&shpc->mmio);
> > + g_free(shpc);
> > +}
> > +
> > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> > +{
> > + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> > + return;
> > + }
> > + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> > + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> > + unsigned dword_data;
> > + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> > + + SHPC_CAP_DWORD_DATA);
> > + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> > + }
> > + /* Update cap dword data in case guest is going to read it. */
> > + shpc_cap_update_dword(d);
> > +}
> > diff --git a/hw/shpc.h b/hw/shpc.h
> > new file mode 100644
> > index 0000000..389b178
> > --- /dev/null
> > +++ b/hw/shpc.h
> > @@ -0,0 +1,40 @@
> > +#ifndef SHPC_H
> > +#define SHPC_H
> > +
> > +#include "qemu-common.h"
> > +#include "memory.h"
> > +
> > +struct SHPCDevice {
> > + /* Capability offset in device's config space */
> > + int cap;
> > +
> > + /* # of hot-pluggable slots */
> > + int nslots;
> > +
> > + /* SHPC WRS: working register set */
> > + uint8_t *config;
> > +
> > + /* Used to enable checks on load. Note that writable bits are
> > + * never checked even if set in cmask. */
> > + uint8_t *cmask;
> > +
> > + /* Used to implement R/W bytes */
> > + uint8_t *wmask;
> > +
> > + /* Used to implement RW1C(Write 1 to Clear) bytes */
> > + uint8_t *w1cmask;
> > +
> > + /* MMIO for the SHPC BAR */
> > + MemoryRegion mmio;
> > +
> > + /* Bus controlled by this SHPC */
> > + PCIBus *sec_bus;
> > +};
> > +
> > +void shpc_reset(PCIDevice *d);
> > +int shpc_bar_size(PCIDevice *dev);
> > +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> > +void shpc_cleanup(PCIDevice *dev);
> > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> > +
> > +#endif
> > diff --git a/qemu-common.h b/qemu-common.h
> > index 9b997f8..4ff9c95 100644
> > --- a/qemu-common.h
> > +++ b/qemu-common.h
> > @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> > typedef struct EventNotifier EventNotifier;
> > typedef struct VirtIODevice VirtIODevice;
> > typedef struct QEMUSGList QEMUSGList;
> > +typedef struct SHPCDevice SHPCDevice;
> >
> > typedef uint64_t pcibus_t;
> >
> > --
> > 1.7.9.111.gf3fb0
> >
>
> --
> yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 1/2] shpc: standard hot plug controller
@ 2012-02-13 11:49 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 11:49 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: Kevin Wolf, kvm, qemu-devel, Avi Kivity
On Mon, Feb 13, 2012 at 07:03:52PM +0900, Isaku Yamahata wrote:
> Oh nice work.
>
> On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> > This adds support for SHPC interface, as defined by PCI Standard
> > Hot-Plug Controller and Subsystem Specification, Rev 1.0
> > http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
> >
> > Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> > SHPC integrated with a host bridge would need more work.
> >
> > All main SHPC features are supported:
> > - MRL sensor
>
> Does this just report latch status? (It seems so.)
What happens is that adding a device closes the latch, removing a device
opens the latch. This simplifies the number of supported configurations
significantly.
> Do you plan to provide interfaces to manipulate the latch?
I didn't plan to do this, and this is non-trivial.
Do you just want this for empty slots? And why?
>
> > - Attention button
> > - Attention indicator
> > - Power indicator
> >
> > Wake on hotplug and serr generation are stubbed out but unused
> > as we don't have interfaces to generate these events ATM.
> >
> > One issue that isn't completely resolved is that qemu currently
> > expects an "eject" interface, which SHPC does not provide: it merely
> > removes the power to device and it's up to the user to remove the device
> > from slot. This patch works around that by ejecting the device
> > when power is removed and power LED goes off.
> >
> > TODO:
> > - migration support
> > - fix dependency on pci_internals.h
>
> If I didn't miss the code,
> - QMP command for pushing attention button.
> - QMP command to get LED status
It's easy to add these, so I'd accept such a patch,
but I wonder why.
> - QMP events for LED on/off
There's also blink :)
>
> thanks,
I'm concerned that a guest can flood the management with such events.
It's better to send a single "LED change" event, then we
can suppress further events until next "get LED status" command.
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > ---
> > Makefile.objs | 1 +
> > hw/pci.h | 6 +
> > hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > hw/shpc.h | 40 ++++
> > qemu-common.h | 1 +
> > 5 files changed, 694 insertions(+), 0 deletions(-)
> > create mode 100644 hw/shpc.c
> > create mode 100644 hw/shpc.h
> >
> > diff --git a/Makefile.objs b/Makefile.objs
> > index 391e524..4546477 100644
> > --- a/Makefile.objs
> > +++ b/Makefile.objs
> > @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> > hw-obj-y += fw_cfg.o
> > hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> > hw-obj-$(CONFIG_PCI) += msix.o msi.o
> > +hw-obj-$(CONFIG_PCI) += shpc.o
> > hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> > hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> > hw-obj-y += watchdog.o
> > diff --git a/hw/pci.h b/hw/pci.h
> > index 33b0b18..756577e 100644
> > --- a/hw/pci.h
> > +++ b/hw/pci.h
> > @@ -125,6 +125,9 @@ enum {
> > /* command register SERR bit enabled */
> > #define QEMU_PCI_CAP_SERR_BITNR 4
> > QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> > + /* Standard hot plug controller. */
> > +#define QEMU_PCI_SHPC_BITNR 5
> > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> > };
> >
> > #define TYPE_PCI_DEVICE "pci-device"
> > @@ -229,6 +232,9 @@ struct PCIDevice {
> > /* PCI Express */
> > PCIExpressDevice exp;
> >
> > + /* SHPC */
> > + SHPCDevice *shpc;
> > +
> > /* Location of option rom */
> > char *romfile;
> > bool has_rom;
> > diff --git a/hw/shpc.c b/hw/shpc.c
> > new file mode 100644
> > index 0000000..4baec29
> > --- /dev/null
> > +++ b/hw/shpc.c
> > @@ -0,0 +1,646 @@
> > +#include <strings.h>
> > +#include <stdint.h>
> > +#include "range.h"
> > +#include "shpc.h"
> > +#include "pci.h"
> > +#include "pci_internals.h"
> > +
> > +/* TODO: model power only and disabled slot states. */
> > +/* TODO: handle SERR and wakeups */
> > +/* TODO: consider enabling 66MHz support */
> > +
> > +/* TODO: remove fully only on state DISABLED and LED off.
> > + * track state to properly record this. */
> > +
> > +/* SHPC Working Register Set */
> > +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> > +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> > +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> > +#define SHPC_NSLOTS 0x0C /* 1 byte */
> > +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> > +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> > +#define SHPC_PHYS_NUM_MAX 0x7ff
> > +#define SHPC_PHYS_NUM_UP 0x1000
> > +#define SHPC_PHYS_MRL 0x4000
> > +#define SHPC_PHYS_BUTTON 0x8000
> > +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> > +#define SHPC_SEC_BUS_33 0x0
> > +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> > +#define SHPC_SEC_BUS_MASK 0x7
> > +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> > +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> > +#define SHPC_PROG_IFC_1_0 0x1
> > +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> > +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> > +#define SHPC_CMD_TRGT_MIN 0x1
> > +#define SHPC_CMD_TRGT_MAX 0x1f
> > +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> > +#define SHPC_CMD_STATUS_BUSY 0x1
> > +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> > +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> > +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> > +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> > +#define SHPC_INT_COMMAND 0x1
> > +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> > +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> > +#define SHPC_INT_DIS 0x1
> > +#define SHPC_SERR_DIS 0x2
> > +#define SHPC_CMD_INT_DIS 0x4
> > +#define SHPC_ARB_SERR_DIS 0x8
> > +#define SHPC_CMD_DETECTED 0x10000
> > +#define SHPC_ARB_DETECTED 0x20000
> > + /* 4 bytes * slot # (start from 0) */
> > +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> > + /* 2 bytes */
> > +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> > +
> > +/* Same slot state masks are used for command and status registers */
> > +#define SHPC_SLOT_STATE_MASK 0x03
> > +#define SHPC_SLOT_STATE_SHIFT \
> > + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> > +
> > +#define SHPC_STATE_NO 0x0
> > +#define SHPC_STATE_PWRONLY 0x1
> > +#define SHPC_STATE_ENABLED 0x2
> > +#define SHPC_STATE_DISABLED 0x3
> > +
> > +#define SHPC_SLOT_PWR_LED_MASK 0xC
> > +#define SHPC_SLOT_PWR_LED_SHIFT \
> > + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> > +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> > +#define SHPC_SLOT_ATTN_LED_SHIFT \
> > + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> > +
> > +#define SHPC_LED_NO 0x0
> > +#define SHPC_LED_ON 0x1
> > +#define SHPC_LED_BLINK 0x2
> > +#define SHPC_LED_OFF 0x3
> > +
> > +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> > +#define SHPC_SLOT_STATUS_BUTTON 0x80
> > +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> > +#define SHPC_SLOT_STATUS_66 0x200
> > +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> > +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> > +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> > +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> > +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> > +
> > +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> > +
> > +
> > + /* 1 byte */
> > +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> > + /* 1 byte */
> > +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> > +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> > +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> > +#define SHPC_SLOT_EVENT_BUTTON 0x04
> > +#define SHPC_SLOT_EVENT_MRL 0x08
> > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> > +/* Bits below are used for Serr/Int disable only */
> > +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> > +
> > +#define SHPC_MIN_SLOTS 1
> > +#define SHPC_MAX_SLOTS 31
> > +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> > +
> > +/* SHPC Slot identifiers */
> > +
> > +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> > + and give the rest of them physical *and* pci numbers starting from 1, so
> > + they match logical numbers. Note: this means that multiple slots must have
> > + different chassis number values, to make chassis+physical slot unique.
> > + TODO: make this configurable? */
> > +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> > +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> > +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> > +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> > +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> > +
> > +static int roundup_pow_of_two(int x)
> > +{
> > + x |= (x >> 1);
> > + x |= (x >> 2);
> > + x |= (x >> 4);
> > + x |= (x >> 8);
> > + x |= (x >> 16);
> > + return x + 1;
> > +}
> > +
> > +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> > +{
> > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> > +}
> > +
> > +static void shpc_set_status(SHPCDevice *shpc,
> > + int slot, uint8_t value, uint16_t msk)
> > +{
> > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > + pci_word_test_and_clear_mask(status, msk);
> > + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> > +}
> > +
> > +static void shpc_interrupt_update(PCIDevice *d)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + int slot;
> > + int level = 0;
> > + uint32_t serr_int;
> > + uint32_t int_locator = 0;
> > +
> > + /* Update interrupt locator register */
> > + for (slot = 0; slot < shpc->nslots; ++slot) {
> > + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> > + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> > + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> > + if (event & ~disable) {
> > + int_locator |= mask;
> > + }
> > + }
> > + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> > + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> > + int_locator |= SHPC_INT_COMMAND;
> > + }
> > + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> > + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> > + qemu_set_irq(d->irq[0], level);
> > +}
> > +
> > +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> > +{
> > + switch (speed) {
> > + case SHPC_SEC_BUS_33:
> > + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> > + shpc->config[SHPC_SEC_BUS] |= speed;
> > + break;
> > + default:
> > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > + SHPC_CMD_STATUS_INVALID_MODE);
> > + }
> > +}
> > +
> > +void shpc_reset(PCIDevice *d)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + int nslots = shpc->nslots;
> > + int i;
> > + memset(shpc->config, 0, SHPC_SIZEOF(d));
> > + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> > + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> > + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> > + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> > + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> > + SHPC_IDX_TO_PHYSICAL(0) |
> > + SHPC_PHYS_NUM_UP |
> > + SHPC_PHYS_MRL |
> > + SHPC_PHYS_BUTTON);
> > + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> > + SHPC_SERR_DIS |
> > + SHPC_CMD_INT_DIS |
> > + SHPC_ARB_SERR_DIS);
> > + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> > + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > + SHPC_SLOT_EVENT_PRESENCE |
> > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> > + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> > + } else {
> > + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> > + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> > + }
> > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> > + }
> > + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> > + shpc_interrupt_update(d);
> > +}
> > +
> > +static void shpc_invalid_command(SHPCDevice *shpc)
> > +{
> > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > + SHPC_CMD_STATUS_INVALID_CMD);
> > +}
> > +
> > +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> > +{
> > + int devfn;
> > + int pci_slot = SHPC_IDX_TO_PCI(slot);
> > + for (devfn = PCI_DEVFN(pci_slot, 0);
> > + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> > + ++devfn) {
> > + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> > + if (affected_dev) {
> > + qdev_free(&affected_dev->qdev);
> > + }
> > + }
> > +}
> > +
> > +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> > + uint8_t state, uint8_t power, uint8_t attn)
> > +{
> > + uint8_t current_state;
> > + int slot = SHPC_LOGICAL_TO_IDX(target);
> > + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> > + shpc_invalid_command(shpc);
> > + return;
> > + }
> > + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> > + shpc_invalid_command(shpc);
> > + return;
> > + }
> > +
> > + switch (power) {
> > + case SHPC_LED_NO:
> > + break;
> > + default:
> > + /* TODO: send event to monitor */
> > + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> > + }
> > + switch (attn) {
> > + case SHPC_LED_NO:
> > + break;
> > + default:
> > + /* TODO: send event to monitor */
> > + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> > + }
> > +
> > + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> > + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > + } else if ((current_state == SHPC_STATE_ENABLED ||
> > + current_state == SHPC_STATE_PWRONLY) &&
> > + state == SHPC_STATE_DISABLED) {
> > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > + /* TODO: track what monitor requested. */
> > + /* Look at LED to figure out whether it's ok to remove the device. */
> > + if (power == SHPC_LED_OFF) {
> > + shpc_free_devices_in_slot(shpc, slot);
> > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_PRESENCE;
> > + }
> > + }
> > +}
> > +
> > +static void shpc_command(SHPCDevice *shpc)
> > +{
> > + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> > + uint8_t speed;
> > + uint8_t target;
> > + uint8_t attn;
> > + uint8_t power;
> > + uint8_t state;
> > + int i;
> > +
> > + /* Clear status from the previous command. */
> > + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> > + SHPC_CMD_STATUS_BUSY |
> > + SHPC_CMD_STATUS_MRL_OPEN |
> > + SHPC_CMD_STATUS_INVALID_CMD |
> > + SHPC_CMD_STATUS_INVALID_MODE);
> > + switch (code) {
> > + case 0x00 ... 0x3f:
> > + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> > + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> > + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> > + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> > + shpc_slot_command(shpc, target, state, power, attn);
> > + break;
> > + case 0x40 ... 0x47:
> > + speed = code & SHPC_SEC_BUS_MASK;
> > + shpc_set_sec_bus_speed(shpc, speed);
> > + break;
> > + case 0x48:
> > + /* Power only all slots */
> > + /* first verify no slots are enabled */
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > + if (state == SHPC_STATE_ENABLED) {
> > + shpc_invalid_command(shpc);
> > + goto done;
> > + }
> > + }
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> > + } else {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > + }
> > + }
> > + break;
> > + case 0x49:
> > + /* Enable all slots */
> > + /* TODO: Spec says this shall fail if some are already enabled.
> > + * This doesn't make sense - why not? a spec bug? */
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > + if (state == SHPC_STATE_ENABLED) {
> > + shpc_invalid_command(shpc);
> > + goto done;
> > + }
> > + }
> > + for (i = 0; i < shpc->nslots; ++i) {
> > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> > + } else {
> > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > + }
> > + }
> > + break;
> > + default:
> > + shpc_invalid_command(shpc);
> > + break;
> > + }
> > +done:
> > + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> > +}
> > +
> > +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + int i;
> > + if (addr >= SHPC_SIZEOF(d)) {
> > + return;
> > + }
> > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > +
> > + /* TODO: code duplicated from pci.c */
> > + for (i = 0; i < l; val >>= 8, ++i) {
> > + unsigned a = addr + i;
> > + uint8_t wmask = shpc->wmask[a];
> > + uint8_t w1cmask = shpc->w1cmask[a];
> > + assert(!(wmask & w1cmask));
> > + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> > + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> > + }
> > + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> > + shpc_command(shpc);
> > + }
> > + shpc_interrupt_update(d);
> > +}
> > +
> > +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> > +{
> > + uint64_t val = 0x0;
> > + if (addr >= SHPC_SIZEOF(d)) {
> > + return val;
> > + }
> > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > + memcpy(&val, d->shpc->config + addr, l);
> > + return val;
> > +}
> > +
> > +/* SHPC Bridge Capability */
> > +#define SHPC_CAP_LENGTH 0x08
> > +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> > +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> > +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> > +#define SHPC_CAP_CSP_MASK 0x4
> > +#define SHPC_CAP_CIP_MASK 0x8
> > +
> > +static uint8_t shpc_cap_dword(PCIDevice *d)
> > +{
> > + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> > +}
> > +
> > +/* Update dword data capability register */
> > +static void shpc_cap_update_dword(PCIDevice *d)
> > +{
> > + unsigned data;
> > + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> > + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> > +}
> > +
> > +/* Add SHPC capability to the config space for the device. */
> > +static int shpc_cap_add_config(PCIDevice *d)
> > +{
> > + uint8_t *config;
> > + int config_offset;
> > + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> > + 0, SHPC_CAP_LENGTH);
> > + if (config_offset < 0) {
> > + return config_offset;
> > + }
> > + config = d->config + config_offset;
> > +
> > + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> > + pci_set_byte(config + SHPC_CAP_CxP, 0);
> > + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> > + d->shpc->cap = config_offset;
> > + /* Make dword select and data writeable. */
> > + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> > + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> > + return 0;
> > +}
> > +
> > +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> > + unsigned size)
> > +{
> > + return shpc_read(opaque, addr, size);
> > +}
> > +
> > +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> > + uint64_t val, unsigned size)
> > +{
> > + shpc_write(opaque, addr, val, size);
> > +}
> > +
> > +static const MemoryRegionOps shpc_mmio_ops = {
> > + .read = shpc_mmio_read,
> > + .write = shpc_mmio_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> > + * It's easier to suppport all sizes than worry about it. */
> > + .min_access_size = 1,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> > + PCIHotplugState hotplug_state)
> > +{
> > + int pci_slot = PCI_SLOT(affected_dev->devfn);
> > + uint8_t state;
> > + uint8_t led;
> > + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> > + SHPCDevice *shpc = d->shpc;
> > + int slot = SHPC_PCI_TO_IDX(pci_slot);
> > + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> > + error_report("Unsupported PCI slot %d for standard hotplug "
> > + "controller. Valid slots are between %d and %d.",
> > + pci_slot, SHPC_IDX_TO_PCI(0),
> > + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> > + return -1;
> > + }
> > + /* Don't send event when device is enabled during qemu machine creation:
> > + * it is present on boot, no hotplug event is necessary. We do send an
> > + * event when the device is disabled later. */
> > + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + return 0;
> > + }
> > + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> > + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> > + shpc_free_devices_in_slot(shpc, slot);
> > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_PRESENCE;
> > + }
> > + } else {
> > + /* This could be a cancellation of the previous removal.
> > + * We check MRL state to figure out. */
> > + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_PRESENCE;
> > + } else {
> > + /* Press attention button to cancel removal */
> > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > + SHPC_SLOT_EVENT_BUTTON;
> > + }
> > + }
> > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> > + shpc_interrupt_update(d);
> > + return 0;
> > +}
> > +
> > +/* Initialize the SHPC structure in bridge's BAR. */
> > +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> > +{
> > + int i, ret;
> > + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> > + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> > + shpc->sec_bus = sec_bus;
> > + ret = shpc_cap_add_config(d);
> > + if (ret) {
> > + g_free(d->shpc);
> > + return ret;
> > + }
> > + if (nslots < SHPC_MIN_SLOTS) {
> > + return 0;
> > + }
> > + if (nslots > SHPC_MAX_SLOTS ||
> > + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> > + /* TODO: report an error mesage that makes sense. */
> > + return -EINVAL;
> > + }
> > + shpc->nslots = nslots;
> > + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> > + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> > + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> > + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> > +
> > + shpc_reset(d);
> > +
> > + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> > +
> > + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> > + SHPC_INT_DIS |
> > + SHPC_SERR_DIS |
> > + SHPC_CMD_INT_DIS |
> > + SHPC_ARB_SERR_DIS);
> > + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> > + SHPC_CMD_DETECTED |
> > + SHPC_ARB_DETECTED);
> > + for (i = 0; i < nslots; ++i) {
> > + pci_set_byte(shpc->wmask +
> > + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > + SHPC_SLOT_EVENT_PRESENCE |
> > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > + pci_set_byte(shpc->w1cmask +
> > + SHPC_SLOT_EVENT_LATCH(i),
> > + SHPC_SLOT_EVENT_PRESENCE |
> > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > + SHPC_SLOT_EVENT_BUTTON |
> > + SHPC_SLOT_EVENT_MRL |
> > + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> > + }
> > +
> > + /* TODO: init cmask */
> > + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> > + SHPC_SIZEOF(d));
> > + shpc_cap_update_dword(d);
> > + memory_region_add_subregion(bar, offset, &shpc->mmio);
> > + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> > + return 0;
> > +}
> > +
> > +int shpc_bar_size(PCIDevice *d)
> > +{
> > + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> > +}
> > +
> > +void shpc_cleanup(PCIDevice *d)
> > +{
> > + SHPCDevice *shpc = d->shpc;
> > + /* TODO: cleanup config space changes? */
> > + g_free(shpc->config);
> > + g_free(shpc->cmask);
> > + g_free(shpc->wmask);
> > + g_free(shpc->w1cmask);
> > + memory_region_destroy(&shpc->mmio);
> > + g_free(shpc);
> > +}
> > +
> > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> > +{
> > + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> > + return;
> > + }
> > + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> > + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> > + unsigned dword_data;
> > + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> > + + SHPC_CAP_DWORD_DATA);
> > + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> > + }
> > + /* Update cap dword data in case guest is going to read it. */
> > + shpc_cap_update_dword(d);
> > +}
> > diff --git a/hw/shpc.h b/hw/shpc.h
> > new file mode 100644
> > index 0000000..389b178
> > --- /dev/null
> > +++ b/hw/shpc.h
> > @@ -0,0 +1,40 @@
> > +#ifndef SHPC_H
> > +#define SHPC_H
> > +
> > +#include "qemu-common.h"
> > +#include "memory.h"
> > +
> > +struct SHPCDevice {
> > + /* Capability offset in device's config space */
> > + int cap;
> > +
> > + /* # of hot-pluggable slots */
> > + int nslots;
> > +
> > + /* SHPC WRS: working register set */
> > + uint8_t *config;
> > +
> > + /* Used to enable checks on load. Note that writable bits are
> > + * never checked even if set in cmask. */
> > + uint8_t *cmask;
> > +
> > + /* Used to implement R/W bytes */
> > + uint8_t *wmask;
> > +
> > + /* Used to implement RW1C(Write 1 to Clear) bytes */
> > + uint8_t *w1cmask;
> > +
> > + /* MMIO for the SHPC BAR */
> > + MemoryRegion mmio;
> > +
> > + /* Bus controlled by this SHPC */
> > + PCIBus *sec_bus;
> > +};
> > +
> > +void shpc_reset(PCIDevice *d);
> > +int shpc_bar_size(PCIDevice *dev);
> > +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> > +void shpc_cleanup(PCIDevice *dev);
> > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> > +
> > +#endif
> > diff --git a/qemu-common.h b/qemu-common.h
> > index 9b997f8..4ff9c95 100644
> > --- a/qemu-common.h
> > +++ b/qemu-common.h
> > @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> > typedef struct EventNotifier EventNotifier;
> > typedef struct VirtIODevice VirtIODevice;
> > typedef struct QEMUSGList QEMUSGList;
> > +typedef struct SHPCDevice SHPCDevice;
> >
> > typedef uint64_t pcibus_t;
> >
> > --
> > 1.7.9.111.gf3fb0
> >
>
> --
> yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 1/2] shpc: standard hot plug controller
2012-02-13 11:49 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-13 14:30 ` Isaku Yamahata
-1 siblings, 0 replies; 52+ messages in thread
From: Isaku Yamahata @ 2012-02-13 14:30 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qemu-devel, kvm, Wen Congyang, Avi Kivity, Kevin Wolf,
Anthony Liguori, berrange
On Mon, Feb 13, 2012 at 01:49:32PM +0200, Michael S. Tsirkin wrote:
> On Mon, Feb 13, 2012 at 07:03:52PM +0900, Isaku Yamahata wrote:
> > Oh nice work.
> >
> > On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> > > This adds support for SHPC interface, as defined by PCI Standard
> > > Hot-Plug Controller and Subsystem Specification, Rev 1.0
> > > http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
> > >
> > > Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> > > SHPC integrated with a host bridge would need more work.
> > >
> > > All main SHPC features are supported:
> > > - MRL sensor
> >
> > Does this just report latch status? (It seems so.)
>
> What happens is that adding a device closes the latch, removing a device
> opens the latch. This simplifies the number of supported configurations
> significantly.
>
>
> > Do you plan to provide interfaces to manipulate the latch?
>
> I didn't plan to do this, and this is non-trivial.
> Do you just want this for empty slots? And why?
No, I just wondered your plan.
> > > - Attention button
> > > - Attention indicator
> > > - Power indicator
> > >
> > > Wake on hotplug and serr generation are stubbed out but unused
> > > as we don't have interfaces to generate these events ATM.
> > >
> > > One issue that isn't completely resolved is that qemu currently
> > > expects an "eject" interface, which SHPC does not provide: it merely
> > > removes the power to device and it's up to the user to remove the device
> > > from slot. This patch works around that by ejecting the device
> > > when power is removed and power LED goes off.
> > >
> > > TODO:
> > > - migration support
> > > - fix dependency on pci_internals.h
> >
> > If I didn't miss the code,
> > - QMP command for pushing attention button.
> > - QMP command to get LED status
>
> It's easy to add these, so I'd accept such a patch,
> but I wonder why.
My concern is how libvirt/virt-manger (or other UI) presents
slot status to operators/users.
> > - QMP events for LED on/off
>
> There's also blink :)
>
> >
> > thanks,
>
> I'm concerned that a guest can flood the management with such events.
> It's better to send a single "LED change" event, then we
> can suppress further events until next "get LED status" command.
Makes sense.
>
> > > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > > ---
> > > Makefile.objs | 1 +
> > > hw/pci.h | 6 +
> > > hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > > hw/shpc.h | 40 ++++
> > > qemu-common.h | 1 +
> > > 5 files changed, 694 insertions(+), 0 deletions(-)
> > > create mode 100644 hw/shpc.c
> > > create mode 100644 hw/shpc.h
> > >
> > > diff --git a/Makefile.objs b/Makefile.objs
> > > index 391e524..4546477 100644
> > > --- a/Makefile.objs
> > > +++ b/Makefile.objs
> > > @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> > > hw-obj-y += fw_cfg.o
> > > hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> > > hw-obj-$(CONFIG_PCI) += msix.o msi.o
> > > +hw-obj-$(CONFIG_PCI) += shpc.o
> > > hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> > > hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> > > hw-obj-y += watchdog.o
> > > diff --git a/hw/pci.h b/hw/pci.h
> > > index 33b0b18..756577e 100644
> > > --- a/hw/pci.h
> > > +++ b/hw/pci.h
> > > @@ -125,6 +125,9 @@ enum {
> > > /* command register SERR bit enabled */
> > > #define QEMU_PCI_CAP_SERR_BITNR 4
> > > QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> > > + /* Standard hot plug controller. */
> > > +#define QEMU_PCI_SHPC_BITNR 5
> > > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> > > };
> > >
> > > #define TYPE_PCI_DEVICE "pci-device"
> > > @@ -229,6 +232,9 @@ struct PCIDevice {
> > > /* PCI Express */
> > > PCIExpressDevice exp;
> > >
> > > + /* SHPC */
> > > + SHPCDevice *shpc;
> > > +
> > > /* Location of option rom */
> > > char *romfile;
> > > bool has_rom;
> > > diff --git a/hw/shpc.c b/hw/shpc.c
> > > new file mode 100644
> > > index 0000000..4baec29
> > > --- /dev/null
> > > +++ b/hw/shpc.c
> > > @@ -0,0 +1,646 @@
> > > +#include <strings.h>
> > > +#include <stdint.h>
> > > +#include "range.h"
> > > +#include "shpc.h"
> > > +#include "pci.h"
> > > +#include "pci_internals.h"
> > > +
> > > +/* TODO: model power only and disabled slot states. */
> > > +/* TODO: handle SERR and wakeups */
> > > +/* TODO: consider enabling 66MHz support */
> > > +
> > > +/* TODO: remove fully only on state DISABLED and LED off.
> > > + * track state to properly record this. */
> > > +
> > > +/* SHPC Working Register Set */
> > > +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> > > +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> > > +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> > > +#define SHPC_NSLOTS 0x0C /* 1 byte */
> > > +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> > > +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> > > +#define SHPC_PHYS_NUM_MAX 0x7ff
> > > +#define SHPC_PHYS_NUM_UP 0x1000
> > > +#define SHPC_PHYS_MRL 0x4000
> > > +#define SHPC_PHYS_BUTTON 0x8000
> > > +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> > > +#define SHPC_SEC_BUS_33 0x0
> > > +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> > > +#define SHPC_SEC_BUS_MASK 0x7
> > > +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> > > +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> > > +#define SHPC_PROG_IFC_1_0 0x1
> > > +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> > > +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> > > +#define SHPC_CMD_TRGT_MIN 0x1
> > > +#define SHPC_CMD_TRGT_MAX 0x1f
> > > +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> > > +#define SHPC_CMD_STATUS_BUSY 0x1
> > > +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> > > +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> > > +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> > > +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> > > +#define SHPC_INT_COMMAND 0x1
> > > +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> > > +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> > > +#define SHPC_INT_DIS 0x1
> > > +#define SHPC_SERR_DIS 0x2
> > > +#define SHPC_CMD_INT_DIS 0x4
> > > +#define SHPC_ARB_SERR_DIS 0x8
> > > +#define SHPC_CMD_DETECTED 0x10000
> > > +#define SHPC_ARB_DETECTED 0x20000
> > > + /* 4 bytes * slot # (start from 0) */
> > > +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> > > + /* 2 bytes */
> > > +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> > > +
> > > +/* Same slot state masks are used for command and status registers */
> > > +#define SHPC_SLOT_STATE_MASK 0x03
> > > +#define SHPC_SLOT_STATE_SHIFT \
> > > + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> > > +
> > > +#define SHPC_STATE_NO 0x0
> > > +#define SHPC_STATE_PWRONLY 0x1
> > > +#define SHPC_STATE_ENABLED 0x2
> > > +#define SHPC_STATE_DISABLED 0x3
> > > +
> > > +#define SHPC_SLOT_PWR_LED_MASK 0xC
> > > +#define SHPC_SLOT_PWR_LED_SHIFT \
> > > + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> > > +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> > > +#define SHPC_SLOT_ATTN_LED_SHIFT \
> > > + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> > > +
> > > +#define SHPC_LED_NO 0x0
> > > +#define SHPC_LED_ON 0x1
> > > +#define SHPC_LED_BLINK 0x2
> > > +#define SHPC_LED_OFF 0x3
> > > +
> > > +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> > > +#define SHPC_SLOT_STATUS_BUTTON 0x80
> > > +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> > > +#define SHPC_SLOT_STATUS_66 0x200
> > > +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> > > +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> > > +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> > > +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> > > +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> > > +
> > > +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> > > +
> > > +
> > > + /* 1 byte */
> > > +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> > > + /* 1 byte */
> > > +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> > > +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> > > +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> > > +#define SHPC_SLOT_EVENT_BUTTON 0x04
> > > +#define SHPC_SLOT_EVENT_MRL 0x08
> > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> > > +/* Bits below are used for Serr/Int disable only */
> > > +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> > > +
> > > +#define SHPC_MIN_SLOTS 1
> > > +#define SHPC_MAX_SLOTS 31
> > > +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> > > +
> > > +/* SHPC Slot identifiers */
> > > +
> > > +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> > > + and give the rest of them physical *and* pci numbers starting from 1, so
> > > + they match logical numbers. Note: this means that multiple slots must have
> > > + different chassis number values, to make chassis+physical slot unique.
> > > + TODO: make this configurable? */
> > > +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> > > +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> > > +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> > > +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> > > +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> > > +
> > > +static int roundup_pow_of_two(int x)
> > > +{
> > > + x |= (x >> 1);
> > > + x |= (x >> 2);
> > > + x |= (x >> 4);
> > > + x |= (x >> 8);
> > > + x |= (x >> 16);
> > > + return x + 1;
> > > +}
> > > +
> > > +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> > > +{
> > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> > > +}
> > > +
> > > +static void shpc_set_status(SHPCDevice *shpc,
> > > + int slot, uint8_t value, uint16_t msk)
> > > +{
> > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > + pci_word_test_and_clear_mask(status, msk);
> > > + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> > > +}
> > > +
> > > +static void shpc_interrupt_update(PCIDevice *d)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + int slot;
> > > + int level = 0;
> > > + uint32_t serr_int;
> > > + uint32_t int_locator = 0;
> > > +
> > > + /* Update interrupt locator register */
> > > + for (slot = 0; slot < shpc->nslots; ++slot) {
> > > + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> > > + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> > > + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> > > + if (event & ~disable) {
> > > + int_locator |= mask;
> > > + }
> > > + }
> > > + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> > > + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> > > + int_locator |= SHPC_INT_COMMAND;
> > > + }
> > > + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> > > + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> > > + qemu_set_irq(d->irq[0], level);
> > > +}
> > > +
> > > +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> > > +{
> > > + switch (speed) {
> > > + case SHPC_SEC_BUS_33:
> > > + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> > > + shpc->config[SHPC_SEC_BUS] |= speed;
> > > + break;
> > > + default:
> > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > + }
> > > +}
> > > +
> > > +void shpc_reset(PCIDevice *d)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + int nslots = shpc->nslots;
> > > + int i;
> > > + memset(shpc->config, 0, SHPC_SIZEOF(d));
> > > + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> > > + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> > > + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> > > + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> > > + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> > > + SHPC_IDX_TO_PHYSICAL(0) |
> > > + SHPC_PHYS_NUM_UP |
> > > + SHPC_PHYS_MRL |
> > > + SHPC_PHYS_BUTTON);
> > > + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> > > + SHPC_SERR_DIS |
> > > + SHPC_CMD_INT_DIS |
> > > + SHPC_ARB_SERR_DIS);
> > > + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> > > + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > + SHPC_SLOT_EVENT_PRESENCE |
> > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> > > + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> > > + } else {
> > > + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> > > + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> > > + }
> > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> > > + }
> > > + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> > > + shpc_interrupt_update(d);
> > > +}
> > > +
> > > +static void shpc_invalid_command(SHPCDevice *shpc)
> > > +{
> > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > + SHPC_CMD_STATUS_INVALID_CMD);
> > > +}
> > > +
> > > +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> > > +{
> > > + int devfn;
> > > + int pci_slot = SHPC_IDX_TO_PCI(slot);
> > > + for (devfn = PCI_DEVFN(pci_slot, 0);
> > > + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> > > + ++devfn) {
> > > + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> > > + if (affected_dev) {
> > > + qdev_free(&affected_dev->qdev);
> > > + }
> > > + }
> > > +}
> > > +
> > > +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> > > + uint8_t state, uint8_t power, uint8_t attn)
> > > +{
> > > + uint8_t current_state;
> > > + int slot = SHPC_LOGICAL_TO_IDX(target);
> > > + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> > > + shpc_invalid_command(shpc);
> > > + return;
> > > + }
> > > + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> > > + shpc_invalid_command(shpc);
> > > + return;
> > > + }
> > > +
> > > + switch (power) {
> > > + case SHPC_LED_NO:
> > > + break;
> > > + default:
> > > + /* TODO: send event to monitor */
> > > + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> > > + }
> > > + switch (attn) {
> > > + case SHPC_LED_NO:
> > > + break;
> > > + default:
> > > + /* TODO: send event to monitor */
> > > + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> > > + }
> > > +
> > > + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> > > + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > + } else if ((current_state == SHPC_STATE_ENABLED ||
> > > + current_state == SHPC_STATE_PWRONLY) &&
> > > + state == SHPC_STATE_DISABLED) {
> > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > + /* TODO: track what monitor requested. */
> > > + /* Look at LED to figure out whether it's ok to remove the device. */
> > > + if (power == SHPC_LED_OFF) {
> > > + shpc_free_devices_in_slot(shpc, slot);
> > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_PRESENCE;
> > > + }
> > > + }
> > > +}
> > > +
> > > +static void shpc_command(SHPCDevice *shpc)
> > > +{
> > > + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> > > + uint8_t speed;
> > > + uint8_t target;
> > > + uint8_t attn;
> > > + uint8_t power;
> > > + uint8_t state;
> > > + int i;
> > > +
> > > + /* Clear status from the previous command. */
> > > + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> > > + SHPC_CMD_STATUS_BUSY |
> > > + SHPC_CMD_STATUS_MRL_OPEN |
> > > + SHPC_CMD_STATUS_INVALID_CMD |
> > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > + switch (code) {
> > > + case 0x00 ... 0x3f:
> > > + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> > > + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> > > + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> > > + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> > > + shpc_slot_command(shpc, target, state, power, attn);
> > > + break;
> > > + case 0x40 ... 0x47:
> > > + speed = code & SHPC_SEC_BUS_MASK;
> > > + shpc_set_sec_bus_speed(shpc, speed);
> > > + break;
> > > + case 0x48:
> > > + /* Power only all slots */
> > > + /* first verify no slots are enabled */
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > + if (state == SHPC_STATE_ENABLED) {
> > > + shpc_invalid_command(shpc);
> > > + goto done;
> > > + }
> > > + }
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> > > + } else {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > + }
> > > + }
> > > + break;
> > > + case 0x49:
> > > + /* Enable all slots */
> > > + /* TODO: Spec says this shall fail if some are already enabled.
> > > + * This doesn't make sense - why not? a spec bug? */
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > + if (state == SHPC_STATE_ENABLED) {
> > > + shpc_invalid_command(shpc);
> > > + goto done;
> > > + }
> > > + }
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> > > + } else {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > + }
> > > + }
> > > + break;
> > > + default:
> > > + shpc_invalid_command(shpc);
> > > + break;
> > > + }
> > > +done:
> > > + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> > > +}
> > > +
> > > +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + int i;
> > > + if (addr >= SHPC_SIZEOF(d)) {
> > > + return;
> > > + }
> > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > +
> > > + /* TODO: code duplicated from pci.c */
> > > + for (i = 0; i < l; val >>= 8, ++i) {
> > > + unsigned a = addr + i;
> > > + uint8_t wmask = shpc->wmask[a];
> > > + uint8_t w1cmask = shpc->w1cmask[a];
> > > + assert(!(wmask & w1cmask));
> > > + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> > > + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> > > + }
> > > + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> > > + shpc_command(shpc);
> > > + }
> > > + shpc_interrupt_update(d);
> > > +}
> > > +
> > > +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> > > +{
> > > + uint64_t val = 0x0;
> > > + if (addr >= SHPC_SIZEOF(d)) {
> > > + return val;
> > > + }
> > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > + memcpy(&val, d->shpc->config + addr, l);
> > > + return val;
> > > +}
> > > +
> > > +/* SHPC Bridge Capability */
> > > +#define SHPC_CAP_LENGTH 0x08
> > > +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> > > +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> > > +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> > > +#define SHPC_CAP_CSP_MASK 0x4
> > > +#define SHPC_CAP_CIP_MASK 0x8
> > > +
> > > +static uint8_t shpc_cap_dword(PCIDevice *d)
> > > +{
> > > + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> > > +}
> > > +
> > > +/* Update dword data capability register */
> > > +static void shpc_cap_update_dword(PCIDevice *d)
> > > +{
> > > + unsigned data;
> > > + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> > > + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> > > +}
> > > +
> > > +/* Add SHPC capability to the config space for the device. */
> > > +static int shpc_cap_add_config(PCIDevice *d)
> > > +{
> > > + uint8_t *config;
> > > + int config_offset;
> > > + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> > > + 0, SHPC_CAP_LENGTH);
> > > + if (config_offset < 0) {
> > > + return config_offset;
> > > + }
> > > + config = d->config + config_offset;
> > > +
> > > + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> > > + pci_set_byte(config + SHPC_CAP_CxP, 0);
> > > + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> > > + d->shpc->cap = config_offset;
> > > + /* Make dword select and data writeable. */
> > > + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> > > + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> > > + return 0;
> > > +}
> > > +
> > > +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> > > + unsigned size)
> > > +{
> > > + return shpc_read(opaque, addr, size);
> > > +}
> > > +
> > > +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> > > + uint64_t val, unsigned size)
> > > +{
> > > + shpc_write(opaque, addr, val, size);
> > > +}
> > > +
> > > +static const MemoryRegionOps shpc_mmio_ops = {
> > > + .read = shpc_mmio_read,
> > > + .write = shpc_mmio_write,
> > > + .endianness = DEVICE_LITTLE_ENDIAN,
> > > + .valid = {
> > > + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> > > + * It's easier to suppport all sizes than worry about it. */
> > > + .min_access_size = 1,
> > > + .max_access_size = 4,
> > > + },
> > > +};
> > > +
> > > +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> > > + PCIHotplugState hotplug_state)
> > > +{
> > > + int pci_slot = PCI_SLOT(affected_dev->devfn);
> > > + uint8_t state;
> > > + uint8_t led;
> > > + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> > > + SHPCDevice *shpc = d->shpc;
> > > + int slot = SHPC_PCI_TO_IDX(pci_slot);
> > > + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> > > + error_report("Unsupported PCI slot %d for standard hotplug "
> > > + "controller. Valid slots are between %d and %d.",
> > > + pci_slot, SHPC_IDX_TO_PCI(0),
> > > + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> > > + return -1;
> > > + }
> > > + /* Don't send event when device is enabled during qemu machine creation:
> > > + * it is present on boot, no hotplug event is necessary. We do send an
> > > + * event when the device is disabled later. */
> > > + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + return 0;
> > > + }
> > > + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> > > + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> > > + shpc_free_devices_in_slot(shpc, slot);
> > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_PRESENCE;
> > > + }
> > > + } else {
> > > + /* This could be a cancellation of the previous removal.
> > > + * We check MRL state to figure out. */
> > > + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_PRESENCE;
> > > + } else {
> > > + /* Press attention button to cancel removal */
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_BUTTON;
> > > + }
> > > + }
> > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> > > + shpc_interrupt_update(d);
> > > + return 0;
> > > +}
> > > +
> > > +/* Initialize the SHPC structure in bridge's BAR. */
> > > +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> > > +{
> > > + int i, ret;
> > > + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> > > + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> > > + shpc->sec_bus = sec_bus;
> > > + ret = shpc_cap_add_config(d);
> > > + if (ret) {
> > > + g_free(d->shpc);
> > > + return ret;
> > > + }
> > > + if (nslots < SHPC_MIN_SLOTS) {
> > > + return 0;
> > > + }
> > > + if (nslots > SHPC_MAX_SLOTS ||
> > > + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> > > + /* TODO: report an error mesage that makes sense. */
> > > + return -EINVAL;
> > > + }
> > > + shpc->nslots = nslots;
> > > + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> > > + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> > > + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> > > + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> > > +
> > > + shpc_reset(d);
> > > +
> > > + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> > > +
> > > + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> > > + SHPC_INT_DIS |
> > > + SHPC_SERR_DIS |
> > > + SHPC_CMD_INT_DIS |
> > > + SHPC_ARB_SERR_DIS);
> > > + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> > > + SHPC_CMD_DETECTED |
> > > + SHPC_ARB_DETECTED);
> > > + for (i = 0; i < nslots; ++i) {
> > > + pci_set_byte(shpc->wmask +
> > > + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > + SHPC_SLOT_EVENT_PRESENCE |
> > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > + pci_set_byte(shpc->w1cmask +
> > > + SHPC_SLOT_EVENT_LATCH(i),
> > > + SHPC_SLOT_EVENT_PRESENCE |
> > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> > > + }
> > > +
> > > + /* TODO: init cmask */
> > > + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> > > + SHPC_SIZEOF(d));
> > > + shpc_cap_update_dword(d);
> > > + memory_region_add_subregion(bar, offset, &shpc->mmio);
> > > + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> > > + return 0;
> > > +}
> > > +
> > > +int shpc_bar_size(PCIDevice *d)
> > > +{
> > > + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> > > +}
> > > +
> > > +void shpc_cleanup(PCIDevice *d)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + /* TODO: cleanup config space changes? */
> > > + g_free(shpc->config);
> > > + g_free(shpc->cmask);
> > > + g_free(shpc->wmask);
> > > + g_free(shpc->w1cmask);
> > > + memory_region_destroy(&shpc->mmio);
> > > + g_free(shpc);
> > > +}
> > > +
> > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> > > +{
> > > + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> > > + return;
> > > + }
> > > + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> > > + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> > > + unsigned dword_data;
> > > + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> > > + + SHPC_CAP_DWORD_DATA);
> > > + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> > > + }
> > > + /* Update cap dword data in case guest is going to read it. */
> > > + shpc_cap_update_dword(d);
> > > +}
> > > diff --git a/hw/shpc.h b/hw/shpc.h
> > > new file mode 100644
> > > index 0000000..389b178
> > > --- /dev/null
> > > +++ b/hw/shpc.h
> > > @@ -0,0 +1,40 @@
> > > +#ifndef SHPC_H
> > > +#define SHPC_H
> > > +
> > > +#include "qemu-common.h"
> > > +#include "memory.h"
> > > +
> > > +struct SHPCDevice {
> > > + /* Capability offset in device's config space */
> > > + int cap;
> > > +
> > > + /* # of hot-pluggable slots */
> > > + int nslots;
> > > +
> > > + /* SHPC WRS: working register set */
> > > + uint8_t *config;
> > > +
> > > + /* Used to enable checks on load. Note that writable bits are
> > > + * never checked even if set in cmask. */
> > > + uint8_t *cmask;
> > > +
> > > + /* Used to implement R/W bytes */
> > > + uint8_t *wmask;
> > > +
> > > + /* Used to implement RW1C(Write 1 to Clear) bytes */
> > > + uint8_t *w1cmask;
> > > +
> > > + /* MMIO for the SHPC BAR */
> > > + MemoryRegion mmio;
> > > +
> > > + /* Bus controlled by this SHPC */
> > > + PCIBus *sec_bus;
> > > +};
> > > +
> > > +void shpc_reset(PCIDevice *d);
> > > +int shpc_bar_size(PCIDevice *dev);
> > > +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> > > +void shpc_cleanup(PCIDevice *dev);
> > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> > > +
> > > +#endif
> > > diff --git a/qemu-common.h b/qemu-common.h
> > > index 9b997f8..4ff9c95 100644
> > > --- a/qemu-common.h
> > > +++ b/qemu-common.h
> > > @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> > > typedef struct EventNotifier EventNotifier;
> > > typedef struct VirtIODevice VirtIODevice;
> > > typedef struct QEMUSGList QEMUSGList;
> > > +typedef struct SHPCDevice SHPCDevice;
> > >
> > > typedef uint64_t pcibus_t;
> > >
> > > --
> > > 1.7.9.111.gf3fb0
> > >
> >
> > --
> > yamahata
>
--
yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 1/2] shpc: standard hot plug controller
@ 2012-02-13 14:30 ` Isaku Yamahata
0 siblings, 0 replies; 52+ messages in thread
From: Isaku Yamahata @ 2012-02-13 14:30 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Kevin Wolf, kvm, qemu-devel, Avi Kivity
On Mon, Feb 13, 2012 at 01:49:32PM +0200, Michael S. Tsirkin wrote:
> On Mon, Feb 13, 2012 at 07:03:52PM +0900, Isaku Yamahata wrote:
> > Oh nice work.
> >
> > On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> > > This adds support for SHPC interface, as defined by PCI Standard
> > > Hot-Plug Controller and Subsystem Specification, Rev 1.0
> > > http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
> > >
> > > Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> > > SHPC integrated with a host bridge would need more work.
> > >
> > > All main SHPC features are supported:
> > > - MRL sensor
> >
> > Does this just report latch status? (It seems so.)
>
> What happens is that adding a device closes the latch, removing a device
> opens the latch. This simplifies the number of supported configurations
> significantly.
>
>
> > Do you plan to provide interfaces to manipulate the latch?
>
> I didn't plan to do this, and this is non-trivial.
> Do you just want this for empty slots? And why?
No, I just wondered your plan.
> > > - Attention button
> > > - Attention indicator
> > > - Power indicator
> > >
> > > Wake on hotplug and serr generation are stubbed out but unused
> > > as we don't have interfaces to generate these events ATM.
> > >
> > > One issue that isn't completely resolved is that qemu currently
> > > expects an "eject" interface, which SHPC does not provide: it merely
> > > removes the power to device and it's up to the user to remove the device
> > > from slot. This patch works around that by ejecting the device
> > > when power is removed and power LED goes off.
> > >
> > > TODO:
> > > - migration support
> > > - fix dependency on pci_internals.h
> >
> > If I didn't miss the code,
> > - QMP command for pushing attention button.
> > - QMP command to get LED status
>
> It's easy to add these, so I'd accept such a patch,
> but I wonder why.
My concern is how libvirt/virt-manger (or other UI) presents
slot status to operators/users.
> > - QMP events for LED on/off
>
> There's also blink :)
>
> >
> > thanks,
>
> I'm concerned that a guest can flood the management with such events.
> It's better to send a single "LED change" event, then we
> can suppress further events until next "get LED status" command.
Makes sense.
>
> > > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > > ---
> > > Makefile.objs | 1 +
> > > hw/pci.h | 6 +
> > > hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > > hw/shpc.h | 40 ++++
> > > qemu-common.h | 1 +
> > > 5 files changed, 694 insertions(+), 0 deletions(-)
> > > create mode 100644 hw/shpc.c
> > > create mode 100644 hw/shpc.h
> > >
> > > diff --git a/Makefile.objs b/Makefile.objs
> > > index 391e524..4546477 100644
> > > --- a/Makefile.objs
> > > +++ b/Makefile.objs
> > > @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> > > hw-obj-y += fw_cfg.o
> > > hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> > > hw-obj-$(CONFIG_PCI) += msix.o msi.o
> > > +hw-obj-$(CONFIG_PCI) += shpc.o
> > > hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> > > hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> > > hw-obj-y += watchdog.o
> > > diff --git a/hw/pci.h b/hw/pci.h
> > > index 33b0b18..756577e 100644
> > > --- a/hw/pci.h
> > > +++ b/hw/pci.h
> > > @@ -125,6 +125,9 @@ enum {
> > > /* command register SERR bit enabled */
> > > #define QEMU_PCI_CAP_SERR_BITNR 4
> > > QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> > > + /* Standard hot plug controller. */
> > > +#define QEMU_PCI_SHPC_BITNR 5
> > > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> > > };
> > >
> > > #define TYPE_PCI_DEVICE "pci-device"
> > > @@ -229,6 +232,9 @@ struct PCIDevice {
> > > /* PCI Express */
> > > PCIExpressDevice exp;
> > >
> > > + /* SHPC */
> > > + SHPCDevice *shpc;
> > > +
> > > /* Location of option rom */
> > > char *romfile;
> > > bool has_rom;
> > > diff --git a/hw/shpc.c b/hw/shpc.c
> > > new file mode 100644
> > > index 0000000..4baec29
> > > --- /dev/null
> > > +++ b/hw/shpc.c
> > > @@ -0,0 +1,646 @@
> > > +#include <strings.h>
> > > +#include <stdint.h>
> > > +#include "range.h"
> > > +#include "shpc.h"
> > > +#include "pci.h"
> > > +#include "pci_internals.h"
> > > +
> > > +/* TODO: model power only and disabled slot states. */
> > > +/* TODO: handle SERR and wakeups */
> > > +/* TODO: consider enabling 66MHz support */
> > > +
> > > +/* TODO: remove fully only on state DISABLED and LED off.
> > > + * track state to properly record this. */
> > > +
> > > +/* SHPC Working Register Set */
> > > +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> > > +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> > > +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> > > +#define SHPC_NSLOTS 0x0C /* 1 byte */
> > > +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> > > +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> > > +#define SHPC_PHYS_NUM_MAX 0x7ff
> > > +#define SHPC_PHYS_NUM_UP 0x1000
> > > +#define SHPC_PHYS_MRL 0x4000
> > > +#define SHPC_PHYS_BUTTON 0x8000
> > > +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> > > +#define SHPC_SEC_BUS_33 0x0
> > > +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> > > +#define SHPC_SEC_BUS_MASK 0x7
> > > +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> > > +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> > > +#define SHPC_PROG_IFC_1_0 0x1
> > > +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> > > +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> > > +#define SHPC_CMD_TRGT_MIN 0x1
> > > +#define SHPC_CMD_TRGT_MAX 0x1f
> > > +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> > > +#define SHPC_CMD_STATUS_BUSY 0x1
> > > +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> > > +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> > > +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> > > +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> > > +#define SHPC_INT_COMMAND 0x1
> > > +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> > > +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> > > +#define SHPC_INT_DIS 0x1
> > > +#define SHPC_SERR_DIS 0x2
> > > +#define SHPC_CMD_INT_DIS 0x4
> > > +#define SHPC_ARB_SERR_DIS 0x8
> > > +#define SHPC_CMD_DETECTED 0x10000
> > > +#define SHPC_ARB_DETECTED 0x20000
> > > + /* 4 bytes * slot # (start from 0) */
> > > +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> > > + /* 2 bytes */
> > > +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> > > +
> > > +/* Same slot state masks are used for command and status registers */
> > > +#define SHPC_SLOT_STATE_MASK 0x03
> > > +#define SHPC_SLOT_STATE_SHIFT \
> > > + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> > > +
> > > +#define SHPC_STATE_NO 0x0
> > > +#define SHPC_STATE_PWRONLY 0x1
> > > +#define SHPC_STATE_ENABLED 0x2
> > > +#define SHPC_STATE_DISABLED 0x3
> > > +
> > > +#define SHPC_SLOT_PWR_LED_MASK 0xC
> > > +#define SHPC_SLOT_PWR_LED_SHIFT \
> > > + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> > > +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> > > +#define SHPC_SLOT_ATTN_LED_SHIFT \
> > > + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> > > +
> > > +#define SHPC_LED_NO 0x0
> > > +#define SHPC_LED_ON 0x1
> > > +#define SHPC_LED_BLINK 0x2
> > > +#define SHPC_LED_OFF 0x3
> > > +
> > > +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> > > +#define SHPC_SLOT_STATUS_BUTTON 0x80
> > > +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> > > +#define SHPC_SLOT_STATUS_66 0x200
> > > +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> > > +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> > > +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> > > +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> > > +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> > > +
> > > +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> > > +
> > > +
> > > + /* 1 byte */
> > > +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> > > + /* 1 byte */
> > > +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> > > +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> > > +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> > > +#define SHPC_SLOT_EVENT_BUTTON 0x04
> > > +#define SHPC_SLOT_EVENT_MRL 0x08
> > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> > > +/* Bits below are used for Serr/Int disable only */
> > > +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> > > +
> > > +#define SHPC_MIN_SLOTS 1
> > > +#define SHPC_MAX_SLOTS 31
> > > +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> > > +
> > > +/* SHPC Slot identifiers */
> > > +
> > > +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> > > + and give the rest of them physical *and* pci numbers starting from 1, so
> > > + they match logical numbers. Note: this means that multiple slots must have
> > > + different chassis number values, to make chassis+physical slot unique.
> > > + TODO: make this configurable? */
> > > +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> > > +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> > > +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> > > +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> > > +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> > > +
> > > +static int roundup_pow_of_two(int x)
> > > +{
> > > + x |= (x >> 1);
> > > + x |= (x >> 2);
> > > + x |= (x >> 4);
> > > + x |= (x >> 8);
> > > + x |= (x >> 16);
> > > + return x + 1;
> > > +}
> > > +
> > > +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> > > +{
> > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> > > +}
> > > +
> > > +static void shpc_set_status(SHPCDevice *shpc,
> > > + int slot, uint8_t value, uint16_t msk)
> > > +{
> > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > + pci_word_test_and_clear_mask(status, msk);
> > > + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> > > +}
> > > +
> > > +static void shpc_interrupt_update(PCIDevice *d)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + int slot;
> > > + int level = 0;
> > > + uint32_t serr_int;
> > > + uint32_t int_locator = 0;
> > > +
> > > + /* Update interrupt locator register */
> > > + for (slot = 0; slot < shpc->nslots; ++slot) {
> > > + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> > > + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> > > + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> > > + if (event & ~disable) {
> > > + int_locator |= mask;
> > > + }
> > > + }
> > > + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> > > + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> > > + int_locator |= SHPC_INT_COMMAND;
> > > + }
> > > + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> > > + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> > > + qemu_set_irq(d->irq[0], level);
> > > +}
> > > +
> > > +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> > > +{
> > > + switch (speed) {
> > > + case SHPC_SEC_BUS_33:
> > > + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> > > + shpc->config[SHPC_SEC_BUS] |= speed;
> > > + break;
> > > + default:
> > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > + }
> > > +}
> > > +
> > > +void shpc_reset(PCIDevice *d)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + int nslots = shpc->nslots;
> > > + int i;
> > > + memset(shpc->config, 0, SHPC_SIZEOF(d));
> > > + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> > > + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> > > + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> > > + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> > > + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> > > + SHPC_IDX_TO_PHYSICAL(0) |
> > > + SHPC_PHYS_NUM_UP |
> > > + SHPC_PHYS_MRL |
> > > + SHPC_PHYS_BUTTON);
> > > + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> > > + SHPC_SERR_DIS |
> > > + SHPC_CMD_INT_DIS |
> > > + SHPC_ARB_SERR_DIS);
> > > + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> > > + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > + SHPC_SLOT_EVENT_PRESENCE |
> > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> > > + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> > > + } else {
> > > + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> > > + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> > > + }
> > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> > > + }
> > > + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> > > + shpc_interrupt_update(d);
> > > +}
> > > +
> > > +static void shpc_invalid_command(SHPCDevice *shpc)
> > > +{
> > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > + SHPC_CMD_STATUS_INVALID_CMD);
> > > +}
> > > +
> > > +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> > > +{
> > > + int devfn;
> > > + int pci_slot = SHPC_IDX_TO_PCI(slot);
> > > + for (devfn = PCI_DEVFN(pci_slot, 0);
> > > + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> > > + ++devfn) {
> > > + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> > > + if (affected_dev) {
> > > + qdev_free(&affected_dev->qdev);
> > > + }
> > > + }
> > > +}
> > > +
> > > +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> > > + uint8_t state, uint8_t power, uint8_t attn)
> > > +{
> > > + uint8_t current_state;
> > > + int slot = SHPC_LOGICAL_TO_IDX(target);
> > > + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> > > + shpc_invalid_command(shpc);
> > > + return;
> > > + }
> > > + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> > > + shpc_invalid_command(shpc);
> > > + return;
> > > + }
> > > +
> > > + switch (power) {
> > > + case SHPC_LED_NO:
> > > + break;
> > > + default:
> > > + /* TODO: send event to monitor */
> > > + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> > > + }
> > > + switch (attn) {
> > > + case SHPC_LED_NO:
> > > + break;
> > > + default:
> > > + /* TODO: send event to monitor */
> > > + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> > > + }
> > > +
> > > + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> > > + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > + } else if ((current_state == SHPC_STATE_ENABLED ||
> > > + current_state == SHPC_STATE_PWRONLY) &&
> > > + state == SHPC_STATE_DISABLED) {
> > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > + /* TODO: track what monitor requested. */
> > > + /* Look at LED to figure out whether it's ok to remove the device. */
> > > + if (power == SHPC_LED_OFF) {
> > > + shpc_free_devices_in_slot(shpc, slot);
> > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_PRESENCE;
> > > + }
> > > + }
> > > +}
> > > +
> > > +static void shpc_command(SHPCDevice *shpc)
> > > +{
> > > + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> > > + uint8_t speed;
> > > + uint8_t target;
> > > + uint8_t attn;
> > > + uint8_t power;
> > > + uint8_t state;
> > > + int i;
> > > +
> > > + /* Clear status from the previous command. */
> > > + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> > > + SHPC_CMD_STATUS_BUSY |
> > > + SHPC_CMD_STATUS_MRL_OPEN |
> > > + SHPC_CMD_STATUS_INVALID_CMD |
> > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > + switch (code) {
> > > + case 0x00 ... 0x3f:
> > > + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> > > + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> > > + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> > > + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> > > + shpc_slot_command(shpc, target, state, power, attn);
> > > + break;
> > > + case 0x40 ... 0x47:
> > > + speed = code & SHPC_SEC_BUS_MASK;
> > > + shpc_set_sec_bus_speed(shpc, speed);
> > > + break;
> > > + case 0x48:
> > > + /* Power only all slots */
> > > + /* first verify no slots are enabled */
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > + if (state == SHPC_STATE_ENABLED) {
> > > + shpc_invalid_command(shpc);
> > > + goto done;
> > > + }
> > > + }
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> > > + } else {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > + }
> > > + }
> > > + break;
> > > + case 0x49:
> > > + /* Enable all slots */
> > > + /* TODO: Spec says this shall fail if some are already enabled.
> > > + * This doesn't make sense - why not? a spec bug? */
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > + if (state == SHPC_STATE_ENABLED) {
> > > + shpc_invalid_command(shpc);
> > > + goto done;
> > > + }
> > > + }
> > > + for (i = 0; i < shpc->nslots; ++i) {
> > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> > > + } else {
> > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > + }
> > > + }
> > > + break;
> > > + default:
> > > + shpc_invalid_command(shpc);
> > > + break;
> > > + }
> > > +done:
> > > + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> > > +}
> > > +
> > > +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + int i;
> > > + if (addr >= SHPC_SIZEOF(d)) {
> > > + return;
> > > + }
> > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > +
> > > + /* TODO: code duplicated from pci.c */
> > > + for (i = 0; i < l; val >>= 8, ++i) {
> > > + unsigned a = addr + i;
> > > + uint8_t wmask = shpc->wmask[a];
> > > + uint8_t w1cmask = shpc->w1cmask[a];
> > > + assert(!(wmask & w1cmask));
> > > + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> > > + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> > > + }
> > > + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> > > + shpc_command(shpc);
> > > + }
> > > + shpc_interrupt_update(d);
> > > +}
> > > +
> > > +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> > > +{
> > > + uint64_t val = 0x0;
> > > + if (addr >= SHPC_SIZEOF(d)) {
> > > + return val;
> > > + }
> > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > + memcpy(&val, d->shpc->config + addr, l);
> > > + return val;
> > > +}
> > > +
> > > +/* SHPC Bridge Capability */
> > > +#define SHPC_CAP_LENGTH 0x08
> > > +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> > > +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> > > +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> > > +#define SHPC_CAP_CSP_MASK 0x4
> > > +#define SHPC_CAP_CIP_MASK 0x8
> > > +
> > > +static uint8_t shpc_cap_dword(PCIDevice *d)
> > > +{
> > > + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> > > +}
> > > +
> > > +/* Update dword data capability register */
> > > +static void shpc_cap_update_dword(PCIDevice *d)
> > > +{
> > > + unsigned data;
> > > + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> > > + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> > > +}
> > > +
> > > +/* Add SHPC capability to the config space for the device. */
> > > +static int shpc_cap_add_config(PCIDevice *d)
> > > +{
> > > + uint8_t *config;
> > > + int config_offset;
> > > + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> > > + 0, SHPC_CAP_LENGTH);
> > > + if (config_offset < 0) {
> > > + return config_offset;
> > > + }
> > > + config = d->config + config_offset;
> > > +
> > > + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> > > + pci_set_byte(config + SHPC_CAP_CxP, 0);
> > > + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> > > + d->shpc->cap = config_offset;
> > > + /* Make dword select and data writeable. */
> > > + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> > > + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> > > + return 0;
> > > +}
> > > +
> > > +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> > > + unsigned size)
> > > +{
> > > + return shpc_read(opaque, addr, size);
> > > +}
> > > +
> > > +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> > > + uint64_t val, unsigned size)
> > > +{
> > > + shpc_write(opaque, addr, val, size);
> > > +}
> > > +
> > > +static const MemoryRegionOps shpc_mmio_ops = {
> > > + .read = shpc_mmio_read,
> > > + .write = shpc_mmio_write,
> > > + .endianness = DEVICE_LITTLE_ENDIAN,
> > > + .valid = {
> > > + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> > > + * It's easier to suppport all sizes than worry about it. */
> > > + .min_access_size = 1,
> > > + .max_access_size = 4,
> > > + },
> > > +};
> > > +
> > > +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> > > + PCIHotplugState hotplug_state)
> > > +{
> > > + int pci_slot = PCI_SLOT(affected_dev->devfn);
> > > + uint8_t state;
> > > + uint8_t led;
> > > + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> > > + SHPCDevice *shpc = d->shpc;
> > > + int slot = SHPC_PCI_TO_IDX(pci_slot);
> > > + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> > > + error_report("Unsupported PCI slot %d for standard hotplug "
> > > + "controller. Valid slots are between %d and %d.",
> > > + pci_slot, SHPC_IDX_TO_PCI(0),
> > > + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> > > + return -1;
> > > + }
> > > + /* Don't send event when device is enabled during qemu machine creation:
> > > + * it is present on boot, no hotplug event is necessary. We do send an
> > > + * event when the device is disabled later. */
> > > + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + return 0;
> > > + }
> > > + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> > > + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> > > + shpc_free_devices_in_slot(shpc, slot);
> > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_PRESENCE;
> > > + }
> > > + } else {
> > > + /* This could be a cancellation of the previous removal.
> > > + * We check MRL state to figure out. */
> > > + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_PRESENCE;
> > > + } else {
> > > + /* Press attention button to cancel removal */
> > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > + SHPC_SLOT_EVENT_BUTTON;
> > > + }
> > > + }
> > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> > > + shpc_interrupt_update(d);
> > > + return 0;
> > > +}
> > > +
> > > +/* Initialize the SHPC structure in bridge's BAR. */
> > > +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> > > +{
> > > + int i, ret;
> > > + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> > > + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> > > + shpc->sec_bus = sec_bus;
> > > + ret = shpc_cap_add_config(d);
> > > + if (ret) {
> > > + g_free(d->shpc);
> > > + return ret;
> > > + }
> > > + if (nslots < SHPC_MIN_SLOTS) {
> > > + return 0;
> > > + }
> > > + if (nslots > SHPC_MAX_SLOTS ||
> > > + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> > > + /* TODO: report an error mesage that makes sense. */
> > > + return -EINVAL;
> > > + }
> > > + shpc->nslots = nslots;
> > > + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> > > + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> > > + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> > > + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> > > +
> > > + shpc_reset(d);
> > > +
> > > + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> > > +
> > > + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> > > + SHPC_INT_DIS |
> > > + SHPC_SERR_DIS |
> > > + SHPC_CMD_INT_DIS |
> > > + SHPC_ARB_SERR_DIS);
> > > + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> > > + SHPC_CMD_DETECTED |
> > > + SHPC_ARB_DETECTED);
> > > + for (i = 0; i < nslots; ++i) {
> > > + pci_set_byte(shpc->wmask +
> > > + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > + SHPC_SLOT_EVENT_PRESENCE |
> > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > + pci_set_byte(shpc->w1cmask +
> > > + SHPC_SLOT_EVENT_LATCH(i),
> > > + SHPC_SLOT_EVENT_PRESENCE |
> > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > + SHPC_SLOT_EVENT_BUTTON |
> > > + SHPC_SLOT_EVENT_MRL |
> > > + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> > > + }
> > > +
> > > + /* TODO: init cmask */
> > > + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> > > + SHPC_SIZEOF(d));
> > > + shpc_cap_update_dword(d);
> > > + memory_region_add_subregion(bar, offset, &shpc->mmio);
> > > + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> > > + return 0;
> > > +}
> > > +
> > > +int shpc_bar_size(PCIDevice *d)
> > > +{
> > > + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> > > +}
> > > +
> > > +void shpc_cleanup(PCIDevice *d)
> > > +{
> > > + SHPCDevice *shpc = d->shpc;
> > > + /* TODO: cleanup config space changes? */
> > > + g_free(shpc->config);
> > > + g_free(shpc->cmask);
> > > + g_free(shpc->wmask);
> > > + g_free(shpc->w1cmask);
> > > + memory_region_destroy(&shpc->mmio);
> > > + g_free(shpc);
> > > +}
> > > +
> > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> > > +{
> > > + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> > > + return;
> > > + }
> > > + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> > > + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> > > + unsigned dword_data;
> > > + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> > > + + SHPC_CAP_DWORD_DATA);
> > > + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> > > + }
> > > + /* Update cap dword data in case guest is going to read it. */
> > > + shpc_cap_update_dword(d);
> > > +}
> > > diff --git a/hw/shpc.h b/hw/shpc.h
> > > new file mode 100644
> > > index 0000000..389b178
> > > --- /dev/null
> > > +++ b/hw/shpc.h
> > > @@ -0,0 +1,40 @@
> > > +#ifndef SHPC_H
> > > +#define SHPC_H
> > > +
> > > +#include "qemu-common.h"
> > > +#include "memory.h"
> > > +
> > > +struct SHPCDevice {
> > > + /* Capability offset in device's config space */
> > > + int cap;
> > > +
> > > + /* # of hot-pluggable slots */
> > > + int nslots;
> > > +
> > > + /* SHPC WRS: working register set */
> > > + uint8_t *config;
> > > +
> > > + /* Used to enable checks on load. Note that writable bits are
> > > + * never checked even if set in cmask. */
> > > + uint8_t *cmask;
> > > +
> > > + /* Used to implement R/W bytes */
> > > + uint8_t *wmask;
> > > +
> > > + /* Used to implement RW1C(Write 1 to Clear) bytes */
> > > + uint8_t *w1cmask;
> > > +
> > > + /* MMIO for the SHPC BAR */
> > > + MemoryRegion mmio;
> > > +
> > > + /* Bus controlled by this SHPC */
> > > + PCIBus *sec_bus;
> > > +};
> > > +
> > > +void shpc_reset(PCIDevice *d);
> > > +int shpc_bar_size(PCIDevice *dev);
> > > +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> > > +void shpc_cleanup(PCIDevice *dev);
> > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> > > +
> > > +#endif
> > > diff --git a/qemu-common.h b/qemu-common.h
> > > index 9b997f8..4ff9c95 100644
> > > --- a/qemu-common.h
> > > +++ b/qemu-common.h
> > > @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> > > typedef struct EventNotifier EventNotifier;
> > > typedef struct VirtIODevice VirtIODevice;
> > > typedef struct QEMUSGList QEMUSGList;
> > > +typedef struct SHPCDevice SHPCDevice;
> > >
> > > typedef uint64_t pcibus_t;
> > >
> > > --
> > > 1.7.9.111.gf3fb0
> > >
> >
> > --
> > yamahata
>
--
yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 1/2] shpc: standard hot plug controller
2012-02-13 14:30 ` [Qemu-devel] " Isaku Yamahata
@ 2012-02-13 14:49 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 14:49 UTC (permalink / raw)
To: Isaku Yamahata
Cc: qemu-devel, kvm, Wen Congyang, Avi Kivity, Kevin Wolf,
Anthony Liguori, berrange
On Mon, Feb 13, 2012 at 11:30:23PM +0900, Isaku Yamahata wrote:
> On Mon, Feb 13, 2012 at 01:49:32PM +0200, Michael S. Tsirkin wrote:
> > On Mon, Feb 13, 2012 at 07:03:52PM +0900, Isaku Yamahata wrote:
> > > Oh nice work.
> > >
> > > On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> > > > This adds support for SHPC interface, as defined by PCI Standard
> > > > Hot-Plug Controller and Subsystem Specification, Rev 1.0
> > > > http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
> > > >
> > > > Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> > > > SHPC integrated with a host bridge would need more work.
> > > >
> > > > All main SHPC features are supported:
> > > > - MRL sensor
> > >
> > > Does this just report latch status? (It seems so.)
> >
> > What happens is that adding a device closes the latch, removing a device
> > opens the latch. This simplifies the number of supported configurations
> > significantly.
> >
> >
> > > Do you plan to provide interfaces to manipulate the latch?
> >
> > I didn't plan to do this, and this is non-trivial.
> > Do you just want this for empty slots? And why?
>
> No, I just wondered your plan.
>
>
> > > > - Attention button
> > > > - Attention indicator
> > > > - Power indicator
> > > >
> > > > Wake on hotplug and serr generation are stubbed out but unused
> > > > as we don't have interfaces to generate these events ATM.
> > > >
> > > > One issue that isn't completely resolved is that qemu currently
> > > > expects an "eject" interface, which SHPC does not provide: it merely
> > > > removes the power to device and it's up to the user to remove the device
> > > > from slot. This patch works around that by ejecting the device
> > > > when power is removed and power LED goes off.
> > > >
> > > > TODO:
> > > > - migration support
> > > > - fix dependency on pci_internals.h
> > >
> > > If I didn't miss the code,
> > > - QMP command for pushing attention button.
> > > - QMP command to get LED status
> >
> > It's easy to add these, so I'd accept such a patch,
> > but I wonder why.
>
> My concern is how libvirt/virt-manger (or other UI) presents
> slot status to operators/users.
They currently present free/busy status just by looking at info pci.
Maybe that is enough.
My concern is rather with the eject hack above: the add/delete
API maps reasonably to _EJ0 interface, but isn't generic enough
for SHPC. We'll need a better API for that.
> > > - QMP events for LED on/off
> >
> > There's also blink :)
> >
> > >
> > > thanks,
> >
> > I'm concerned that a guest can flood the management with such events.
> > It's better to send a single "LED change" event, then we
> > can suppress further events until next "get LED status" command.
>
> Makes sense.
>
> >
> > > > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > > > ---
> > > > Makefile.objs | 1 +
> > > > hw/pci.h | 6 +
> > > > hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > > > hw/shpc.h | 40 ++++
> > > > qemu-common.h | 1 +
> > > > 5 files changed, 694 insertions(+), 0 deletions(-)
> > > > create mode 100644 hw/shpc.c
> > > > create mode 100644 hw/shpc.h
> > > >
> > > > diff --git a/Makefile.objs b/Makefile.objs
> > > > index 391e524..4546477 100644
> > > > --- a/Makefile.objs
> > > > +++ b/Makefile.objs
> > > > @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> > > > hw-obj-y += fw_cfg.o
> > > > hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> > > > hw-obj-$(CONFIG_PCI) += msix.o msi.o
> > > > +hw-obj-$(CONFIG_PCI) += shpc.o
> > > > hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> > > > hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> > > > hw-obj-y += watchdog.o
> > > > diff --git a/hw/pci.h b/hw/pci.h
> > > > index 33b0b18..756577e 100644
> > > > --- a/hw/pci.h
> > > > +++ b/hw/pci.h
> > > > @@ -125,6 +125,9 @@ enum {
> > > > /* command register SERR bit enabled */
> > > > #define QEMU_PCI_CAP_SERR_BITNR 4
> > > > QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> > > > + /* Standard hot plug controller. */
> > > > +#define QEMU_PCI_SHPC_BITNR 5
> > > > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> > > > };
> > > >
> > > > #define TYPE_PCI_DEVICE "pci-device"
> > > > @@ -229,6 +232,9 @@ struct PCIDevice {
> > > > /* PCI Express */
> > > > PCIExpressDevice exp;
> > > >
> > > > + /* SHPC */
> > > > + SHPCDevice *shpc;
> > > > +
> > > > /* Location of option rom */
> > > > char *romfile;
> > > > bool has_rom;
> > > > diff --git a/hw/shpc.c b/hw/shpc.c
> > > > new file mode 100644
> > > > index 0000000..4baec29
> > > > --- /dev/null
> > > > +++ b/hw/shpc.c
> > > > @@ -0,0 +1,646 @@
> > > > +#include <strings.h>
> > > > +#include <stdint.h>
> > > > +#include "range.h"
> > > > +#include "shpc.h"
> > > > +#include "pci.h"
> > > > +#include "pci_internals.h"
> > > > +
> > > > +/* TODO: model power only and disabled slot states. */
> > > > +/* TODO: handle SERR and wakeups */
> > > > +/* TODO: consider enabling 66MHz support */
> > > > +
> > > > +/* TODO: remove fully only on state DISABLED and LED off.
> > > > + * track state to properly record this. */
> > > > +
> > > > +/* SHPC Working Register Set */
> > > > +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> > > > +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> > > > +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> > > > +#define SHPC_NSLOTS 0x0C /* 1 byte */
> > > > +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> > > > +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> > > > +#define SHPC_PHYS_NUM_MAX 0x7ff
> > > > +#define SHPC_PHYS_NUM_UP 0x1000
> > > > +#define SHPC_PHYS_MRL 0x4000
> > > > +#define SHPC_PHYS_BUTTON 0x8000
> > > > +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> > > > +#define SHPC_SEC_BUS_33 0x0
> > > > +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> > > > +#define SHPC_SEC_BUS_MASK 0x7
> > > > +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> > > > +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> > > > +#define SHPC_PROG_IFC_1_0 0x1
> > > > +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> > > > +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> > > > +#define SHPC_CMD_TRGT_MIN 0x1
> > > > +#define SHPC_CMD_TRGT_MAX 0x1f
> > > > +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> > > > +#define SHPC_CMD_STATUS_BUSY 0x1
> > > > +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> > > > +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> > > > +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> > > > +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> > > > +#define SHPC_INT_COMMAND 0x1
> > > > +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> > > > +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> > > > +#define SHPC_INT_DIS 0x1
> > > > +#define SHPC_SERR_DIS 0x2
> > > > +#define SHPC_CMD_INT_DIS 0x4
> > > > +#define SHPC_ARB_SERR_DIS 0x8
> > > > +#define SHPC_CMD_DETECTED 0x10000
> > > > +#define SHPC_ARB_DETECTED 0x20000
> > > > + /* 4 bytes * slot # (start from 0) */
> > > > +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> > > > + /* 2 bytes */
> > > > +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> > > > +
> > > > +/* Same slot state masks are used for command and status registers */
> > > > +#define SHPC_SLOT_STATE_MASK 0x03
> > > > +#define SHPC_SLOT_STATE_SHIFT \
> > > > + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> > > > +
> > > > +#define SHPC_STATE_NO 0x0
> > > > +#define SHPC_STATE_PWRONLY 0x1
> > > > +#define SHPC_STATE_ENABLED 0x2
> > > > +#define SHPC_STATE_DISABLED 0x3
> > > > +
> > > > +#define SHPC_SLOT_PWR_LED_MASK 0xC
> > > > +#define SHPC_SLOT_PWR_LED_SHIFT \
> > > > + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> > > > +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> > > > +#define SHPC_SLOT_ATTN_LED_SHIFT \
> > > > + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> > > > +
> > > > +#define SHPC_LED_NO 0x0
> > > > +#define SHPC_LED_ON 0x1
> > > > +#define SHPC_LED_BLINK 0x2
> > > > +#define SHPC_LED_OFF 0x3
> > > > +
> > > > +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> > > > +#define SHPC_SLOT_STATUS_BUTTON 0x80
> > > > +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> > > > +#define SHPC_SLOT_STATUS_66 0x200
> > > > +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> > > > +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> > > > +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> > > > +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> > > > +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> > > > +
> > > > +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> > > > +
> > > > +
> > > > + /* 1 byte */
> > > > +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> > > > + /* 1 byte */
> > > > +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> > > > +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> > > > +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> > > > +#define SHPC_SLOT_EVENT_BUTTON 0x04
> > > > +#define SHPC_SLOT_EVENT_MRL 0x08
> > > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> > > > +/* Bits below are used for Serr/Int disable only */
> > > > +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> > > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> > > > +
> > > > +#define SHPC_MIN_SLOTS 1
> > > > +#define SHPC_MAX_SLOTS 31
> > > > +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> > > > +
> > > > +/* SHPC Slot identifiers */
> > > > +
> > > > +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> > > > + and give the rest of them physical *and* pci numbers starting from 1, so
> > > > + they match logical numbers. Note: this means that multiple slots must have
> > > > + different chassis number values, to make chassis+physical slot unique.
> > > > + TODO: make this configurable? */
> > > > +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> > > > +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> > > > +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> > > > +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> > > > +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> > > > +
> > > > +static int roundup_pow_of_two(int x)
> > > > +{
> > > > + x |= (x >> 1);
> > > > + x |= (x >> 2);
> > > > + x |= (x >> 4);
> > > > + x |= (x >> 8);
> > > > + x |= (x >> 16);
> > > > + return x + 1;
> > > > +}
> > > > +
> > > > +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> > > > +{
> > > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > > + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> > > > +}
> > > > +
> > > > +static void shpc_set_status(SHPCDevice *shpc,
> > > > + int slot, uint8_t value, uint16_t msk)
> > > > +{
> > > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > > + pci_word_test_and_clear_mask(status, msk);
> > > > + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> > > > +}
> > > > +
> > > > +static void shpc_interrupt_update(PCIDevice *d)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int slot;
> > > > + int level = 0;
> > > > + uint32_t serr_int;
> > > > + uint32_t int_locator = 0;
> > > > +
> > > > + /* Update interrupt locator register */
> > > > + for (slot = 0; slot < shpc->nslots; ++slot) {
> > > > + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> > > > + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> > > > + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> > > > + if (event & ~disable) {
> > > > + int_locator |= mask;
> > > > + }
> > > > + }
> > > > + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> > > > + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> > > > + int_locator |= SHPC_INT_COMMAND;
> > > > + }
> > > > + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> > > > + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> > > > + qemu_set_irq(d->irq[0], level);
> > > > +}
> > > > +
> > > > +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> > > > +{
> > > > + switch (speed) {
> > > > + case SHPC_SEC_BUS_33:
> > > > + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> > > > + shpc->config[SHPC_SEC_BUS] |= speed;
> > > > + break;
> > > > + default:
> > > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > > + }
> > > > +}
> > > > +
> > > > +void shpc_reset(PCIDevice *d)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int nslots = shpc->nslots;
> > > > + int i;
> > > > + memset(shpc->config, 0, SHPC_SIZEOF(d));
> > > > + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> > > > + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> > > > + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> > > > + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> > > > + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> > > > + SHPC_IDX_TO_PHYSICAL(0) |
> > > > + SHPC_PHYS_NUM_UP |
> > > > + SHPC_PHYS_MRL |
> > > > + SHPC_PHYS_BUTTON);
> > > > + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> > > > + SHPC_SERR_DIS |
> > > > + SHPC_CMD_INT_DIS |
> > > > + SHPC_ARB_SERR_DIS);
> > > > + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> > > > + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > > + SHPC_SLOT_EVENT_PRESENCE |
> > > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > > + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> > > > + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> > > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> > > > + } else {
> > > > + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> > > > + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> > > > + }
> > > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> > > > + }
> > > > + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> > > > + shpc_interrupt_update(d);
> > > > +}
> > > > +
> > > > +static void shpc_invalid_command(SHPCDevice *shpc)
> > > > +{
> > > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > > + SHPC_CMD_STATUS_INVALID_CMD);
> > > > +}
> > > > +
> > > > +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> > > > +{
> > > > + int devfn;
> > > > + int pci_slot = SHPC_IDX_TO_PCI(slot);
> > > > + for (devfn = PCI_DEVFN(pci_slot, 0);
> > > > + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> > > > + ++devfn) {
> > > > + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> > > > + if (affected_dev) {
> > > > + qdev_free(&affected_dev->qdev);
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> > > > + uint8_t state, uint8_t power, uint8_t attn)
> > > > +{
> > > > + uint8_t current_state;
> > > > + int slot = SHPC_LOGICAL_TO_IDX(target);
> > > > + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> > > > + shpc_invalid_command(shpc);
> > > > + return;
> > > > + }
> > > > + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > > + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> > > > + shpc_invalid_command(shpc);
> > > > + return;
> > > > + }
> > > > +
> > > > + switch (power) {
> > > > + case SHPC_LED_NO:
> > > > + break;
> > > > + default:
> > > > + /* TODO: send event to monitor */
> > > > + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> > > > + }
> > > > + switch (attn) {
> > > > + case SHPC_LED_NO:
> > > > + break;
> > > > + default:
> > > > + /* TODO: send event to monitor */
> > > > + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> > > > + }
> > > > +
> > > > + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> > > > + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> > > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > > + } else if ((current_state == SHPC_STATE_ENABLED ||
> > > > + current_state == SHPC_STATE_PWRONLY) &&
> > > > + state == SHPC_STATE_DISABLED) {
> > > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > > + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > > + /* TODO: track what monitor requested. */
> > > > + /* Look at LED to figure out whether it's ok to remove the device. */
> > > > + if (power == SHPC_LED_OFF) {
> > > > + shpc_free_devices_in_slot(shpc, slot);
> > > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_PRESENCE;
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > +static void shpc_command(SHPCDevice *shpc)
> > > > +{
> > > > + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> > > > + uint8_t speed;
> > > > + uint8_t target;
> > > > + uint8_t attn;
> > > > + uint8_t power;
> > > > + uint8_t state;
> > > > + int i;
> > > > +
> > > > + /* Clear status from the previous command. */
> > > > + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> > > > + SHPC_CMD_STATUS_BUSY |
> > > > + SHPC_CMD_STATUS_MRL_OPEN |
> > > > + SHPC_CMD_STATUS_INVALID_CMD |
> > > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > > + switch (code) {
> > > > + case 0x00 ... 0x3f:
> > > > + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> > > > + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> > > > + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> > > > + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> > > > + shpc_slot_command(shpc, target, state, power, attn);
> > > > + break;
> > > > + case 0x40 ... 0x47:
> > > > + speed = code & SHPC_SEC_BUS_MASK;
> > > > + shpc_set_sec_bus_speed(shpc, speed);
> > > > + break;
> > > > + case 0x48:
> > > > + /* Power only all slots */
> > > > + /* first verify no slots are enabled */
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > > + if (state == SHPC_STATE_ENABLED) {
> > > > + shpc_invalid_command(shpc);
> > > > + goto done;
> > > > + }
> > > > + }
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> > > > + } else {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > > + }
> > > > + }
> > > > + break;
> > > > + case 0x49:
> > > > + /* Enable all slots */
> > > > + /* TODO: Spec says this shall fail if some are already enabled.
> > > > + * This doesn't make sense - why not? a spec bug? */
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > > + if (state == SHPC_STATE_ENABLED) {
> > > > + shpc_invalid_command(shpc);
> > > > + goto done;
> > > > + }
> > > > + }
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> > > > + } else {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > > + }
> > > > + }
> > > > + break;
> > > > + default:
> > > > + shpc_invalid_command(shpc);
> > > > + break;
> > > > + }
> > > > +done:
> > > > + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> > > > +}
> > > > +
> > > > +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int i;
> > > > + if (addr >= SHPC_SIZEOF(d)) {
> > > > + return;
> > > > + }
> > > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > > +
> > > > + /* TODO: code duplicated from pci.c */
> > > > + for (i = 0; i < l; val >>= 8, ++i) {
> > > > + unsigned a = addr + i;
> > > > + uint8_t wmask = shpc->wmask[a];
> > > > + uint8_t w1cmask = shpc->w1cmask[a];
> > > > + assert(!(wmask & w1cmask));
> > > > + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> > > > + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> > > > + }
> > > > + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> > > > + shpc_command(shpc);
> > > > + }
> > > > + shpc_interrupt_update(d);
> > > > +}
> > > > +
> > > > +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> > > > +{
> > > > + uint64_t val = 0x0;
> > > > + if (addr >= SHPC_SIZEOF(d)) {
> > > > + return val;
> > > > + }
> > > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > > + memcpy(&val, d->shpc->config + addr, l);
> > > > + return val;
> > > > +}
> > > > +
> > > > +/* SHPC Bridge Capability */
> > > > +#define SHPC_CAP_LENGTH 0x08
> > > > +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> > > > +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> > > > +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> > > > +#define SHPC_CAP_CSP_MASK 0x4
> > > > +#define SHPC_CAP_CIP_MASK 0x8
> > > > +
> > > > +static uint8_t shpc_cap_dword(PCIDevice *d)
> > > > +{
> > > > + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> > > > +}
> > > > +
> > > > +/* Update dword data capability register */
> > > > +static void shpc_cap_update_dword(PCIDevice *d)
> > > > +{
> > > > + unsigned data;
> > > > + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> > > > + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> > > > +}
> > > > +
> > > > +/* Add SHPC capability to the config space for the device. */
> > > > +static int shpc_cap_add_config(PCIDevice *d)
> > > > +{
> > > > + uint8_t *config;
> > > > + int config_offset;
> > > > + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> > > > + 0, SHPC_CAP_LENGTH);
> > > > + if (config_offset < 0) {
> > > > + return config_offset;
> > > > + }
> > > > + config = d->config + config_offset;
> > > > +
> > > > + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> > > > + pci_set_byte(config + SHPC_CAP_CxP, 0);
> > > > + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> > > > + d->shpc->cap = config_offset;
> > > > + /* Make dword select and data writeable. */
> > > > + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> > > > + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> > > > + unsigned size)
> > > > +{
> > > > + return shpc_read(opaque, addr, size);
> > > > +}
> > > > +
> > > > +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> > > > + uint64_t val, unsigned size)
> > > > +{
> > > > + shpc_write(opaque, addr, val, size);
> > > > +}
> > > > +
> > > > +static const MemoryRegionOps shpc_mmio_ops = {
> > > > + .read = shpc_mmio_read,
> > > > + .write = shpc_mmio_write,
> > > > + .endianness = DEVICE_LITTLE_ENDIAN,
> > > > + .valid = {
> > > > + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> > > > + * It's easier to suppport all sizes than worry about it. */
> > > > + .min_access_size = 1,
> > > > + .max_access_size = 4,
> > > > + },
> > > > +};
> > > > +
> > > > +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> > > > + PCIHotplugState hotplug_state)
> > > > +{
> > > > + int pci_slot = PCI_SLOT(affected_dev->devfn);
> > > > + uint8_t state;
> > > > + uint8_t led;
> > > > + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int slot = SHPC_PCI_TO_IDX(pci_slot);
> > > > + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> > > > + error_report("Unsupported PCI slot %d for standard hotplug "
> > > > + "controller. Valid slots are between %d and %d.",
> > > > + pci_slot, SHPC_IDX_TO_PCI(0),
> > > > + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> > > > + return -1;
> > > > + }
> > > > + /* Don't send event when device is enabled during qemu machine creation:
> > > > + * it is present on boot, no hotplug event is necessary. We do send an
> > > > + * event when the device is disabled later. */
> > > > + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> > > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + return 0;
> > > > + }
> > > > + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> > > > + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > > + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > > + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> > > > + shpc_free_devices_in_slot(shpc, slot);
> > > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_PRESENCE;
> > > > + }
> > > > + } else {
> > > > + /* This could be a cancellation of the previous removal.
> > > > + * We check MRL state to figure out. */
> > > > + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> > > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_PRESENCE;
> > > > + } else {
> > > > + /* Press attention button to cancel removal */
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_BUTTON;
> > > > + }
> > > > + }
> > > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> > > > + shpc_interrupt_update(d);
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/* Initialize the SHPC structure in bridge's BAR. */
> > > > +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> > > > +{
> > > > + int i, ret;
> > > > + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> > > > + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> > > > + shpc->sec_bus = sec_bus;
> > > > + ret = shpc_cap_add_config(d);
> > > > + if (ret) {
> > > > + g_free(d->shpc);
> > > > + return ret;
> > > > + }
> > > > + if (nslots < SHPC_MIN_SLOTS) {
> > > > + return 0;
> > > > + }
> > > > + if (nslots > SHPC_MAX_SLOTS ||
> > > > + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> > > > + /* TODO: report an error mesage that makes sense. */
> > > > + return -EINVAL;
> > > > + }
> > > > + shpc->nslots = nslots;
> > > > + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> > > > + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> > > > + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> > > > + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> > > > +
> > > > + shpc_reset(d);
> > > > +
> > > > + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> > > > +
> > > > + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> > > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > > + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> > > > + SHPC_INT_DIS |
> > > > + SHPC_SERR_DIS |
> > > > + SHPC_CMD_INT_DIS |
> > > > + SHPC_ARB_SERR_DIS);
> > > > + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> > > > + SHPC_CMD_DETECTED |
> > > > + SHPC_ARB_DETECTED);
> > > > + for (i = 0; i < nslots; ++i) {
> > > > + pci_set_byte(shpc->wmask +
> > > > + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > > + SHPC_SLOT_EVENT_PRESENCE |
> > > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > > + pci_set_byte(shpc->w1cmask +
> > > > + SHPC_SLOT_EVENT_LATCH(i),
> > > > + SHPC_SLOT_EVENT_PRESENCE |
> > > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> > > > + }
> > > > +
> > > > + /* TODO: init cmask */
> > > > + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> > > > + SHPC_SIZEOF(d));
> > > > + shpc_cap_update_dword(d);
> > > > + memory_region_add_subregion(bar, offset, &shpc->mmio);
> > > > + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int shpc_bar_size(PCIDevice *d)
> > > > +{
> > > > + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> > > > +}
> > > > +
> > > > +void shpc_cleanup(PCIDevice *d)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + /* TODO: cleanup config space changes? */
> > > > + g_free(shpc->config);
> > > > + g_free(shpc->cmask);
> > > > + g_free(shpc->wmask);
> > > > + g_free(shpc->w1cmask);
> > > > + memory_region_destroy(&shpc->mmio);
> > > > + g_free(shpc);
> > > > +}
> > > > +
> > > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> > > > +{
> > > > + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> > > > + return;
> > > > + }
> > > > + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> > > > + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> > > > + unsigned dword_data;
> > > > + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> > > > + + SHPC_CAP_DWORD_DATA);
> > > > + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> > > > + }
> > > > + /* Update cap dword data in case guest is going to read it. */
> > > > + shpc_cap_update_dword(d);
> > > > +}
> > > > diff --git a/hw/shpc.h b/hw/shpc.h
> > > > new file mode 100644
> > > > index 0000000..389b178
> > > > --- /dev/null
> > > > +++ b/hw/shpc.h
> > > > @@ -0,0 +1,40 @@
> > > > +#ifndef SHPC_H
> > > > +#define SHPC_H
> > > > +
> > > > +#include "qemu-common.h"
> > > > +#include "memory.h"
> > > > +
> > > > +struct SHPCDevice {
> > > > + /* Capability offset in device's config space */
> > > > + int cap;
> > > > +
> > > > + /* # of hot-pluggable slots */
> > > > + int nslots;
> > > > +
> > > > + /* SHPC WRS: working register set */
> > > > + uint8_t *config;
> > > > +
> > > > + /* Used to enable checks on load. Note that writable bits are
> > > > + * never checked even if set in cmask. */
> > > > + uint8_t *cmask;
> > > > +
> > > > + /* Used to implement R/W bytes */
> > > > + uint8_t *wmask;
> > > > +
> > > > + /* Used to implement RW1C(Write 1 to Clear) bytes */
> > > > + uint8_t *w1cmask;
> > > > +
> > > > + /* MMIO for the SHPC BAR */
> > > > + MemoryRegion mmio;
> > > > +
> > > > + /* Bus controlled by this SHPC */
> > > > + PCIBus *sec_bus;
> > > > +};
> > > > +
> > > > +void shpc_reset(PCIDevice *d);
> > > > +int shpc_bar_size(PCIDevice *dev);
> > > > +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> > > > +void shpc_cleanup(PCIDevice *dev);
> > > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> > > > +
> > > > +#endif
> > > > diff --git a/qemu-common.h b/qemu-common.h
> > > > index 9b997f8..4ff9c95 100644
> > > > --- a/qemu-common.h
> > > > +++ b/qemu-common.h
> > > > @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> > > > typedef struct EventNotifier EventNotifier;
> > > > typedef struct VirtIODevice VirtIODevice;
> > > > typedef struct QEMUSGList QEMUSGList;
> > > > +typedef struct SHPCDevice SHPCDevice;
> > > >
> > > > typedef uint64_t pcibus_t;
> > > >
> > > > --
> > > > 1.7.9.111.gf3fb0
> > > >
> > >
> > > --
> > > yamahata
> >
>
> --
> yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 1/2] shpc: standard hot plug controller
@ 2012-02-13 14:49 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-13 14:49 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: Kevin Wolf, kvm, qemu-devel, Avi Kivity
On Mon, Feb 13, 2012 at 11:30:23PM +0900, Isaku Yamahata wrote:
> On Mon, Feb 13, 2012 at 01:49:32PM +0200, Michael S. Tsirkin wrote:
> > On Mon, Feb 13, 2012 at 07:03:52PM +0900, Isaku Yamahata wrote:
> > > Oh nice work.
> > >
> > > On Mon, Feb 13, 2012 at 11:15:55AM +0200, Michael S. Tsirkin wrote:
> > > > This adds support for SHPC interface, as defined by PCI Standard
> > > > Hot-Plug Controller and Subsystem Specification, Rev 1.0
> > > > http://www.pcisig.com/specifications/conventional/pci_hot_plug/SHPC_10
> > > >
> > > > Only SHPC intergrated with a PCI-to-PCI bridge is supported,
> > > > SHPC integrated with a host bridge would need more work.
> > > >
> > > > All main SHPC features are supported:
> > > > - MRL sensor
> > >
> > > Does this just report latch status? (It seems so.)
> >
> > What happens is that adding a device closes the latch, removing a device
> > opens the latch. This simplifies the number of supported configurations
> > significantly.
> >
> >
> > > Do you plan to provide interfaces to manipulate the latch?
> >
> > I didn't plan to do this, and this is non-trivial.
> > Do you just want this for empty slots? And why?
>
> No, I just wondered your plan.
>
>
> > > > - Attention button
> > > > - Attention indicator
> > > > - Power indicator
> > > >
> > > > Wake on hotplug and serr generation are stubbed out but unused
> > > > as we don't have interfaces to generate these events ATM.
> > > >
> > > > One issue that isn't completely resolved is that qemu currently
> > > > expects an "eject" interface, which SHPC does not provide: it merely
> > > > removes the power to device and it's up to the user to remove the device
> > > > from slot. This patch works around that by ejecting the device
> > > > when power is removed and power LED goes off.
> > > >
> > > > TODO:
> > > > - migration support
> > > > - fix dependency on pci_internals.h
> > >
> > > If I didn't miss the code,
> > > - QMP command for pushing attention button.
> > > - QMP command to get LED status
> >
> > It's easy to add these, so I'd accept such a patch,
> > but I wonder why.
>
> My concern is how libvirt/virt-manger (or other UI) presents
> slot status to operators/users.
They currently present free/busy status just by looking at info pci.
Maybe that is enough.
My concern is rather with the eject hack above: the add/delete
API maps reasonably to _EJ0 interface, but isn't generic enough
for SHPC. We'll need a better API for that.
> > > - QMP events for LED on/off
> >
> > There's also blink :)
> >
> > >
> > > thanks,
> >
> > I'm concerned that a guest can flood the management with such events.
> > It's better to send a single "LED change" event, then we
> > can suppress further events until next "get LED status" command.
>
> Makes sense.
>
> >
> > > > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > > > ---
> > > > Makefile.objs | 1 +
> > > > hw/pci.h | 6 +
> > > > hw/shpc.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > > > hw/shpc.h | 40 ++++
> > > > qemu-common.h | 1 +
> > > > 5 files changed, 694 insertions(+), 0 deletions(-)
> > > > create mode 100644 hw/shpc.c
> > > > create mode 100644 hw/shpc.h
> > > >
> > > > diff --git a/Makefile.objs b/Makefile.objs
> > > > index 391e524..4546477 100644
> > > > --- a/Makefile.objs
> > > > +++ b/Makefile.objs
> > > > @@ -195,6 +195,7 @@ hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> > > > hw-obj-y += fw_cfg.o
> > > > hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
> > > > hw-obj-$(CONFIG_PCI) += msix.o msi.o
> > > > +hw-obj-$(CONFIG_PCI) += shpc.o
> > > > hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
> > > > hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> > > > hw-obj-y += watchdog.o
> > > > diff --git a/hw/pci.h b/hw/pci.h
> > > > index 33b0b18..756577e 100644
> > > > --- a/hw/pci.h
> > > > +++ b/hw/pci.h
> > > > @@ -125,6 +125,9 @@ enum {
> > > > /* command register SERR bit enabled */
> > > > #define QEMU_PCI_CAP_SERR_BITNR 4
> > > > QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
> > > > + /* Standard hot plug controller. */
> > > > +#define QEMU_PCI_SHPC_BITNR 5
> > > > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
> > > > };
> > > >
> > > > #define TYPE_PCI_DEVICE "pci-device"
> > > > @@ -229,6 +232,9 @@ struct PCIDevice {
> > > > /* PCI Express */
> > > > PCIExpressDevice exp;
> > > >
> > > > + /* SHPC */
> > > > + SHPCDevice *shpc;
> > > > +
> > > > /* Location of option rom */
> > > > char *romfile;
> > > > bool has_rom;
> > > > diff --git a/hw/shpc.c b/hw/shpc.c
> > > > new file mode 100644
> > > > index 0000000..4baec29
> > > > --- /dev/null
> > > > +++ b/hw/shpc.c
> > > > @@ -0,0 +1,646 @@
> > > > +#include <strings.h>
> > > > +#include <stdint.h>
> > > > +#include "range.h"
> > > > +#include "shpc.h"
> > > > +#include "pci.h"
> > > > +#include "pci_internals.h"
> > > > +
> > > > +/* TODO: model power only and disabled slot states. */
> > > > +/* TODO: handle SERR and wakeups */
> > > > +/* TODO: consider enabling 66MHz support */
> > > > +
> > > > +/* TODO: remove fully only on state DISABLED and LED off.
> > > > + * track state to properly record this. */
> > > > +
> > > > +/* SHPC Working Register Set */
> > > > +#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
> > > > +#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
> > > > +#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
> > > > +#define SHPC_NSLOTS 0x0C /* 1 byte */
> > > > +#define SHPC_FIRST_DEV 0x0D /* 1 byte */
> > > > +#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
> > > > +#define SHPC_PHYS_NUM_MAX 0x7ff
> > > > +#define SHPC_PHYS_NUM_UP 0x1000
> > > > +#define SHPC_PHYS_MRL 0x4000
> > > > +#define SHPC_PHYS_BUTTON 0x8000
> > > > +#define SHPC_SEC_BUS 0x10 /* 2 bytes */
> > > > +#define SHPC_SEC_BUS_33 0x0
> > > > +#define SHPC_SEC_BUS_66 0x1 /* Unused */
> > > > +#define SHPC_SEC_BUS_MASK 0x7
> > > > +#define SHPC_MSI_CTL 0x12 /* 1 byte */
> > > > +#define SHPC_PROG_IFC 0x13 /* 1 byte */
> > > > +#define SHPC_PROG_IFC_1_0 0x1
> > > > +#define SHPC_CMD_CODE 0x14 /* 1 byte */
> > > > +#define SHPC_CMD_TRGT 0x15 /* 1 byte */
> > > > +#define SHPC_CMD_TRGT_MIN 0x1
> > > > +#define SHPC_CMD_TRGT_MAX 0x1f
> > > > +#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
> > > > +#define SHPC_CMD_STATUS_BUSY 0x1
> > > > +#define SHPC_CMD_STATUS_MRL_OPEN 0x2
> > > > +#define SHPC_CMD_STATUS_INVALID_CMD 0x4
> > > > +#define SHPC_CMD_STATUS_INVALID_MODE 0x8
> > > > +#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
> > > > +#define SHPC_INT_COMMAND 0x1
> > > > +#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
> > > > +#define SHPC_SERR_INT 0x20 /* 4 bytes */
> > > > +#define SHPC_INT_DIS 0x1
> > > > +#define SHPC_SERR_DIS 0x2
> > > > +#define SHPC_CMD_INT_DIS 0x4
> > > > +#define SHPC_ARB_SERR_DIS 0x8
> > > > +#define SHPC_CMD_DETECTED 0x10000
> > > > +#define SHPC_ARB_DETECTED 0x20000
> > > > + /* 4 bytes * slot # (start from 0) */
> > > > +#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
> > > > + /* 2 bytes */
> > > > +#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
> > > > +
> > > > +/* Same slot state masks are used for command and status registers */
> > > > +#define SHPC_SLOT_STATE_MASK 0x03
> > > > +#define SHPC_SLOT_STATE_SHIFT \
> > > > + (ffs(SHPC_SLOT_STATE_MASK) - 1)
> > > > +
> > > > +#define SHPC_STATE_NO 0x0
> > > > +#define SHPC_STATE_PWRONLY 0x1
> > > > +#define SHPC_STATE_ENABLED 0x2
> > > > +#define SHPC_STATE_DISABLED 0x3
> > > > +
> > > > +#define SHPC_SLOT_PWR_LED_MASK 0xC
> > > > +#define SHPC_SLOT_PWR_LED_SHIFT \
> > > > + (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
> > > > +#define SHPC_SLOT_ATTN_LED_MASK 0x30
> > > > +#define SHPC_SLOT_ATTN_LED_SHIFT \
> > > > + (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
> > > > +
> > > > +#define SHPC_LED_NO 0x0
> > > > +#define SHPC_LED_ON 0x1
> > > > +#define SHPC_LED_BLINK 0x2
> > > > +#define SHPC_LED_OFF 0x3
> > > > +
> > > > +#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
> > > > +#define SHPC_SLOT_STATUS_BUTTON 0x80
> > > > +#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
> > > > +#define SHPC_SLOT_STATUS_66 0x200
> > > > +#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
> > > > +#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
> > > > +#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
> > > > +#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
> > > > +#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
> > > > +
> > > > +#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
> > > > +
> > > > +
> > > > + /* 1 byte */
> > > > +#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
> > > > + /* 1 byte */
> > > > +#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
> > > > +#define SHPC_SLOT_EVENT_PRESENCE 0x01
> > > > +#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
> > > > +#define SHPC_SLOT_EVENT_BUTTON 0x04
> > > > +#define SHPC_SLOT_EVENT_MRL 0x08
> > > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
> > > > +/* Bits below are used for Serr/Int disable only */
> > > > +#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
> > > > +#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
> > > > +
> > > > +#define SHPC_MIN_SLOTS 1
> > > > +#define SHPC_MAX_SLOTS 31
> > > > +#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
> > > > +
> > > > +/* SHPC Slot identifiers */
> > > > +
> > > > +/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
> > > > + and give the rest of them physical *and* pci numbers starting from 1, so
> > > > + they match logical numbers. Note: this means that multiple slots must have
> > > > + different chassis number values, to make chassis+physical slot unique.
> > > > + TODO: make this configurable? */
> > > > +#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
> > > > +#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
> > > > +#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
> > > > +#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
> > > > +#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
> > > > +
> > > > +static int roundup_pow_of_two(int x)
> > > > +{
> > > > + x |= (x >> 1);
> > > > + x |= (x >> 2);
> > > > + x |= (x >> 4);
> > > > + x |= (x >> 8);
> > > > + x |= (x >> 16);
> > > > + return x + 1;
> > > > +}
> > > > +
> > > > +static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
> > > > +{
> > > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > > + return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
> > > > +}
> > > > +
> > > > +static void shpc_set_status(SHPCDevice *shpc,
> > > > + int slot, uint8_t value, uint16_t msk)
> > > > +{
> > > > + uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
> > > > + pci_word_test_and_clear_mask(status, msk);
> > > > + pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
> > > > +}
> > > > +
> > > > +static void shpc_interrupt_update(PCIDevice *d)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int slot;
> > > > + int level = 0;
> > > > + uint32_t serr_int;
> > > > + uint32_t int_locator = 0;
> > > > +
> > > > + /* Update interrupt locator register */
> > > > + for (slot = 0; slot < shpc->nslots; ++slot) {
> > > > + uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
> > > > + uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
> > > > + uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
> > > > + if (event & ~disable) {
> > > > + int_locator |= mask;
> > > > + }
> > > > + }
> > > > + serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
> > > > + if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
> > > > + int_locator |= SHPC_INT_COMMAND;
> > > > + }
> > > > + pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
> > > > + level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
> > > > + qemu_set_irq(d->irq[0], level);
> > > > +}
> > > > +
> > > > +static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
> > > > +{
> > > > + switch (speed) {
> > > > + case SHPC_SEC_BUS_33:
> > > > + shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
> > > > + shpc->config[SHPC_SEC_BUS] |= speed;
> > > > + break;
> > > > + default:
> > > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > > + }
> > > > +}
> > > > +
> > > > +void shpc_reset(PCIDevice *d)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int nslots = shpc->nslots;
> > > > + int i;
> > > > + memset(shpc->config, 0, SHPC_SIZEOF(d));
> > > > + pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
> > > > + pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
> > > > + pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
> > > > + pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
> > > > + pci_set_word(shpc->config + SHPC_PHYS_SLOT,
> > > > + SHPC_IDX_TO_PHYSICAL(0) |
> > > > + SHPC_PHYS_NUM_UP |
> > > > + SHPC_PHYS_MRL |
> > > > + SHPC_PHYS_BUTTON);
> > > > + pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
> > > > + SHPC_SERR_DIS |
> > > > + SHPC_CMD_INT_DIS |
> > > > + SHPC_ARB_SERR_DIS);
> > > > + pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
> > > > + pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + pci_set_word(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > > + SHPC_SLOT_EVENT_PRESENCE |
> > > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > > + if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
> > > > + shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
> > > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
> > > > + } else {
> > > > + shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
> > > > + shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
> > > > + }
> > > > + shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
> > > > + }
> > > > + shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
> > > > + shpc_interrupt_update(d);
> > > > +}
> > > > +
> > > > +static void shpc_invalid_command(SHPCDevice *shpc)
> > > > +{
> > > > + pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
> > > > + SHPC_CMD_STATUS_INVALID_CMD);
> > > > +}
> > > > +
> > > > +static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
> > > > +{
> > > > + int devfn;
> > > > + int pci_slot = SHPC_IDX_TO_PCI(slot);
> > > > + for (devfn = PCI_DEVFN(pci_slot, 0);
> > > > + devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
> > > > + ++devfn) {
> > > > + PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
> > > > + if (affected_dev) {
> > > > + qdev_free(&affected_dev->qdev);
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > +static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
> > > > + uint8_t state, uint8_t power, uint8_t attn)
> > > > +{
> > > > + uint8_t current_state;
> > > > + int slot = SHPC_LOGICAL_TO_IDX(target);
> > > > + if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
> > > > + shpc_invalid_command(shpc);
> > > > + return;
> > > > + }
> > > > + current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > > + if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
> > > > + shpc_invalid_command(shpc);
> > > > + return;
> > > > + }
> > > > +
> > > > + switch (power) {
> > > > + case SHPC_LED_NO:
> > > > + break;
> > > > + default:
> > > > + /* TODO: send event to monitor */
> > > > + shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
> > > > + }
> > > > + switch (attn) {
> > > > + case SHPC_LED_NO:
> > > > + break;
> > > > + default:
> > > > + /* TODO: send event to monitor */
> > > > + shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
> > > > + }
> > > > +
> > > > + if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
> > > > + (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
> > > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > > + } else if ((current_state == SHPC_STATE_ENABLED ||
> > > > + current_state == SHPC_STATE_PWRONLY) &&
> > > > + state == SHPC_STATE_DISABLED) {
> > > > + shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
> > > > + power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > > + /* TODO: track what monitor requested. */
> > > > + /* Look at LED to figure out whether it's ok to remove the device. */
> > > > + if (power == SHPC_LED_OFF) {
> > > > + shpc_free_devices_in_slot(shpc, slot);
> > > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_PRESENCE;
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > +static void shpc_command(SHPCDevice *shpc)
> > > > +{
> > > > + uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
> > > > + uint8_t speed;
> > > > + uint8_t target;
> > > > + uint8_t attn;
> > > > + uint8_t power;
> > > > + uint8_t state;
> > > > + int i;
> > > > +
> > > > + /* Clear status from the previous command. */
> > > > + pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
> > > > + SHPC_CMD_STATUS_BUSY |
> > > > + SHPC_CMD_STATUS_MRL_OPEN |
> > > > + SHPC_CMD_STATUS_INVALID_CMD |
> > > > + SHPC_CMD_STATUS_INVALID_MODE);
> > > > + switch (code) {
> > > > + case 0x00 ... 0x3f:
> > > > + target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
> > > > + state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
> > > > + power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
> > > > + attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
> > > > + shpc_slot_command(shpc, target, state, power, attn);
> > > > + break;
> > > > + case 0x40 ... 0x47:
> > > > + speed = code & SHPC_SEC_BUS_MASK;
> > > > + shpc_set_sec_bus_speed(shpc, speed);
> > > > + break;
> > > > + case 0x48:
> > > > + /* Power only all slots */
> > > > + /* first verify no slots are enabled */
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > > + if (state == SHPC_STATE_ENABLED) {
> > > > + shpc_invalid_command(shpc);
> > > > + goto done;
> > > > + }
> > > > + }
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
> > > > + } else {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > > + }
> > > > + }
> > > > + break;
> > > > + case 0x49:
> > > > + /* Enable all slots */
> > > > + /* TODO: Spec says this shall fail if some are already enabled.
> > > > + * This doesn't make sense - why not? a spec bug? */
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
> > > > + if (state == SHPC_STATE_ENABLED) {
> > > > + shpc_invalid_command(shpc);
> > > > + goto done;
> > > > + }
> > > > + }
> > > > + for (i = 0; i < shpc->nslots; ++i) {
> > > > + if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
> > > > + } else {
> > > > + shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
> > > > + SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
> > > > + }
> > > > + }
> > > > + break;
> > > > + default:
> > > > + shpc_invalid_command(shpc);
> > > > + break;
> > > > + }
> > > > +done:
> > > > + pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
> > > > +}
> > > > +
> > > > +static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int i;
> > > > + if (addr >= SHPC_SIZEOF(d)) {
> > > > + return;
> > > > + }
> > > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > > +
> > > > + /* TODO: code duplicated from pci.c */
> > > > + for (i = 0; i < l; val >>= 8, ++i) {
> > > > + unsigned a = addr + i;
> > > > + uint8_t wmask = shpc->wmask[a];
> > > > + uint8_t w1cmask = shpc->w1cmask[a];
> > > > + assert(!(wmask & w1cmask));
> > > > + shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
> > > > + shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
> > > > + }
> > > > + if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
> > > > + shpc_command(shpc);
> > > > + }
> > > > + shpc_interrupt_update(d);
> > > > +}
> > > > +
> > > > +static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
> > > > +{
> > > > + uint64_t val = 0x0;
> > > > + if (addr >= SHPC_SIZEOF(d)) {
> > > > + return val;
> > > > + }
> > > > + l = MIN(l, SHPC_SIZEOF(d) - addr);
> > > > + memcpy(&val, d->shpc->config + addr, l);
> > > > + return val;
> > > > +}
> > > > +
> > > > +/* SHPC Bridge Capability */
> > > > +#define SHPC_CAP_LENGTH 0x08
> > > > +#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
> > > > +#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
> > > > +#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
> > > > +#define SHPC_CAP_CSP_MASK 0x4
> > > > +#define SHPC_CAP_CIP_MASK 0x8
> > > > +
> > > > +static uint8_t shpc_cap_dword(PCIDevice *d)
> > > > +{
> > > > + return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
> > > > +}
> > > > +
> > > > +/* Update dword data capability register */
> > > > +static void shpc_cap_update_dword(PCIDevice *d)
> > > > +{
> > > > + unsigned data;
> > > > + data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
> > > > + pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
> > > > +}
> > > > +
> > > > +/* Add SHPC capability to the config space for the device. */
> > > > +static int shpc_cap_add_config(PCIDevice *d)
> > > > +{
> > > > + uint8_t *config;
> > > > + int config_offset;
> > > > + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
> > > > + 0, SHPC_CAP_LENGTH);
> > > > + if (config_offset < 0) {
> > > > + return config_offset;
> > > > + }
> > > > + config = d->config + config_offset;
> > > > +
> > > > + pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
> > > > + pci_set_byte(config + SHPC_CAP_CxP, 0);
> > > > + pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
> > > > + d->shpc->cap = config_offset;
> > > > + /* Make dword select and data writeable. */
> > > > + pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
> > > > + pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> > > > + unsigned size)
> > > > +{
> > > > + return shpc_read(opaque, addr, size);
> > > > +}
> > > > +
> > > > +static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> > > > + uint64_t val, unsigned size)
> > > > +{
> > > > + shpc_write(opaque, addr, val, size);
> > > > +}
> > > > +
> > > > +static const MemoryRegionOps shpc_mmio_ops = {
> > > > + .read = shpc_mmio_read,
> > > > + .write = shpc_mmio_write,
> > > > + .endianness = DEVICE_LITTLE_ENDIAN,
> > > > + .valid = {
> > > > + /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
> > > > + * It's easier to suppport all sizes than worry about it. */
> > > > + .min_access_size = 1,
> > > > + .max_access_size = 4,
> > > > + },
> > > > +};
> > > > +
> > > > +static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
> > > > + PCIHotplugState hotplug_state)
> > > > +{
> > > > + int pci_slot = PCI_SLOT(affected_dev->devfn);
> > > > + uint8_t state;
> > > > + uint8_t led;
> > > > + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + int slot = SHPC_PCI_TO_IDX(pci_slot);
> > > > + if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
> > > > + error_report("Unsupported PCI slot %d for standard hotplug "
> > > > + "controller. Valid slots are between %d and %d.",
> > > > + pci_slot, SHPC_IDX_TO_PCI(0),
> > > > + SHPC_IDX_TO_PCI(shpc->nslots) - 1);
> > > > + return -1;
> > > > + }
> > > > + /* Don't send event when device is enabled during qemu machine creation:
> > > > + * it is present on boot, no hotplug event is necessary. We do send an
> > > > + * event when the device is disabled later. */
> > > > + if (hotplug_state == PCI_COLDPLUG_ENABLED) {
> > > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + return 0;
> > > > + }
> > > > + if (hotplug_state == PCI_HOTPLUG_DISABLED) {
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
> > > > + state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
> > > > + led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
> > > > + if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
> > > > + shpc_free_devices_in_slot(shpc, slot);
> > > > + shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_PRESENCE;
> > > > + }
> > > > + } else {
> > > > + /* This could be a cancellation of the previous removal.
> > > > + * We check MRL state to figure out. */
> > > > + if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
> > > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
> > > > + shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
> > > > + SHPC_SLOT_STATUS_PRSNT_MASK);
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_PRESENCE;
> > > > + } else {
> > > > + /* Press attention button to cancel removal */
> > > > + shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
> > > > + SHPC_SLOT_EVENT_BUTTON;
> > > > + }
> > > > + }
> > > > + shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
> > > > + shpc_interrupt_update(d);
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/* Initialize the SHPC structure in bridge's BAR. */
> > > > +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
> > > > +{
> > > > + int i, ret;
> > > > + int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
> > > > + SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
> > > > + shpc->sec_bus = sec_bus;
> > > > + ret = shpc_cap_add_config(d);
> > > > + if (ret) {
> > > > + g_free(d->shpc);
> > > > + return ret;
> > > > + }
> > > > + if (nslots < SHPC_MIN_SLOTS) {
> > > > + return 0;
> > > > + }
> > > > + if (nslots > SHPC_MAX_SLOTS ||
> > > > + SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
> > > > + /* TODO: report an error mesage that makes sense. */
> > > > + return -EINVAL;
> > > > + }
> > > > + shpc->nslots = nslots;
> > > > + shpc->config = g_malloc0(SHPC_SIZEOF(d));
> > > > + shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
> > > > + shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
> > > > + shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
> > > > +
> > > > + shpc_reset(d);
> > > > +
> > > > + pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
> > > > +
> > > > + pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
> > > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > > + pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
> > > > + pci_set_long(shpc->wmask + SHPC_SERR_INT,
> > > > + SHPC_INT_DIS |
> > > > + SHPC_SERR_DIS |
> > > > + SHPC_CMD_INT_DIS |
> > > > + SHPC_ARB_SERR_DIS);
> > > > + pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
> > > > + SHPC_CMD_DETECTED |
> > > > + SHPC_ARB_DETECTED);
> > > > + for (i = 0; i < nslots; ++i) {
> > > > + pci_set_byte(shpc->wmask +
> > > > + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
> > > > + SHPC_SLOT_EVENT_PRESENCE |
> > > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT |
> > > > + SHPC_SLOT_EVENT_MRL_SERR_DIS |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
> > > > + pci_set_byte(shpc->w1cmask +
> > > > + SHPC_SLOT_EVENT_LATCH(i),
> > > > + SHPC_SLOT_EVENT_PRESENCE |
> > > > + SHPC_SLOT_EVENT_ISOLATED_FAULT |
> > > > + SHPC_SLOT_EVENT_BUTTON |
> > > > + SHPC_SLOT_EVENT_MRL |
> > > > + SHPC_SLOT_EVENT_CONNECTED_FAULT);
> > > > + }
> > > > +
> > > > + /* TODO: init cmask */
> > > > + memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
> > > > + SHPC_SIZEOF(d));
> > > > + shpc_cap_update_dword(d);
> > > > + memory_region_add_subregion(bar, offset, &shpc->mmio);
> > > > + pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int shpc_bar_size(PCIDevice *d)
> > > > +{
> > > > + return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
> > > > +}
> > > > +
> > > > +void shpc_cleanup(PCIDevice *d)
> > > > +{
> > > > + SHPCDevice *shpc = d->shpc;
> > > > + /* TODO: cleanup config space changes? */
> > > > + g_free(shpc->config);
> > > > + g_free(shpc->cmask);
> > > > + g_free(shpc->wmask);
> > > > + g_free(shpc->w1cmask);
> > > > + memory_region_destroy(&shpc->mmio);
> > > > + g_free(shpc);
> > > > +}
> > > > +
> > > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> > > > +{
> > > > + if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
> > > > + return;
> > > > + }
> > > > + fprintf(stderr, "%s: 0x%x 0x%x %d\n", __func__, addr, val, l);
> > > > + if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
> > > > + unsigned dword_data;
> > > > + dword_data = pci_get_long(d->shpc->config + d->shpc->cap
> > > > + + SHPC_CAP_DWORD_DATA);
> > > > + shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
> > > > + }
> > > > + /* Update cap dword data in case guest is going to read it. */
> > > > + shpc_cap_update_dword(d);
> > > > +}
> > > > diff --git a/hw/shpc.h b/hw/shpc.h
> > > > new file mode 100644
> > > > index 0000000..389b178
> > > > --- /dev/null
> > > > +++ b/hw/shpc.h
> > > > @@ -0,0 +1,40 @@
> > > > +#ifndef SHPC_H
> > > > +#define SHPC_H
> > > > +
> > > > +#include "qemu-common.h"
> > > > +#include "memory.h"
> > > > +
> > > > +struct SHPCDevice {
> > > > + /* Capability offset in device's config space */
> > > > + int cap;
> > > > +
> > > > + /* # of hot-pluggable slots */
> > > > + int nslots;
> > > > +
> > > > + /* SHPC WRS: working register set */
> > > > + uint8_t *config;
> > > > +
> > > > + /* Used to enable checks on load. Note that writable bits are
> > > > + * never checked even if set in cmask. */
> > > > + uint8_t *cmask;
> > > > +
> > > > + /* Used to implement R/W bytes */
> > > > + uint8_t *wmask;
> > > > +
> > > > + /* Used to implement RW1C(Write 1 to Clear) bytes */
> > > > + uint8_t *w1cmask;
> > > > +
> > > > + /* MMIO for the SHPC BAR */
> > > > + MemoryRegion mmio;
> > > > +
> > > > + /* Bus controlled by this SHPC */
> > > > + PCIBus *sec_bus;
> > > > +};
> > > > +
> > > > +void shpc_reset(PCIDevice *d);
> > > > +int shpc_bar_size(PCIDevice *dev);
> > > > +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset);
> > > > +void shpc_cleanup(PCIDevice *dev);
> > > > +void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
> > > > +
> > > > +#endif
> > > > diff --git a/qemu-common.h b/qemu-common.h
> > > > index 9b997f8..4ff9c95 100644
> > > > --- a/qemu-common.h
> > > > +++ b/qemu-common.h
> > > > @@ -247,6 +247,7 @@ typedef struct SSIBus SSIBus;
> > > > typedef struct EventNotifier EventNotifier;
> > > > typedef struct VirtIODevice VirtIODevice;
> > > > typedef struct QEMUSGList QEMUSGList;
> > > > +typedef struct SHPCDevice SHPCDevice;
> > > >
> > > > typedef uint64_t pcibus_t;
> > > >
> > > > --
> > > > 1.7.9.111.gf3fb0
> > > >
> > >
> > > --
> > > yamahata
> >
>
> --
> yamahata
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH RFC] seabios: add OSHP method stub
2012-02-13 9:33 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-14 0:34 ` Kevin O'Connor
-1 siblings, 0 replies; 52+ messages in thread
From: Kevin O'Connor @ 2012-02-14 0:34 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> To allow guests to load the native SHPC driver
> for a bridge, we must declare an OSHP method
> for the appropriate device which lets the OS
> take control of the SHPC.
> As we don't access SHPC at the moment, we
> don't need to do anything - just report success.
The patch is fine with me, but since this is really qemu/kvm specific,
please provide an ack from one of the qemu/kvm maintainers.
-Kevin
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 0:34 ` Kevin O'Connor
0 siblings, 0 replies; 52+ messages in thread
From: Kevin O'Connor @ 2012-02-14 0:34 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> To allow guests to load the native SHPC driver
> for a bridge, we must declare an OSHP method
> for the appropriate device which lets the OS
> take control of the SHPC.
> As we don't access SHPC at the moment, we
> don't need to do anything - just report success.
The patch is fine with me, but since this is really qemu/kvm specific,
please provide an ack from one of the qemu/kvm maintainers.
-Kevin
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH RFC] seabios: add OSHP method stub
2012-02-14 0:34 ` [Qemu-devel] " Kevin O'Connor
@ 2012-02-14 0:43 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 0:43 UTC (permalink / raw)
To: Kevin O'Connor
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
> On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> > To allow guests to load the native SHPC driver
> > for a bridge, we must declare an OSHP method
> > for the appropriate device which lets the OS
> > take control of the SHPC.
> > As we don't access SHPC at the moment, we
> > don't need to do anything - just report success.
>
> The patch is fine with me, but since this is really qemu/kvm specific,
> please provide an ack from one of the qemu/kvm maintainers.
>
> -Kevin
I expect no problem with this,
though I'm wondering what makes it qemu specific.
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 0:43 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 0:43 UTC (permalink / raw)
To: Kevin O'Connor
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
> On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> > To allow guests to load the native SHPC driver
> > for a bridge, we must declare an OSHP method
> > for the appropriate device which lets the OS
> > take control of the SHPC.
> > As we don't access SHPC at the moment, we
> > don't need to do anything - just report success.
>
> The patch is fine with me, but since this is really qemu/kvm specific,
> please provide an ack from one of the qemu/kvm maintainers.
>
> -Kevin
I expect no problem with this,
though I'm wondering what makes it qemu specific.
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH RFC] seabios: add OSHP method stub
2012-02-14 0:43 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-14 0:48 ` Kevin O'Connor
-1 siblings, 0 replies; 52+ messages in thread
From: Kevin O'Connor @ 2012-02-14 0:48 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Tue, Feb 14, 2012 at 02:43:45AM +0200, Michael S. Tsirkin wrote:
> On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
> > On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> > > To allow guests to load the native SHPC driver
> > > for a bridge, we must declare an OSHP method
> > > for the appropriate device which lets the OS
> > > take control of the SHPC.
> > > As we don't access SHPC at the moment, we
> > > don't need to do anything - just report success.
> >
> > The patch is fine with me, but since this is really qemu/kvm specific,
> > please provide an ack from one of the qemu/kvm maintainers.
> >
> > -Kevin
>
> I expect no problem with this,
> though I'm wondering what makes it qemu specific.
Only kvm/qemu use the ACPI tables in seabios.
In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
for an additional Ack.
-Kevin
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 0:48 ` Kevin O'Connor
0 siblings, 0 replies; 52+ messages in thread
From: Kevin O'Connor @ 2012-02-14 0:48 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Tue, Feb 14, 2012 at 02:43:45AM +0200, Michael S. Tsirkin wrote:
> On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
> > On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> > > To allow guests to load the native SHPC driver
> > > for a bridge, we must declare an OSHP method
> > > for the appropriate device which lets the OS
> > > take control of the SHPC.
> > > As we don't access SHPC at the moment, we
> > > don't need to do anything - just report success.
> >
> > The patch is fine with me, but since this is really qemu/kvm specific,
> > please provide an ack from one of the qemu/kvm maintainers.
> >
> > -Kevin
>
> I expect no problem with this,
> though I'm wondering what makes it qemu specific.
Only kvm/qemu use the ACPI tables in seabios.
In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
for an additional Ack.
-Kevin
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH RFC] seabios: add OSHP method stub
2012-02-14 0:48 ` [Qemu-devel] " Kevin O'Connor
@ 2012-02-14 1:09 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 1:09 UTC (permalink / raw)
To: Kevin O'Connor
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 07:48:37PM -0500, Kevin O'Connor wrote:
> On Tue, Feb 14, 2012 at 02:43:45AM +0200, Michael S. Tsirkin wrote:
> > On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
> > > On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> > > > To allow guests to load the native SHPC driver
> > > > for a bridge, we must declare an OSHP method
> > > > for the appropriate device which lets the OS
> > > > take control of the SHPC.
> > > > As we don't access SHPC at the moment, we
> > > > don't need to do anything - just report success.
> > >
> > > The patch is fine with me, but since this is really qemu/kvm specific,
> > > please provide an ack from one of the qemu/kvm maintainers.
> > >
> > > -Kevin
> >
> > I expect no problem with this,
> > though I'm wondering what makes it qemu specific.
>
> Only kvm/qemu use the ACPI tables in seabios.
>
> In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
> for an additional Ack.
>
> -Kevin
No problem, I'll get an Ack :)
Meanwhile - here's a summary, as far as I understand it.
Originally PCI SIG only defined the electrical
and mechanical requirements from hotplug, no standard
software interface. So it needed ACPI to drive device-specific registers
to actually do hotplug.
At some point PCISIG defined standard interfaces
for PCI hotplug. There are two of them: standard
hot plug controller (SHPC) for PCI and PCIE hotplug
for Express.
Now an OS can have a standard driver and use it
to activate hotplug functionality. This is OS hotplug (OSHP).
But what about older OSes that do not have this
driver? ACPI can support these by driving
the SHPC interface itself. This will work but
then it can conflict with the new driver in the OS.
To solve the problem, OS tells ACPI to leave SHPC
alone. There are two things OS tries to activate to do this,
in this order:
1. _OSC for global switch to native SHPC driver
2. OSHP for switch on the given bridge device
If none of the above are present, or if they fail,
OS assumes ACPI wants control of the SHPC registers
and won't touch them.
Hope above makes sense.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 1:09 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 1:09 UTC (permalink / raw)
To: Kevin O'Connor
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
On Mon, Feb 13, 2012 at 07:48:37PM -0500, Kevin O'Connor wrote:
> On Tue, Feb 14, 2012 at 02:43:45AM +0200, Michael S. Tsirkin wrote:
> > On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
> > > On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
> > > > To allow guests to load the native SHPC driver
> > > > for a bridge, we must declare an OSHP method
> > > > for the appropriate device which lets the OS
> > > > take control of the SHPC.
> > > > As we don't access SHPC at the moment, we
> > > > don't need to do anything - just report success.
> > >
> > > The patch is fine with me, but since this is really qemu/kvm specific,
> > > please provide an ack from one of the qemu/kvm maintainers.
> > >
> > > -Kevin
> >
> > I expect no problem with this,
> > though I'm wondering what makes it qemu specific.
>
> Only kvm/qemu use the ACPI tables in seabios.
>
> In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
> for an additional Ack.
>
> -Kevin
No problem, I'll get an Ack :)
Meanwhile - here's a summary, as far as I understand it.
Originally PCI SIG only defined the electrical
and mechanical requirements from hotplug, no standard
software interface. So it needed ACPI to drive device-specific registers
to actually do hotplug.
At some point PCISIG defined standard interfaces
for PCI hotplug. There are two of them: standard
hot plug controller (SHPC) for PCI and PCIE hotplug
for Express.
Now an OS can have a standard driver and use it
to activate hotplug functionality. This is OS hotplug (OSHP).
But what about older OSes that do not have this
driver? ACPI can support these by driving
the SHPC interface itself. This will work but
then it can conflict with the new driver in the OS.
To solve the problem, OS tells ACPI to leave SHPC
alone. There are two things OS tries to activate to do this,
in this order:
1. _OSC for global switch to native SHPC driver
2. OSHP for switch on the given bridge device
If none of the above are present, or if they fail,
OS assumes ACPI wants control of the SHPC registers
and won't touch them.
Hope above makes sense.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH RFC] seabios: add OSHP method stub
2012-02-14 1:09 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-14 12:49 ` Paul Brook
-1 siblings, 0 replies; 52+ messages in thread
From: Paul Brook @ 2012-02-14 12:49 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, kvm, Michael S. Tsirkin, seabios, Isaku Yamahata,
Kevin O'Connor, Avi Kivity
> > In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
> > for an additional Ack.
>
> No problem, I'll get an Ack :)
> Meanwhile - here's a summary, as far as I understand it.
>
> Originally PCI SIG only defined the electrical
> and mechanical requirements from hotplug, no standard
> software interface. So it needed ACPI to drive device-specific registers
> to actually do hotplug.
> At some point PCISIG defined standard interfaces
> for PCI hotplug. There are two of them: standard
> hot plug controller (SHPC) for PCI and PCIE hotplug
> for Express.
>
> Now an OS can have a standard driver and use it
> to activate hotplug functionality. This is OS hotplug (OSHP).
So presumably this will work on targets that don't have ACPI?
Assuming a competent guest OS of course. Have you tested this?
Paul
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 12:49 ` Paul Brook
0 siblings, 0 replies; 52+ messages in thread
From: Paul Brook @ 2012-02-14 12:49 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, kvm, Michael S. Tsirkin, seabios, Isaku Yamahata,
Kevin O'Connor, Avi Kivity
> > In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
> > for an additional Ack.
>
> No problem, I'll get an Ack :)
> Meanwhile - here's a summary, as far as I understand it.
>
> Originally PCI SIG only defined the electrical
> and mechanical requirements from hotplug, no standard
> software interface. So it needed ACPI to drive device-specific registers
> to actually do hotplug.
> At some point PCISIG defined standard interfaces
> for PCI hotplug. There are two of them: standard
> hot plug controller (SHPC) for PCI and PCIE hotplug
> for Express.
>
> Now an OS can have a standard driver and use it
> to activate hotplug functionality. This is OS hotplug (OSHP).
So presumably this will work on targets that don't have ACPI?
Assuming a competent guest OS of course. Have you tested this?
Paul
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH RFC] seabios: add OSHP method stub
2012-02-14 12:49 ` [Qemu-devel] " Paul Brook
@ 2012-02-14 13:37 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 13:37 UTC (permalink / raw)
To: Paul Brook
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata,
Kevin O'Connor, Avi Kivity
On Tue, Feb 14, 2012 at 12:49:08PM +0000, Paul Brook wrote:
> > > In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
> > > for an additional Ack.
> >
> > No problem, I'll get an Ack :)
> > Meanwhile - here's a summary, as far as I understand it.
> >
> > Originally PCI SIG only defined the electrical
> > and mechanical requirements from hotplug, no standard
> > software interface. So it needed ACPI to drive device-specific registers
> > to actually do hotplug.
> > At some point PCISIG defined standard interfaces
> > for PCI hotplug. There are two of them: standard
> > hot plug controller (SHPC) for PCI and PCIE hotplug
> > for Express.
> >
> > Now an OS can have a standard driver and use it
> > to activate hotplug functionality. This is OS hotplug (OSHP).
>
> So presumably this will work on targets that don't have ACPI?
> Assuming a competent guest OS of course. Have you tested this?
>
> Paul
This being the qemu side of things? I run Linux
and verified that it calls OSHP and afterwards,
runs the native driver and handles hotplug/unplug
without invoking ACPI at all.
It seems that at least the SHPC driver in linux
doesn't work if you don't have an acpi table
with the OSHP method - not many people run with acpi=off
nowdays, so it's probably just a bug.
I'll check how hard it is to fix this.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 13:37 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 13:37 UTC (permalink / raw)
To: Paul Brook
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata,
Kevin O'Connor, Avi Kivity
On Tue, Feb 14, 2012 at 12:49:08PM +0000, Paul Brook wrote:
> > > In a nutshell, I don't know what a SHPC is (nor OSHP), so I'm looking
> > > for an additional Ack.
> >
> > No problem, I'll get an Ack :)
> > Meanwhile - here's a summary, as far as I understand it.
> >
> > Originally PCI SIG only defined the electrical
> > and mechanical requirements from hotplug, no standard
> > software interface. So it needed ACPI to drive device-specific registers
> > to actually do hotplug.
> > At some point PCISIG defined standard interfaces
> > for PCI hotplug. There are two of them: standard
> > hot plug controller (SHPC) for PCI and PCIE hotplug
> > for Express.
> >
> > Now an OS can have a standard driver and use it
> > to activate hotplug functionality. This is OS hotplug (OSHP).
>
> So presumably this will work on targets that don't have ACPI?
> Assuming a competent guest OS of course. Have you tested this?
>
> Paul
This being the qemu side of things? I run Linux
and verified that it calls OSHP and afterwards,
runs the native driver and handles hotplug/unplug
without invoking ACPI at all.
It seems that at least the SHPC driver in linux
doesn't work if you don't have an acpi table
with the OSHP method - not many people run with acpi=off
nowdays, so it's probably just a bug.
I'll check how hard it is to fix this.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
2012-02-14 13:37 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-14 13:47 ` Paul Brook
-1 siblings, 0 replies; 52+ messages in thread
From: Paul Brook @ 2012-02-14 13:47 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qemu-devel, Kevin O'Connor, Kevin Wolf, kvm, seabios,
Isaku Yamahata, Avi Kivity
> > > Now an OS can have a standard driver and use it
> > > to activate hotplug functionality. This is OS hotplug (OSHP).
> >
> > So presumably this will work on targets that don't have ACPI?
> > Assuming a competent guest OS of course. Have you tested this?
>
> This being the qemu side of things? I run Linux
> and verified that it calls OSHP and afterwards,
> runs the native driver and handles hotplug/unplug
> without invoking ACPI at all.
I mean using your shiny new hotplug PCI-PCI bridge on arm/ppc/mips targets
(i.e anything other than x86 PC). From your description it sounds like it
*should* work.
> It seems that at least the SHPC driver in linux
> doesn't work if you don't have an acpi table
> with the OSHP method - not many people run with acpi=off
> nowdays, so it's probably just a bug.
> I'll check how hard it is to fix this.
Targets other than x86 don't have ACPI to start with.
Paul
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 13:47 ` Paul Brook
0 siblings, 0 replies; 52+ messages in thread
From: Paul Brook @ 2012-02-14 13:47 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata,
Kevin O'Connor, Avi Kivity
> > > Now an OS can have a standard driver and use it
> > > to activate hotplug functionality. This is OS hotplug (OSHP).
> >
> > So presumably this will work on targets that don't have ACPI?
> > Assuming a competent guest OS of course. Have you tested this?
>
> This being the qemu side of things? I run Linux
> and verified that it calls OSHP and afterwards,
> runs the native driver and handles hotplug/unplug
> without invoking ACPI at all.
I mean using your shiny new hotplug PCI-PCI bridge on arm/ppc/mips targets
(i.e anything other than x86 PC). From your description it sounds like it
*should* work.
> It seems that at least the SHPC driver in linux
> doesn't work if you don't have an acpi table
> with the OSHP method - not many people run with acpi=off
> nowdays, so it's probably just a bug.
> I'll check how hard it is to fix this.
Targets other than x86 don't have ACPI to start with.
Paul
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
2012-02-14 13:47 ` Paul Brook
@ 2012-02-14 14:11 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 14:11 UTC (permalink / raw)
To: Paul Brook
Cc: qemu-devel, Kevin O'Connor, Kevin Wolf, kvm, seabios,
Isaku Yamahata, Avi Kivity
On Tue, Feb 14, 2012 at 01:47:59PM +0000, Paul Brook wrote:
> > > > Now an OS can have a standard driver and use it
> > > > to activate hotplug functionality. This is OS hotplug (OSHP).
> > >
> > > So presumably this will work on targets that don't have ACPI?
> > > Assuming a competent guest OS of course. Have you tested this?
> >
> > This being the qemu side of things? I run Linux
> > and verified that it calls OSHP and afterwards,
> > runs the native driver and handles hotplug/unplug
> > without invoking ACPI at all.
>
> I mean using your shiny new hotplug PCI-PCI bridge on arm/ppc/mips targets
> (i.e anything other than x86 PC). From your description it sounds like it
> *should* work.
>
> > It seems that at least the SHPC driver in linux
> > doesn't work if you don't have an acpi table
> > with the OSHP method - not many people run with acpi=off
> > nowdays, so it's probably just a bug.
> > I'll check how hard it is to fix this.
>
> Targets other than x86 don't have ACPI to start with.
>
> Paul
So
#ifdef CONFIG_ACPI
#include <linux/pci-acpi.h>
static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
{
u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
return acpi_get_hp_hw_control_from_firmware(dev, flags);
}
#else
#define get_hp_hw_control_from_firmware(dev) (0)
#endif
So if you build your guest without acpi, things should work fine.
--
MMST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-14 14:11 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-14 14:11 UTC (permalink / raw)
To: Paul Brook
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata,
Kevin O'Connor, Avi Kivity
On Tue, Feb 14, 2012 at 01:47:59PM +0000, Paul Brook wrote:
> > > > Now an OS can have a standard driver and use it
> > > > to activate hotplug functionality. This is OS hotplug (OSHP).
> > >
> > > So presumably this will work on targets that don't have ACPI?
> > > Assuming a competent guest OS of course. Have you tested this?
> >
> > This being the qemu side of things? I run Linux
> > and verified that it calls OSHP and afterwards,
> > runs the native driver and handles hotplug/unplug
> > without invoking ACPI at all.
>
> I mean using your shiny new hotplug PCI-PCI bridge on arm/ppc/mips targets
> (i.e anything other than x86 PC). From your description it sounds like it
> *should* work.
>
> > It seems that at least the SHPC driver in linux
> > doesn't work if you don't have an acpi table
> > with the OSHP method - not many people run with acpi=off
> > nowdays, so it's probably just a bug.
> > I'll check how hard it is to fix this.
>
> Targets other than x86 don't have ACPI to start with.
>
> Paul
So
#ifdef CONFIG_ACPI
#include <linux/pci-acpi.h>
static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
{
u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
return acpi_get_hp_hw_control_from_firmware(dev, flags);
}
#else
#define get_hp_hw_control_from_firmware(dev) (0)
#endif
So if you build your guest without acpi, things should work fine.
--
MMST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 1/2] shpc: standard hot plug controller
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-17 13:20 ` Gerd Hoffmann
-1 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-17 13:20 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On 02/13/12 10:15, Michael S. Tsirkin wrote:
> TODO:
> - migration support
> - fix dependency on pci_internals.h
fix checkpatch warnings
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 1/2] shpc: standard hot plug controller
@ 2012-02-17 13:20 ` Gerd Hoffmann
0 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-17 13:20 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On 02/13/12 10:15, Michael S. Tsirkin wrote:
> TODO:
> - migration support
> - fix dependency on pci_internals.h
fix checkpatch warnings
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-13 9:16 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-17 13:25 ` Gerd Hoffmann
-1 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-17 13:25 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
Hi,
> + /* If we don't specify the name, the bus will be addressed as <id>.0, where
> + * id is the parent id. But it seems more natural to address the bus using
> + * the parent device name. */
> + if (dev->qdev.id && *dev->qdev.id) {
> + br->bus_name = dev->qdev.id;
> + }
That makes the bridge behave different than everybody else.
Not a good idea IMHO.
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-17 13:25 ` Gerd Hoffmann
0 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-17 13:25 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
Hi,
> + /* If we don't specify the name, the bus will be addressed as <id>.0, where
> + * id is the parent id. But it seems more natural to address the bus using
> + * the parent device name. */
> + if (dev->qdev.id && *dev->qdev.id) {
> + br->bus_name = dev->qdev.id;
> + }
That makes the bridge behave different than everybody else.
Not a good idea IMHO.
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-13 9:16 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-17 13:33 ` Gerd Hoffmann
-1 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-17 13:33 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On 02/13/12 10:16, Michael S. Tsirkin wrote:
> This adds support for a standard pci to pci bridge,
> enabling support for more than 32 PCI devices in the system.
> Device hotplug is supported by means of SHPC controller.
> For guests with an SHPC driver, this allows robust hotplug
> and even hotplug of nested bridges, up to 31 devices
> per bridge.
This seems to not support 64bit prefetchable memory windows, at least
linux doesn't think it does, lspci looks like this:
00:10.0 PCI bridge: Red Hat, Inc. Device 0001 (prog-if 00 [Normal decode])
Physical Slot: 16
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Region 0: Memory at f6126000 (32-bit, non-prefetchable) [size=256]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: f6000000-f60fffff
Prefetchable memory behind bridge: f8000000-fbffffff
Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Hot-plug capable
Kernel modules: shpchp
Intentional?
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-17 13:33 ` Gerd Hoffmann
0 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-17 13:33 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On 02/13/12 10:16, Michael S. Tsirkin wrote:
> This adds support for a standard pci to pci bridge,
> enabling support for more than 32 PCI devices in the system.
> Device hotplug is supported by means of SHPC controller.
> For guests with an SHPC driver, this allows robust hotplug
> and even hotplug of nested bridges, up to 31 devices
> per bridge.
This seems to not support 64bit prefetchable memory windows, at least
linux doesn't think it does, lspci looks like this:
00:10.0 PCI bridge: Red Hat, Inc. Device 0001 (prog-if 00 [Normal decode])
Physical Slot: 16
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Region 0: Memory at f6126000 (32-bit, non-prefetchable) [size=256]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: f6000000-f60fffff
Prefetchable memory behind bridge: f8000000-fbffffff
Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Hot-plug capable
Kernel modules: shpchp
Intentional?
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-17 13:25 ` [Qemu-devel] " Gerd Hoffmann
@ 2012-02-19 14:57 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-19 14:57 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On Fri, Feb 17, 2012 at 02:25:56PM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > + /* If we don't specify the name, the bus will be addressed as <id>.0, where
> > + * id is the parent id. But it seems more natural to address the bus using
> > + * the parent device name. */
> > + if (dev->qdev.id && *dev->qdev.id) {
> > + br->bus_name = dev->qdev.id;
> > + }
>
> That makes the bridge behave different than everybody else.
> Not a good idea IMHO.
>
> cheers,
> Gerd
Everybody else has names built up according to an undocumented scheme
which no one can figure out without reading code, so no one uses them.
We need to fix that, but there is, generally, no need for these names
so it stayed low priority.
With the bridge people must use the id to connect devices to it,
so name must be a sane one.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-19 14:57 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-19 14:57 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On Fri, Feb 17, 2012 at 02:25:56PM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > + /* If we don't specify the name, the bus will be addressed as <id>.0, where
> > + * id is the parent id. But it seems more natural to address the bus using
> > + * the parent device name. */
> > + if (dev->qdev.id && *dev->qdev.id) {
> > + br->bus_name = dev->qdev.id;
> > + }
>
> That makes the bridge behave different than everybody else.
> Not a good idea IMHO.
>
> cheers,
> Gerd
Everybody else has names built up according to an undocumented scheme
which no one can figure out without reading code, so no one uses them.
We need to fix that, but there is, generally, no need for these names
so it stayed low priority.
With the bridge people must use the id to connect devices to it,
so name must be a sane one.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-19 14:57 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-19 23:44 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-19 23:44 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel, kvm, Kevin Wolf, Isaku Yamahata, Avi Kivity
On Sun, Feb 19, 2012 at 04:57:07PM +0200, Michael S. Tsirkin wrote:
> On Fri, Feb 17, 2012 at 02:25:56PM +0100, Gerd Hoffmann wrote:
> > Hi,
> >
> > > + /* If we don't specify the name, the bus will be addressed as <id>.0, where
> > > + * id is the parent id. But it seems more natural to address the bus using
> > > + * the parent device name. */
> > > + if (dev->qdev.id && *dev->qdev.id) {
> > > + br->bus_name = dev->qdev.id;
> > > + }
> >
> > That makes the bridge behave different than everybody else.
> > Not a good idea IMHO.
> >
> > cheers,
> > Gerd
>
> Everybody else has names built up according to an undocumented scheme
> which no one can figure out without reading code, so no one uses them.
> We need to fix that, but there is, generally, no need for these names
> so it stayed low priority.
>
> With the bridge people must use the id to connect devices to it,
> so name must be a sane one.
I just sent the patch making bus id for bridges
follow the value set by the user.
That will make the bridge behave in the same way
as everybody else :)
> --
> MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-19 23:44 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-19 23:44 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On Sun, Feb 19, 2012 at 04:57:07PM +0200, Michael S. Tsirkin wrote:
> On Fri, Feb 17, 2012 at 02:25:56PM +0100, Gerd Hoffmann wrote:
> > Hi,
> >
> > > + /* If we don't specify the name, the bus will be addressed as <id>.0, where
> > > + * id is the parent id. But it seems more natural to address the bus using
> > > + * the parent device name. */
> > > + if (dev->qdev.id && *dev->qdev.id) {
> > > + br->bus_name = dev->qdev.id;
> > > + }
> >
> > That makes the bridge behave different than everybody else.
> > Not a good idea IMHO.
> >
> > cheers,
> > Gerd
>
> Everybody else has names built up according to an undocumented scheme
> which no one can figure out without reading code, so no one uses them.
> We need to fix that, but there is, generally, no need for these names
> so it stayed low priority.
>
> With the bridge people must use the id to connect devices to it,
> so name must be a sane one.
I just sent the patch making bus id for bridges
follow the value set by the user.
That will make the bridge behave in the same way
as everybody else :)
> --
> MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-17 13:33 ` [Qemu-devel] " Gerd Hoffmann
@ 2012-02-20 22:40 ` Michael S. Tsirkin
-1 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-20 22:40 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel, kvm, Kevin Wolf, Isaku Yamahata, Avi Kivity
On Fri, Feb 17, 2012 at 02:33:42PM +0100, Gerd Hoffmann wrote:
> On 02/13/12 10:16, Michael S. Tsirkin wrote:
> > This adds support for a standard pci to pci bridge,
> > enabling support for more than 32 PCI devices in the system.
> > Device hotplug is supported by means of SHPC controller.
> > For guests with an SHPC driver, this allows robust hotplug
> > and even hotplug of nested bridges, up to 31 devices
> > per bridge.
>
> This seems to not support 64bit prefetchable memory windows, at least
> linux doesn't think it does, lspci looks like this:
>
> 00:10.0 PCI bridge: Red Hat, Inc. Device 0001 (prog-if 00 [Normal decode])
> Physical Slot: 16
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx-
> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0
> Region 0: Memory at f6126000 (32-bit, non-prefetchable) [size=256]
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> Memory behind bridge: f6000000-f60fffff
> Prefetchable memory behind bridge: f8000000-fbffffff
> Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- <SERR- <PERR-
> BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> Capabilities: [40] Hot-plug capable
> Kernel modules: shpchp
>
> Intentional?
>
> cheers,
> Gerd
I'll need to check. v3 I am sending out has this code unchanged.
What in the above tells you that 64 bit windows are not supported?
BAR0 is 32 bit non prefetcheable. As far as I can see linux driver
takes no precautions against access combining that can
happen with prefetcheable BARs, so non-prefetcheable
seems safer. I could make it 64 bit I guess, I just heard that
there is some known bug being worked around in
memory region code triggered somehow by 64 bit, and
waiting for the dust to settle.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-20 22:40 ` Michael S. Tsirkin
0 siblings, 0 replies; 52+ messages in thread
From: Michael S. Tsirkin @ 2012-02-20 22:40 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
On Fri, Feb 17, 2012 at 02:33:42PM +0100, Gerd Hoffmann wrote:
> On 02/13/12 10:16, Michael S. Tsirkin wrote:
> > This adds support for a standard pci to pci bridge,
> > enabling support for more than 32 PCI devices in the system.
> > Device hotplug is supported by means of SHPC controller.
> > For guests with an SHPC driver, this allows robust hotplug
> > and even hotplug of nested bridges, up to 31 devices
> > per bridge.
>
> This seems to not support 64bit prefetchable memory windows, at least
> linux doesn't think it does, lspci looks like this:
>
> 00:10.0 PCI bridge: Red Hat, Inc. Device 0001 (prog-if 00 [Normal decode])
> Physical Slot: 16
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx-
> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0
> Region 0: Memory at f6126000 (32-bit, non-prefetchable) [size=256]
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> Memory behind bridge: f6000000-f60fffff
> Prefetchable memory behind bridge: f8000000-fbffffff
> Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- <SERR- <PERR-
> BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> Capabilities: [40] Hot-plug capable
> Kernel modules: shpchp
>
> Intentional?
>
> cheers,
> Gerd
I'll need to check. v3 I am sending out has this code unchanged.
What in the above tells you that 64 bit windows are not supported?
BAR0 is 32 bit non prefetcheable. As far as I can see linux driver
takes no precautions against access combining that can
happen with prefetcheable BARs, so non-prefetcheable
seems safer. I could make it 64 bit I guess, I just heard that
there is some known bug being worked around in
memory region code triggered somehow by 64 bit, and
waiting for the dust to settle.
--
MST
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCHv2-RFC 2/2] pci: add standard bridge device
2012-02-20 22:40 ` Michael S. Tsirkin
@ 2012-02-21 8:02 ` Gerd Hoffmann
-1 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-21 8:02 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
Hi,
>> This seems to not support 64bit prefetchable memory windows, at least
>> linux doesn't think it does, lspci looks like this:
>>
>> 00:10.0 PCI bridge: Red Hat, Inc. Device 0001 (prog-if 00 [Normal decode])
[ ... ]
>> Memory behind bridge: f6000000-f60fffff
>> Prefetchable memory behind bridge: f8000000-fbffffff
> What in the above tells you that 64 bit windows are not supported?
lspci prints 64bit addresses then, like this:
00:1c.0 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express
Port 1 (rev 03) (prog-if 00 [Normal decode])
[ ... ]
I/O behind bridge: 00008000-00008fff
Memory behind bridge: c0000000-c01fffff
Prefetchable memory behind bridge: 00000000c0200000-00000000c03fffff
> BAR0 is 32 bit non prefetcheable. As far as I can see linux driver
> takes no precautions against access combining that can
> happen with prefetcheable BARs, so non-prefetcheable
> seems safer.
I'm not talking about bar #0, but about the prefetchable memory window
for devices behind the bridge.
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCHv2-RFC 2/2] pci: add standard bridge device
@ 2012-02-21 8:02 ` Gerd Hoffmann
0 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-21 8:02 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, Isaku Yamahata, qemu-devel, kvm, Avi Kivity
Hi,
>> This seems to not support 64bit prefetchable memory windows, at least
>> linux doesn't think it does, lspci looks like this:
>>
>> 00:10.0 PCI bridge: Red Hat, Inc. Device 0001 (prog-if 00 [Normal decode])
[ ... ]
>> Memory behind bridge: f6000000-f60fffff
>> Prefetchable memory behind bridge: f8000000-fbffffff
> What in the above tells you that 64 bit windows are not supported?
lspci prints 64bit addresses then, like this:
00:1c.0 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express
Port 1 (rev 03) (prog-if 00 [Normal decode])
[ ... ]
I/O behind bridge: 00008000-00008fff
Memory behind bridge: c0000000-c01fffff
Prefetchable memory behind bridge: 00000000c0200000-00000000c03fffff
> BAR0 is 32 bit non prefetcheable. As far as I can see linux driver
> takes no precautions against access combining that can
> happen with prefetcheable BARs, so non-prefetcheable
> seems safer.
I'm not talking about bar #0, but about the prefetchable memory window
for devices behind the bridge.
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [SeaBIOS] [PATCH RFC] seabios: add OSHP method stub
2012-02-13 9:33 ` [Qemu-devel] " Michael S. Tsirkin
@ 2012-02-29 11:25 ` Gerd Hoffmann
-1 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-29 11:25 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
> diff --git a/src/ssdt-pcihp.dsl b/src/ssdt-pcihp.dsl
> index 442e7a8..3f50169 100644
> --- a/src/ssdt-pcihp.dsl
> +++ b/src/ssdt-pcihp.dsl
> @@ -24,6 +24,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
> ACPI_EXTRACT_METHOD_STRING aml_ej0_name \
> Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \
> Name (_SUN, 0x##slot) \
> + Method (OSHP, 1) { Return(0x0) } \
> }
Linux kernel (kernel-3.2.7-1.fc16.x86_64) complains:
ACPI Warning: For \_SB_.PCI0.S10_.OSHP: Insufficient arguments - needs
1, found 0 (20110623/nspredef-321)
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [SeaBIOS] [PATCH RFC] seabios: add OSHP method stub
@ 2012-02-29 11:25 ` Gerd Hoffmann
0 siblings, 0 replies; 52+ messages in thread
From: Gerd Hoffmann @ 2012-02-29 11:25 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Kevin Wolf, kvm, seabios, qemu-devel, Isaku Yamahata, Avi Kivity
> diff --git a/src/ssdt-pcihp.dsl b/src/ssdt-pcihp.dsl
> index 442e7a8..3f50169 100644
> --- a/src/ssdt-pcihp.dsl
> +++ b/src/ssdt-pcihp.dsl
> @@ -24,6 +24,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
> ACPI_EXTRACT_METHOD_STRING aml_ej0_name \
> Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \
> Name (_SUN, 0x##slot) \
> + Method (OSHP, 1) { Return(0x0) } \
> }
Linux kernel (kernel-3.2.7-1.fc16.x86_64) complains:
ACPI Warning: For \_SB_.PCI0.S10_.OSHP: Insufficient arguments - needs
1, found 0 (20110623/nspredef-321)
cheers,
Gerd
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2012-02-29 11:25 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-02-13 9:15 [PATCHv2-RFC 0/2] RFC: standard pci bridge device Michael S. Tsirkin
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-13 9:15 ` [PATCHv2-RFC 1/2] shpc: standard hot plug controller Michael S. Tsirkin
2012-02-13 9:15 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-13 10:03 ` Isaku Yamahata
2012-02-13 10:03 ` [Qemu-devel] " Isaku Yamahata
2012-02-13 11:49 ` Michael S. Tsirkin
2012-02-13 11:49 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-13 14:30 ` Isaku Yamahata
2012-02-13 14:30 ` [Qemu-devel] " Isaku Yamahata
2012-02-13 14:49 ` Michael S. Tsirkin
2012-02-13 14:49 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-17 13:20 ` Gerd Hoffmann
2012-02-17 13:20 ` [Qemu-devel] " Gerd Hoffmann
2012-02-13 9:16 ` [PATCHv2-RFC 2/2] pci: add standard bridge device Michael S. Tsirkin
2012-02-13 9:16 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-17 13:25 ` Gerd Hoffmann
2012-02-17 13:25 ` [Qemu-devel] " Gerd Hoffmann
2012-02-19 14:57 ` Michael S. Tsirkin
2012-02-19 14:57 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-19 23:44 ` Michael S. Tsirkin
2012-02-19 23:44 ` Michael S. Tsirkin
2012-02-17 13:33 ` Gerd Hoffmann
2012-02-17 13:33 ` [Qemu-devel] " Gerd Hoffmann
2012-02-20 22:40 ` Michael S. Tsirkin
2012-02-20 22:40 ` Michael S. Tsirkin
2012-02-21 8:02 ` Gerd Hoffmann
2012-02-21 8:02 ` [Qemu-devel] " Gerd Hoffmann
2012-02-13 9:33 ` [PATCH RFC] seabios: add OSHP method stub Michael S. Tsirkin
2012-02-13 9:33 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-14 0:34 ` Kevin O'Connor
2012-02-14 0:34 ` [Qemu-devel] " Kevin O'Connor
2012-02-14 0:43 ` Michael S. Tsirkin
2012-02-14 0:43 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-14 0:48 ` Kevin O'Connor
2012-02-14 0:48 ` [Qemu-devel] " Kevin O'Connor
2012-02-14 1:09 ` Michael S. Tsirkin
2012-02-14 1:09 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-14 12:49 ` Paul Brook
2012-02-14 12:49 ` [Qemu-devel] " Paul Brook
2012-02-14 13:37 ` Michael S. Tsirkin
2012-02-14 13:37 ` [Qemu-devel] " Michael S. Tsirkin
2012-02-14 13:47 ` Paul Brook
2012-02-14 13:47 ` Paul Brook
2012-02-14 14:11 ` Michael S. Tsirkin
2012-02-14 14:11 ` Michael S. Tsirkin
2012-02-29 11:25 ` [SeaBIOS] " Gerd Hoffmann
2012-02-29 11:25 ` [Qemu-devel] " Gerd Hoffmann
2012-02-13 9:38 ` [PATCHv2-RFC 0/2] RFC: standard pci bridge device Wen Congyang
2012-02-13 9:38 ` [Qemu-devel] " Wen Congyang
2012-02-13 9:56 ` Michael S. Tsirkin
2012-02-13 9:56 ` [Qemu-devel] " Michael S. Tsirkin
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